[Intel-gfx] [PATCH 38/41] drm/i915: Defer setting of global seqno on request to submission

[Chris Wilson]

Defer the assignment of the global seqno on a request to its submission.
In the next patch, we will only allocate the global seqno at that time,
here we are just enabling the wait-for-submission before wait-for-seqno
paths.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_request.c  | 30 +++---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 12 
 2 files changed, 31 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 0e4b03c23b49..e6d6da8370fa 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -324,14 +324,32 @@ submit_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)
struct drm_i915_gem_request *request =
container_of(fence, typeof(*request), submit);
struct intel_engine_cs *engine = request->engine;
+   struct intel_timeline *timeline;
+   u32 seqno;
 
if (state != FENCE_COMPLETE)
return NOTIFY_DONE;
 
/* Will be called from irq-context when using foreign DMA fences */
 
-   engine->timeline->last_submitted_seqno = request->fence.seqno;
+   timeline = request->timeline;
 
+   seqno = request->fence.seqno;
+   GEM_BUG_ON(!seqno);
+   GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
+
+   GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno, seqno));
+   request->previous_seqno = timeline->last_submitted_seqno;
+   timeline->last_submitted_seqno = seqno;
+
+   /* We may be recursing from the signal callback of another i915 fence */
+   spin_lock_nested(>lock, SINGLE_DEPTH_NESTING);
+   request->global_seqno = seqno;
+   if (test_bit(FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
+   intel_engine_enable_signaling(request);
+   spin_unlock(>lock);
+
+   GEM_BUG_ON(!request->global_seqno);
engine->emit_breadcrumb(request,
request->ring->vaddr + request->postfix);
engine->submit_request(request);
@@ -427,10 +445,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
INIT_LIST_HEAD(>active_list);
req->i915 = dev_priv;
req->engine = engine;
-   req->global_seqno = req->fence.seqno;
req->ctx = i915_gem_context_get(ctx);
 
/* No zalloc, must clear what we need by hand */
+   req->global_seqno = 0;
req->previous_context = NULL;
req->file_priv = NULL;
req->batch = NULL;
@@ -704,15 +722,13 @@ void __i915_add_request(struct drm_i915_gem_request 
*request, bool flush_caches)
i915_sw_fence_await_sw_fence(>submit, >submit,
 >submitq);
 
-   GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno,
-request->fence.seqno));
+   list_add_tail(>link, >requests);
 
-   request->emitted_jiffies = jiffies;
-   request->previous_seqno = timeline->last_pending_seqno;
timeline->last_pending_seqno = request->fence.seqno;
i915_gem_active_set(>last_request, request);
-   list_add_tail(>link, >requests);
+
list_add_tail(>ring_link, >request_list);
+   request->emitted_jiffies = jiffies;
 
i915_gem_mark_busy(engine);
 
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 7e65b415c535..594676363056 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -77,22 +77,26 @@ static void intel_breadcrumbs_fake_irq(unsigned long data)
 
 static void irq_enable(struct intel_engine_cs *engine)
 {
+   unsigned long flags;
+
/* Enabling the IRQ may miss the generation of the interrupt, but
 * we still need to force the barrier before reading the seqno,
 * just in case.
 */
engine->breadcrumbs.irq_posted = true;
 
-   spin_lock_irq(>i915->irq_lock);
+   spin_lock_irqsave(>i915->irq_lock, flags);
engine->irq_enable(engine);
-   spin_unlock_irq(>i915->irq_lock);
+   spin_unlock_irqrestore(>i915->irq_lock, flags);
 }
 
 static void irq_disable(struct intel_engine_cs *engine)
 {
-   spin_lock_irq(>i915->irq_lock);
+   unsigned long flags;
+
+   spin_lock_irqsave(>i915->irq_lock, flags);
engine->irq_disable(engine);
-   spin_unlock_irq(>i915->irq_lock);
+   spin_unlock_irqrestore(>i915->irq_lock, flags);
 
engine->breadcrumbs.irq_posted = false;
 }
-- 
2.9.3

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Re: [Intel-gfx] [PATCH 38/41] drm/i915: Defer setting of global seqno on request to submission

[Joonas Lahtinen]

On pe, 2016-10-14 at 13:18 +0100, Chris Wilson wrote:
> Defer the assignment of the global seqno on a request to its submission.
> In the next patch, we will only allocate the global seqno at that time,
> here we are just enabling the wait-for-submission before wait-for-seqno
> paths.
> 
> Signed-off-by: Chris Wilson 

This was already;

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH 38/41] drm/i915: Defer setting of global seqno on request to submission

[Chris Wilson]

Defer the assignment of the global seqno on a request to its submission.
In the next patch, we will only allocate the global seqno at that time,
here we are just enabling the wait-for-submission before wait-for-seqno
paths.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_request.c  | 29 ++---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 12 
 2 files changed, 30 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 5622aaafb1ad..c54fee57c8fb 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -324,14 +324,31 @@ submit_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)
struct drm_i915_gem_request *request =
container_of(fence, typeof(*request), submit);
struct intel_engine_cs *engine = request->engine;
+   struct intel_timeline *timeline;
+   u32 seqno;
 
if (state != FENCE_COMPLETE)
return NOTIFY_DONE;
 
/* Will be called from irq-context when using foreign DMA fences */
 
-   engine->timeline->last_submitted_seqno = request->fence.seqno;
+   timeline = request->timeline;
 
+   seqno = request->fence.seqno;
+   GEM_BUG_ON(!seqno);
+   GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno));
+
+   GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno, seqno));
+   request->previous_seqno = timeline->last_submitted_seqno;
+   timeline->last_submitted_seqno = seqno;
+
+   spin_lock_nested(>lock, SINGLE_DEPTH_NESTING);
+   request->global_seqno = seqno;
+   if (test_bit(FENCE_FLAG_ENABLE_SIGNAL_BIT, >fence.flags))
+   intel_engine_enable_signaling(request);
+   spin_unlock(>lock);
+
+   GEM_BUG_ON(!request->global_seqno);
engine->emit_breadcrumb(request,
request->ring->vaddr + request->postfix);
engine->submit_request(request);
@@ -427,10 +444,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
INIT_LIST_HEAD(>active_list);
req->i915 = dev_priv;
req->engine = engine;
-   req->global_seqno = req->fence.seqno;
req->ctx = i915_gem_context_get(ctx);
 
/* No zalloc, must clear what we need by hand */
+   req->global_seqno = 0;
req->previous_context = NULL;
req->file_priv = NULL;
req->batch = NULL;
@@ -704,15 +721,13 @@ void __i915_add_request(struct drm_i915_gem_request 
*request, bool flush_caches)
i915_sw_fence_await_sw_fence(>submit, >submit,
 >submitq);
 
-   GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno,
-request->fence.seqno));
+   list_add_tail(>link, >requests);
 
-   request->emitted_jiffies = jiffies;
-   request->previous_seqno = timeline->last_pending_seqno;
timeline->last_pending_seqno = request->fence.seqno;
i915_gem_active_set(>last_request, request);
-   list_add_tail(>link, >requests);
+
list_add_tail(>ring_link, >request_list);
+   request->emitted_jiffies = jiffies;
 
i915_gem_mark_busy(engine);
 
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 7e65b415c535..594676363056 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -77,22 +77,26 @@ static void intel_breadcrumbs_fake_irq(unsigned long data)
 
 static void irq_enable(struct intel_engine_cs *engine)
 {
+   unsigned long flags;
+
/* Enabling the IRQ may miss the generation of the interrupt, but
 * we still need to force the barrier before reading the seqno,
 * just in case.
 */
engine->breadcrumbs.irq_posted = true;
 
-   spin_lock_irq(>i915->irq_lock);
+   spin_lock_irqsave(>i915->irq_lock, flags);
engine->irq_enable(engine);
-   spin_unlock_irq(>i915->irq_lock);
+   spin_unlock_irqrestore(>i915->irq_lock, flags);
 }
 
 static void irq_disable(struct intel_engine_cs *engine)
 {
-   spin_lock_irq(>i915->irq_lock);
+   unsigned long flags;
+
+   spin_lock_irqsave(>i915->irq_lock, flags);
engine->irq_disable(engine);
-   spin_unlock_irq(>i915->irq_lock);
+   spin_unlock_irqrestore(>i915->irq_lock, flags);
 
engine->breadcrumbs.irq_posted = false;
 }
-- 
2.9.3

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