Re: [Intel-gfx] [PATCH 4/4] drm/i915/bxt: Enable DC5 during runtime resume

2016-04-20 Thread Bob Paauwe 
On Wed, 20 Apr 2016 20:27:57 +0300
Imre Deak  wrote:

> Right after runtime resume we know that we can re-enable DC5, since we
> just disabled DC9 and power well 2 is disabled. So enable DC5 explicitly
> instead of delaying this until the next time we disable power well 2.
> 
> Signed-off-by: Imre Deak 

Reviewed-by: Bob Paauwe 

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 3 +++
>  drivers/gpu/drm/i915/intel_drv.h| 1 +
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
>  3 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 9f55631..d37c0a6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1601,6 +1601,9 @@ static int intel_runtime_resume(struct device *device)
>   if (IS_BROXTON(dev)) {
>   bxt_disable_dc9(dev_priv);
>   bxt_display_core_init(dev_priv, true);
> + if (dev_priv->csr.dmc_payload &&
> + (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
> + gen9_enable_dc5(dev_priv);
>   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>   hsw_disable_pc8(dev_priv);
>   } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 5464632..b9f1304 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1238,6 +1238,7 @@ void broxton_ddi_phy_verify_state(struct 
> drm_i915_private *dev_priv);
>  void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
>  void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> +void gen9_enable_dc5(struct drm_i915_private *dev_priv);
>  void skl_init_cdclk(struct drm_i915_private *dev_priv);
>  int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>  void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 329784e..3036962 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -582,7 +582,7 @@ static void assert_can_enable_dc5(struct drm_i915_private 
> *dev_priv)
>   assert_csr_loaded(dev_priv);
>  }
>  
> -static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> +void gen9_enable_dc5(struct drm_i915_private *dev_priv)
>  {
>   assert_can_enable_dc5(dev_priv);
>  



-- 
--
Bob Paauwe  
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193

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[Intel-gfx] [PATCH 4/4] drm/i915/bxt: Enable DC5 during runtime resume

2016-04-20 Thread Imre Deak 
Right after runtime resume we know that we can re-enable DC5, since we
just disabled DC9 and power well 2 is disabled. So enable DC5 explicitly
instead of delaying this until the next time we disable power well 2.

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_drv.c | 3 +++
 drivers/gpu/drm/i915/intel_drv.h| 1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9f55631..d37c0a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1601,6 +1601,9 @@ static int intel_runtime_resume(struct device *device)
if (IS_BROXTON(dev)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
+   if (dev_priv->csr.dmc_payload &&
+   (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+   gen9_enable_dc5(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
hsw_disable_pc8(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5464632..b9f1304 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1238,6 +1238,7 @@ void broxton_ddi_phy_verify_state(struct drm_i915_private 
*dev_priv);
 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
+void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 329784e..3036962 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -582,7 +582,7 @@ static void assert_can_enable_dc5(struct drm_i915_private 
*dev_priv)
assert_csr_loaded(dev_priv);
 }
 
-static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
+void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 {
assert_can_enable_dc5(dev_priv);
 
-- 
2.5.0

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