Re: [Intel-gfx] [PATCH 4/4] drm/i915: Clean up some DISPLAY_VER checks
On Mon, 27 Nov 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use the >= and < operators for the DISPLAY_VER checks everywhere.
> This is what most of the code does, but especially recently random
> pieces of code have started doing this differently for no good reason.
I suppose all the < 14 and >= 14 could be written as < 20 and >= 20, but
functionally should make no difference.
Reviewed-by: Jani Nikula
>
> Conversion done with the following cocci:
> @find@
> expression i915;
> constant ver;
> @@
> (
> DISPLAY_VER(i915) <= ver
> |
> DISPLAY_VER(i915) > ver
> )
>
> @script:python inc@
> old_ver << find.ver;
> new_ver;
> @@
> coccinelle.new_ver = str(int(old_ver) + 1)
>
> @@
> expression find.i915;
> constant find.ver;
> identifier inc.new_ver;
> @@
> (
> - DISPLAY_VER(i915) <= ver
> + DISPLAY_VER(i915) < new_ver
> |
> - DISPLAY_VER(i915) > ver
> + DISPLAY_VER(i915) >= new_ver
> )
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 8
> drivers/gpu/drm/i915/display/intel_bw.c | 7 ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c| 8
> drivers/gpu/drm/i915/display/intel_display_device.h | 2 +-
> drivers/gpu/drm/i915/display/intel_display_irq.c| 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c| 8
> 10 files changed, 22 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
> b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index b37c0d02d500..03e8fb6caa83 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -2477,7 +2477,7 @@ static unsigned int ilk_plane_wm_max(const struct
> drm_i915_private *dev_priv,
>* FIFO size is only half of the self
>* refresh FIFO size on ILK/SNB.
>*/
> - if (DISPLAY_VER(dev_priv) <= 6)
> + if (DISPLAY_VER(dev_priv) < 7)
> fifo_size /= 2;
> }
>
> @@ -2818,7 +2818,7 @@ static int ilk_compute_pipe_wm(struct
> intel_atomic_state *state,
> usable_level = dev_priv->display.wm.num_levels - 1;
>
> /* ILK/SNB: LP2+ watermarks only w/o sprites */
> - if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)
> + if (DISPLAY_VER(dev_priv) < 7 && pipe_wm->sprites_enabled)
> usable_level = 1;
>
> /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
> @@ -2961,7 +2961,7 @@ static void ilk_wm_merge(struct drm_i915_private
> *dev_priv,
> int last_enabled_level = num_levels - 1;
>
> /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
> - if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
> + if ((DISPLAY_VER(dev_priv) < 7 || IS_IVYBRIDGE(dev_priv)) &&
> config->num_pipes_active > 1)
> last_enabled_level = 0;
>
> @@ -3060,7 +3060,7 @@ static void ilk_compute_wm_results(struct
> drm_i915_private *dev_priv,
>* Always set WM_LP_SPRITE_EN when spr_val != 0, even if the
>* level is disabled. Doing otherwise could cause underruns.
>*/
> - if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
> + if (DISPLAY_VER(dev_priv) < 7 && r->spr_val) {
> drm_WARN_ON(_priv->drm, wm_lp != 1);
> results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index bef96db62c80..7f2a50b4f494 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -87,7 +87,8 @@ static int icl_pcode_read_qgv_point_info(struct
> drm_i915_private *dev_priv,
> return ret;
>
> dclk = val & 0x;
> - sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ?
> 500 : 0), 1000);
> + sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ?
> 500 : 0),
> + 1000);
> sp->t_rp = (val & 0xff) >> 16;
> sp->t_rcd = (val & 0xff00) >> 24;
>
> @@ -480,7 +481,7 @@ static int tgl_get_bw_info(struct drm_i915_private
> *dev_priv, const struct intel
> if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
> qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
>
> - if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels)
> + if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels)
> drm_warn(_priv->drm, "Number of channels exceeds max number
> of channels.");
> if (qi.max_numchannels != 0)
> num_channels = min_t(u8,
[Intel-gfx] [PATCH 4/4] drm/i915: Clean up some DISPLAY_VER checks
From: Ville Syrjälä
Use the >= and < operators for the DISPLAY_VER checks everywhere.
This is what most of the code does, but especially recently random
pieces of code have started doing this differently for no good reason.
Conversion done with the following cocci:
@find@
expression i915;
constant ver;
@@
(
DISPLAY_VER(i915) <= ver
|
DISPLAY_VER(i915) > ver
)
@script:python inc@
old_ver << find.ver;
new_ver;
@@
coccinelle.new_ver = str(int(old_ver) + 1)
@@
expression find.i915;
constant find.ver;
identifier inc.new_ver;
@@
(
- DISPLAY_VER(i915) <= ver
+ DISPLAY_VER(i915) < new_ver
|
- DISPLAY_VER(i915) > ver
+ DISPLAY_VER(i915) >= new_ver
)
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 8
drivers/gpu/drm/i915/display/intel_bw.c | 7 ---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c| 8
drivers/gpu/drm/i915/display/intel_display_device.h | 2 +-
drivers/gpu/drm/i915/display/intel_display_irq.c| 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c| 8
10 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/drm/i915/display/i9xx_wm.c
index b37c0d02d500..03e8fb6caa83 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -2477,7 +2477,7 @@ static unsigned int ilk_plane_wm_max(const struct
drm_i915_private *dev_priv,
* FIFO size is only half of the self
* refresh FIFO size on ILK/SNB.
*/
- if (DISPLAY_VER(dev_priv) <= 6)
+ if (DISPLAY_VER(dev_priv) < 7)
fifo_size /= 2;
}
@@ -2818,7 +2818,7 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state
*state,
usable_level = dev_priv->display.wm.num_levels - 1;
/* ILK/SNB: LP2+ watermarks only w/o sprites */
- if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)
+ if (DISPLAY_VER(dev_priv) < 7 && pipe_wm->sprites_enabled)
usable_level = 1;
/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
@@ -2961,7 +2961,7 @@ static void ilk_wm_merge(struct drm_i915_private
*dev_priv,
int last_enabled_level = num_levels - 1;
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
- if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
+ if ((DISPLAY_VER(dev_priv) < 7 || IS_IVYBRIDGE(dev_priv)) &&
config->num_pipes_active > 1)
last_enabled_level = 0;
@@ -3060,7 +3060,7 @@ static void ilk_compute_wm_results(struct
drm_i915_private *dev_priv,
* Always set WM_LP_SPRITE_EN when spr_val != 0, even if the
* level is disabled. Doing otherwise could cause underruns.
*/
- if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
+ if (DISPLAY_VER(dev_priv) < 7 && r->spr_val) {
drm_WARN_ON(_priv->drm, wm_lp != 1);
results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index bef96db62c80..7f2a50b4f494 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -87,7 +87,8 @@ static int icl_pcode_read_qgv_point_info(struct
drm_i915_private *dev_priv,
return ret;
dclk = val & 0x;
- sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ?
500 : 0), 1000);
+ sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ?
500 : 0),
+ 1000);
sp->t_rp = (val & 0xff) >> 16;
sp->t_rcd = (val & 0xff00) >> 24;
@@ -480,7 +481,7 @@ static int tgl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
- if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels)
+ if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels)
drm_warn(_priv->drm, "Number of channels exceeds max number
of channels.");
if (qi.max_numchannels != 0)
num_channels = min_t(u8, num_channels, qi.max_numchannels);
@@ -897,7 +898,7 @@ static int icl_find_qgv_points(struct drm_i915_private
*i915,
unsigned int idx;
unsigned int max_data_rate;
- if (DISPLAY_VER(i915) > 11)
+ if (DISPLAY_VER(i915) >= 12)
idx = tgl_max_bw_index(i915,
