Re: [Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-11 Thread Tvrtko Ursulin 


On 10/04/2017 15:34, Oscar Mateo wrote:

There are some properties that logically belong to the engine class, and some
that belong to the engine instance. Make it explicit.

v2: Commit message (Tvrtko)

v3:
  - Rebased
  - Exec/uabi id should be per instance (Chris)

v4:
  - Rebased
  - Avoid re-ordering fields for smaller diff (Tvrtko)
  - Bug on oob access to the class array (Michal)

v5: Bug on the right thing (Michal)

v6: Rebased

Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Reviewed-by: Michal Wajdeczko 
Signed-off-by: Oscar Mateo 

Conflicts:
drivers/gpu/drm/i915/intel_engine_cs.c


Snip this next time unless it sneaked in by accident.


---
 drivers/gpu/drm/i915/intel_engine_cs.c | 65 ++
 1 file changed, 42 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 5e5cda0..80cb0ff 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,84 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"

-static const struct engine_info {
+struct engine_class_info {
const char *name;
-   unsigned int exec_id;
+   int (*init_legacy)(struct intel_engine_cs *engine);
+   int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+   [RENDER_CLASS] = {
+   .name = "rcs",
+   .init_execlists = logical_render_ring_init,
+   .init_legacy = intel_init_render_ring_buffer,
+   },
+   [COPY_ENGINE_CLASS] = {
+   .name = "bcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_blt_ring_buffer,
+   },
+   [VIDEO_DECODE_CLASS] = {
+   .name = "vcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_bsd_ring_buffer,
+   },
+   [VIDEO_ENHANCEMENT_CLASS] = {
+   .name = "vecs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_vebox_ring_buffer,
+   },
+};
+
+struct engine_info {
unsigned int hw_id;
+   unsigned int exec_id;
u8 class;
u8 instance;
u32 mmio_base;
unsigned irq_shift;
-   int (*init_legacy)(struct intel_engine_cs *engine);
-   int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
[RCS] = {
-   .name = "rcs",
.hw_id = RCS_HW,
.exec_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
.instance = 0,
.mmio_base = RENDER_RING_BASE,
.irq_shift = GEN8_RCS_IRQ_SHIFT,
-   .init_execlists = logical_render_ring_init,
-   .init_legacy = intel_init_render_ring_buffer,
},
[BCS] = {
-   .name = "bcs",
.hw_id = BCS_HW,
.exec_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_base = BLT_RING_BASE,
.irq_shift = GEN8_BCS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_blt_ring_buffer,
},
[VCS] = {
-   .name = "vcs",
.hw_id = VCS_HW,
.exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_base = GEN6_BSD_RING_BASE,
.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VCS2] = {
-   .name = "vcs",
.hw_id = VCS2_HW,
.exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_base = GEN8_BSD2_RING_BASE,
.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VECS] = {
-   .name = "vecs",
.hw_id = VECS_HW,
.exec_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_base = VEBOX_RING_BASE,
.irq_shift = GEN8_VECS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_vebox_ring_buffer,
},
 };

@@ -99,8 +112,12 @@
   enum intel_engine_id id)
 {
const struct engine_info *info = &intel_engines[id];
+   const struct engine_class_info *class_info;
struct intel_engine_cs *engine;

+   GEM_BUG_ON(info->c

[Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-10 Thread Oscar Mateo 
There are some properties that logically belong to the engine class, and some
that belong to the engine instance. Make it explicit.

v2: Commit message (Tvrtko)

v3:
  - Rebased
  - Exec/uabi id should be per instance (Chris)

v4:
  - Rebased
  - Avoid re-ordering fields for smaller diff (Tvrtko)
  - Bug on oob access to the class array (Michal)

v5: Bug on the right thing (Michal)

v6: Rebased

Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Reviewed-by: Michal Wajdeczko 
Signed-off-by: Oscar Mateo 

Conflicts:
drivers/gpu/drm/i915/intel_engine_cs.c
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 65 ++
 1 file changed, 42 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 5e5cda0..80cb0ff 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,84 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
-static const struct engine_info {
+struct engine_class_info {
const char *name;
-   unsigned int exec_id;
+   int (*init_legacy)(struct intel_engine_cs *engine);
+   int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+   [RENDER_CLASS] = {
+   .name = "rcs",
+   .init_execlists = logical_render_ring_init,
+   .init_legacy = intel_init_render_ring_buffer,
+   },
+   [COPY_ENGINE_CLASS] = {
+   .name = "bcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_blt_ring_buffer,
+   },
+   [VIDEO_DECODE_CLASS] = {
+   .name = "vcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_bsd_ring_buffer,
+   },
+   [VIDEO_ENHANCEMENT_CLASS] = {
+   .name = "vecs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_vebox_ring_buffer,
+   },
+};
+
+struct engine_info {
unsigned int hw_id;
+   unsigned int exec_id;
u8 class;
u8 instance;
u32 mmio_base;
unsigned irq_shift;
-   int (*init_legacy)(struct intel_engine_cs *engine);
-   int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
[RCS] = {
-   .name = "rcs",
.hw_id = RCS_HW,
.exec_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
.instance = 0,
.mmio_base = RENDER_RING_BASE,
.irq_shift = GEN8_RCS_IRQ_SHIFT,
-   .init_execlists = logical_render_ring_init,
-   .init_legacy = intel_init_render_ring_buffer,
},
[BCS] = {
-   .name = "bcs",
.hw_id = BCS_HW,
.exec_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_base = BLT_RING_BASE,
.irq_shift = GEN8_BCS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_blt_ring_buffer,
},
[VCS] = {
-   .name = "vcs",
.hw_id = VCS_HW,
.exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_base = GEN6_BSD_RING_BASE,
.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VCS2] = {
-   .name = "vcs",
.hw_id = VCS2_HW,
.exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_base = GEN8_BSD2_RING_BASE,
.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VECS] = {
-   .name = "vecs",
.hw_id = VECS_HW,
.exec_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_base = VEBOX_RING_BASE,
.irq_shift = GEN8_VECS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_vebox_ring_buffer,
},
 };
 
@@ -99,8 +112,12 @@
   enum intel_engine_id id)
 {
const struct engine_info *info = &intel_engines[id];
+   const struct engine_class_info *class_info;
struct intel_engine_cs *engine;
 
+   GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));
+   class_info = &intel_engine_classes[info->class]

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-07 Thread Michal Wajdeczko 
On Fri, Apr 07, 2017 at 02:15:48AM -0700, Oscar Mateo wrote:
> There are some properties that logically belong to the engine class, and some
> that belong to the engine instance. Make it explicit.
> 
> v2: Commit message (Tvrtko)
> 
> v3:
>   - Rebased
>   - Exec/uabi id should be per instance (Chris)
> 
> v4:
>   - Rebased
>   - Avoid re-ordering fields for smaller diff (Tvrtko)
>   - Bug on oob access to the class array (Michal)
> 
> Cc: Tvrtko Ursulin 
> Cc: Paulo Zanoni 
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Cc: Daniele Ceraolo Spurio 
> Cc: Michal Wajdeczko 
> Signed-off-by: Oscar Mateo 
> ---



> @@ -99,8 +112,12 @@
>  enum intel_engine_id id)
>  {
>   const struct engine_info *info = &intel_engines[id];
> + const struct engine_class_info *class_info;
>   struct intel_engine_cs *engine;
>  
> + GEM_BUG_ON(info->class > ARRAY_SIZE(intel_engine_classes));
> + class_info = &intel_engine_classes[info->class];
> +

Hmm, I think we should check against info->class >= ARRAY_SIZE, as
index 4 can't be used on array[4]

-Michal

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[Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-07 Thread Oscar Mateo 
There are some properties that logically belong to the engine class, and some
that belong to the engine instance. Make it explicit.

v2: Commit message (Tvrtko)

v3:
  - Rebased
  - Exec/uabi id should be per instance (Chris)

v4:
  - Rebased
  - Avoid re-ordering fields for smaller diff (Tvrtko)
  - Bug on oob access to the class array (Michal)

Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 65 ++
 1 file changed, 42 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index e40355c..4e2b5da 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,84 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
-static const struct engine_info {
+struct engine_class_info {
const char *name;
-   unsigned int exec_id;
+   int (*init_legacy)(struct intel_engine_cs *engine);
+   int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+   [RENDER_CLASS] = {
+   .name = "rcs",
+   .init_execlists = logical_render_ring_init,
+   .init_legacy = intel_init_render_ring_buffer,
+   },
+   [COPY_ENGINE_CLASS] = {
+   .name = "bcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_blt_ring_buffer,
+   },
+   [VIDEO_DECODE_CLASS] = {
+   .name = "vcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_bsd_ring_buffer,
+   },
+   [VIDEO_ENHANCEMENT_CLASS] = {
+   .name = "vecs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_vebox_ring_buffer,
+   },
+};
+
+struct engine_info {
unsigned int hw_id;
+   unsigned int exec_id;
u8 class;
u8 instance;
u32 mmio_base;
unsigned irq_shift;
-   int (*init_legacy)(struct intel_engine_cs *engine);
-   int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
[RCS] = {
-   .name = "rcs",
.hw_id = RCS_HW,
.exec_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
.instance = 0,
.mmio_base = RENDER_RING_BASE,
.irq_shift = GEN8_RCS_IRQ_SHIFT,
-   .init_execlists = logical_render_ring_init,
-   .init_legacy = intel_init_render_ring_buffer,
},
[BCS] = {
-   .name = "bcs",
.hw_id = BCS_HW,
.exec_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_base = BLT_RING_BASE,
.irq_shift = GEN8_BCS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_blt_ring_buffer,
},
[VCS] = {
-   .name = "vcs",
.hw_id = VCS_HW,
.exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_base = GEN6_BSD_RING_BASE,
.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VCS2] = {
-   .name = "vcs",
.hw_id = VCS2_HW,
.exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_base = GEN8_BSD2_RING_BASE,
.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VECS] = {
-   .name = "vecs",
.hw_id = VECS_HW,
.exec_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_base = VEBOX_RING_BASE,
.irq_shift = GEN8_VECS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_vebox_ring_buffer,
},
 };
 
@@ -99,8 +112,12 @@
   enum intel_engine_id id)
 {
const struct engine_info *info = &intel_engines[id];
+   const struct engine_class_info *class_info;
struct intel_engine_cs *engine;
 
+   GEM_BUG_ON(info->class > ARRAY_SIZE(intel_engine_classes));
+   class_info = &intel_engine_classes[info->class];
+
GEM_BUG_ON(dev_priv->engine[id]);
engine = kzalloc(sizeof(*engine), GFP_KERNEL);
if (!engin

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-07 Thread Michal Wajdeczko 
On Thu, Apr 06, 2017 at 08:00:15AM -0700, Oscar Mateo wrote:
> There are some properties that logically belong to the engine class, and some
> that belong to the engine instance. Make it explicit.
> 
> v2: Commit message (Tvrtko)
> 
> v3:
>   - Rebased
>   - Exec/uabi id should be per instance (Chris)
> 
> Cc: Tvrtko Ursulin 
> Cc: Paulo Zanoni 
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Cc: Daniele Ceraolo Spurio 
> Signed-off-by: Oscar Mateo 
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 71 
> +-
>  1 file changed, 44 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index c6a73d0..6eab22d 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -26,71 +26,84 @@
>  #include "intel_ringbuffer.h"
>  #include "intel_lrc.h"
>  
> -static const struct engine_info {
> +struct engine_class_info {
>   const char *name;
> + int (*init_legacy)(struct intel_engine_cs *engine);
> + int (*init_execlists)(struct intel_engine_cs *engine);
> +};
> +
> +static const struct engine_class_info intel_engine_classes[] = {
> + [RENDER_CLASS] = {
> + .name = "rcs",
> + .init_execlists = logical_render_ring_init,
> + .init_legacy = intel_init_render_ring_buffer,
> + },
> + [COPY_ENGINE_CLASS] = {
> + .name = "bcs",
> + .init_execlists = logical_xcs_ring_init,
> + .init_legacy = intel_init_blt_ring_buffer,
> + },
> + [VIDEO_DECODE_CLASS] = {
> + .name = "vcs",
> + .init_execlists = logical_xcs_ring_init,
> + .init_legacy = intel_init_bsd_ring_buffer,
> + },
> + [VIDEO_ENHANCEMENT_CLASS] = {
> + .name = "vecs",
> + .init_execlists = logical_xcs_ring_init,
> + .init_legacy = intel_init_vebox_ring_buffer,
> + },
> +};
> +
> +struct engine_info {
>   unsigned int exec_id;
>   unsigned int hw_id;
>   enum intel_engine_class class;
>   u8 instance;
>   u32 mmio_base;
>   unsigned irq_shift;
> - int (*init_legacy)(struct intel_engine_cs *engine);
> - int (*init_execlists)(struct intel_engine_cs *engine);
> -} intel_engines[] = {
> +};
> +
> +static const struct engine_info intel_engines[] = {
>   [RCS] = {
> - .name = "rcs",
> - .hw_id = RCS_HW,
>   .exec_id = I915_EXEC_RENDER,
> + .hw_id = RCS_HW,
>   .class = RENDER_CLASS,
>   .instance = 0,
>   .mmio_base = RENDER_RING_BASE,
>   .irq_shift = GEN8_RCS_IRQ_SHIFT,
> - .init_execlists = logical_render_ring_init,
> - .init_legacy = intel_init_render_ring_buffer,
>   },
>   [BCS] = {
> - .name = "bcs",
> - .hw_id = BCS_HW,
>   .exec_id = I915_EXEC_BLT,
> + .hw_id = BCS_HW,
>   .class = COPY_ENGINE_CLASS,
>   .instance = 0,
>   .mmio_base = BLT_RING_BASE,
>   .irq_shift = GEN8_BCS_IRQ_SHIFT,
> - .init_execlists = logical_xcs_ring_init,
> - .init_legacy = intel_init_blt_ring_buffer,
>   },
>   [VCS] = {
> - .name = "vcs",
> - .hw_id = VCS_HW,
>   .exec_id = I915_EXEC_BSD,
> + .hw_id = VCS_HW,
>   .class = VIDEO_DECODE_CLASS,
>   .instance = 0,
>   .mmio_base = GEN6_BSD_RING_BASE,
>   .irq_shift = GEN8_VCS1_IRQ_SHIFT,
> - .init_execlists = logical_xcs_ring_init,
> - .init_legacy = intel_init_bsd_ring_buffer,
>   },
>   [VCS2] = {
> - .name = "vcs",
> - .hw_id = VCS2_HW,
>   .exec_id = I915_EXEC_BSD,
> + .hw_id = VCS2_HW,
>   .class = VIDEO_DECODE_CLASS,
>   .instance = 1,
>   .mmio_base = GEN8_BSD2_RING_BASE,
>   .irq_shift = GEN8_VCS2_IRQ_SHIFT,
> - .init_execlists = logical_xcs_ring_init,
> - .init_legacy = intel_init_bsd_ring_buffer,
>   },
>   [VECS] = {
> - .name = "vecs",
> - .hw_id = VECS_HW,
>   .exec_id = I915_EXEC_VEBOX,
> + .hw_id = VECS_HW,
>   .class = VIDEO_ENHANCEMENT_CLASS,
>   .instance = 0,
>   .mmio_base = VEBOX_RING_BASE,
>   .irq_shift = GEN8_VECS_IRQ_SHIFT,
> - .init_execlists = logical_xcs_ring_init,
> - .init_legacy = intel_init_vebox_ring_buffer,
>   },
>  };
>  
> @@ -99,6 +112,8 @@
>  enum intel_engine_id id)
>  {
>   const struct engine_info *info = &intel_engines[id];
> + const struct engine_class_info *class_info =
> + &intel_engine_classes[info->class];

Hmm, maybe we should add some protection against

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-07 Thread Tvrtko Ursulin 


On 06/04/2017 16:00, Oscar Mateo wrote:

There are some properties that logically belong to the engine class, and some
that belong to the engine instance. Make it explicit.

v2: Commit message (Tvrtko)

v3:
  - Rebased
  - Exec/uabi id should be per instance (Chris)

Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 71 +-
 1 file changed, 44 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index c6a73d0..6eab22d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,84 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"

-static const struct engine_info {
+struct engine_class_info {
const char *name;
+   int (*init_legacy)(struct intel_engine_cs *engine);
+   int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+   [RENDER_CLASS] = {
+   .name = "rcs",
+   .init_execlists = logical_render_ring_init,
+   .init_legacy = intel_init_render_ring_buffer,
+   },
+   [COPY_ENGINE_CLASS] = {
+   .name = "bcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_blt_ring_buffer,
+   },
+   [VIDEO_DECODE_CLASS] = {
+   .name = "vcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_bsd_ring_buffer,
+   },
+   [VIDEO_ENHANCEMENT_CLASS] = {
+   .name = "vecs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_vebox_ring_buffer,
+   },
+};
+
+struct engine_info {
unsigned int exec_id;
unsigned int hw_id;
enum intel_engine_class class;
u8 instance;
u32 mmio_base;
unsigned irq_shift;
-   int (*init_legacy)(struct intel_engine_cs *engine);
-   int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
[RCS] = {
-   .name = "rcs",
-   .hw_id = RCS_HW,
.exec_id = I915_EXEC_RENDER,
+   .hw_id = RCS_HW,


One more bit of polish - avoid re-ordering the two fields here and below 
for a smaller diff. Or it is a deliberate choice to re-order?


Regards,

Tvrtko


.class = RENDER_CLASS,
.instance = 0,
.mmio_base = RENDER_RING_BASE,
.irq_shift = GEN8_RCS_IRQ_SHIFT,
-   .init_execlists = logical_render_ring_init,
-   .init_legacy = intel_init_render_ring_buffer,
},
[BCS] = {
-   .name = "bcs",
-   .hw_id = BCS_HW,
.exec_id = I915_EXEC_BLT,
+   .hw_id = BCS_HW,
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_base = BLT_RING_BASE,
.irq_shift = GEN8_BCS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_blt_ring_buffer,
},
[VCS] = {
-   .name = "vcs",
-   .hw_id = VCS_HW,
.exec_id = I915_EXEC_BSD,
+   .hw_id = VCS_HW,
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_base = GEN6_BSD_RING_BASE,
.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VCS2] = {
-   .name = "vcs",
-   .hw_id = VCS2_HW,
.exec_id = I915_EXEC_BSD,
+   .hw_id = VCS2_HW,
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_base = GEN8_BSD2_RING_BASE,
.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VECS] = {
-   .name = "vecs",
-   .hw_id = VECS_HW,
.exec_id = I915_EXEC_VEBOX,
+   .hw_id = VECS_HW,
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_base = VEBOX_RING_BASE,
.irq_shift = GEN8_VECS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_vebox_ring_buffer,
},
 };

@@ -99,6 +112,8 @@
   enum intel_engine_id id)
 {
const struct engine_info *info = &intel_engines[id];
+   const struct engine_class_info *class_info =
+   &intel_engine_classes[info->class];

[Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-06 Thread Oscar Mateo 
There are some properties that logically belong to the engine class, and some
that belong to the engine instance. Make it explicit.

v2: Commit message (Tvrtko)

v3:
  - Rebased
  - Exec/uabi id should be per instance (Chris)

Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 71 +-
 1 file changed, 44 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index c6a73d0..6eab22d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,84 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
-static const struct engine_info {
+struct engine_class_info {
const char *name;
+   int (*init_legacy)(struct intel_engine_cs *engine);
+   int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+   [RENDER_CLASS] = {
+   .name = "rcs",
+   .init_execlists = logical_render_ring_init,
+   .init_legacy = intel_init_render_ring_buffer,
+   },
+   [COPY_ENGINE_CLASS] = {
+   .name = "bcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_blt_ring_buffer,
+   },
+   [VIDEO_DECODE_CLASS] = {
+   .name = "vcs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_bsd_ring_buffer,
+   },
+   [VIDEO_ENHANCEMENT_CLASS] = {
+   .name = "vecs",
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_vebox_ring_buffer,
+   },
+};
+
+struct engine_info {
unsigned int exec_id;
unsigned int hw_id;
enum intel_engine_class class;
u8 instance;
u32 mmio_base;
unsigned irq_shift;
-   int (*init_legacy)(struct intel_engine_cs *engine);
-   int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
[RCS] = {
-   .name = "rcs",
-   .hw_id = RCS_HW,
.exec_id = I915_EXEC_RENDER,
+   .hw_id = RCS_HW,
.class = RENDER_CLASS,
.instance = 0,
.mmio_base = RENDER_RING_BASE,
.irq_shift = GEN8_RCS_IRQ_SHIFT,
-   .init_execlists = logical_render_ring_init,
-   .init_legacy = intel_init_render_ring_buffer,
},
[BCS] = {
-   .name = "bcs",
-   .hw_id = BCS_HW,
.exec_id = I915_EXEC_BLT,
+   .hw_id = BCS_HW,
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_base = BLT_RING_BASE,
.irq_shift = GEN8_BCS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_blt_ring_buffer,
},
[VCS] = {
-   .name = "vcs",
-   .hw_id = VCS_HW,
.exec_id = I915_EXEC_BSD,
+   .hw_id = VCS_HW,
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_base = GEN6_BSD_RING_BASE,
.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VCS2] = {
-   .name = "vcs",
-   .hw_id = VCS2_HW,
.exec_id = I915_EXEC_BSD,
+   .hw_id = VCS2_HW,
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_base = GEN8_BSD2_RING_BASE,
.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VECS] = {
-   .name = "vecs",
-   .hw_id = VECS_HW,
.exec_id = I915_EXEC_VEBOX,
+   .hw_id = VECS_HW,
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_base = VEBOX_RING_BASE,
.irq_shift = GEN8_VECS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_vebox_ring_buffer,
},
 };
 
@@ -99,6 +112,8 @@
   enum intel_engine_id id)
 {
const struct engine_info *info = &intel_engines[id];
+   const struct engine_class_info *class_info =
+   &intel_engine_classes[info->class];
struct intel_engine_cs *engine;
 
GEM_BUG_ON(dev_priv->engine[id]);
@@ -109,7 +124,7 @@
engine->id = id;
engine->i915 = dev_priv;
snprintf(engine->name, sizeof(en

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-06 Thread Oscar Mateo 



On 04/06/2017 01:12 PM, Chris Wilson wrote:

On Thu, Apr 06, 2017 at 05:55:43AM -0700, Oscar Mateo wrote:

There are some properties that logically belong to the engine class, and some
that belong to the engine instance. Make it explicit.

v2: Commit message (Tvrtko)

Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
---
  drivers/gpu/drm/i915/intel_engine_cs.c | 72 +-
  1 file changed, 44 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 2409908..506ec952 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,83 @@
  #include "intel_ringbuffer.h"
  #include "intel_lrc.h"
  
-static const struct engine_info {

+struct engine_class_info {
const char *name;
unsigned int exec_id;

Ugh. What??? Each engine will have a unique exec/uabi id.
-Chris
Ok, I'll move it back to the instance if it matches better the VLC load 
balancing work?

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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-06 Thread Chris Wilson 
On Thu, Apr 06, 2017 at 05:55:43AM -0700, Oscar Mateo wrote:
> There are some properties that logically belong to the engine class, and some
> that belong to the engine instance. Make it explicit.
> 
> v2: Commit message (Tvrtko)
> 
> Cc: Tvrtko Ursulin 
> Cc: Paulo Zanoni 
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Cc: Daniele Ceraolo Spurio 
> Signed-off-by: Oscar Mateo 
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 72 
> +-
>  1 file changed, 44 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 2409908..506ec952 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -26,71 +26,83 @@
>  #include "intel_ringbuffer.h"
>  #include "intel_lrc.h"
>  
> -static const struct engine_info {
> +struct engine_class_info {
>   const char *name;
>   unsigned int exec_id;

Ugh. What??? Each engine will have a unique exec/uabi id.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-06 Thread Oscar Mateo 
There are some properties that logically belong to the engine class, and some
that belong to the engine instance. Make it explicit.

v2: Commit message (Tvrtko)

Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 72 +-
 1 file changed, 44 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 2409908..506ec952 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,83 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
-static const struct engine_info {
+struct engine_class_info {
const char *name;
unsigned int exec_id;
+   int (*init_legacy)(struct intel_engine_cs *engine);
+   int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+   [RENDER_CLASS] = {
+   .name = "rcs",
+   .exec_id = I915_EXEC_RENDER,
+   .init_execlists = logical_render_ring_init,
+   .init_legacy = intel_init_render_ring_buffer,
+   },
+   [COPY_ENGINE_CLASS] = {
+   .name = "bcs",
+   .exec_id = I915_EXEC_BLT,
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_blt_ring_buffer,
+   },
+   [VIDEO_DECODE_CLASS] = {
+   .name = "vcs",
+   .exec_id = I915_EXEC_BSD,
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_bsd_ring_buffer,
+   },
+   [VIDEO_ENHANCEMENT_CLASS] = {
+   .name = "vecs",
+   .exec_id = I915_EXEC_VEBOX,
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_vebox_ring_buffer,
+   },
+};
+
+struct engine_info {
unsigned int hw_id;
enum intel_engine_class class;
u8 instance;
u32 mmio_base;
unsigned irq_shift;
-   int (*init_legacy)(struct intel_engine_cs *engine);
-   int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
[RCS] = {
-   .name = "rcs",
.hw_id = RCS_HW,
-   .exec_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
.instance = 0,
.mmio_base = RENDER_RING_BASE,
.irq_shift = GEN8_RCS_IRQ_SHIFT,
-   .init_execlists = logical_render_ring_init,
-   .init_legacy = intel_init_render_ring_buffer,
},
[BCS] = {
-   .name = "bcs",
.hw_id = BCS_HW,
-   .exec_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_base = BLT_RING_BASE,
.irq_shift = GEN8_BCS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_blt_ring_buffer,
},
[VCS] = {
-   .name = "vcs",
.hw_id = VCS_HW,
-   .exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_base = GEN6_BSD_RING_BASE,
.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VCS2] = {
-   .name = "vcs",
.hw_id = VCS2_HW,
-   .exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_base = GEN8_BSD2_RING_BASE,
.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VECS] = {
-   .name = "vecs",
.hw_id = VECS_HW,
-   .exec_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_base = VEBOX_RING_BASE,
.irq_shift = GEN8_VECS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_vebox_ring_buffer,
},
 };
 
@@ -99,6 +111,8 @@
   enum intel_engine_id id)
 {
const struct engine_info *info = &intel_engines[id];
+   const struct engine_class_info *class_info =
+   &intel_engine_classes[info->class];
struct intel_engine_cs *engine;
char instance[3] = "";
 
@@ -110,8 +124,8 @@
engine->id = id;
engine->i915 = dev_priv;
snprintf(instance, sizeof(instance), "%u", info->instance);
-   snprintf(engine->name, sizeof(eng

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-06 Thread Tvrtko Ursulin 


On 05/04/2017 10:30, Oscar Mateo wrote:

Commit message missing.


Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 72 +-
 1 file changed, 44 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 530f822..691689c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,83 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"

-static const struct engine_info {
+struct engine_class_info {
const char *name;
unsigned int exec_id;
+   int (*init_legacy)(struct intel_engine_cs *engine);
+   int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+   [RENDER_CLASS] = {
+   .name = "rcs",
+   .exec_id = I915_EXEC_RENDER,
+   .init_execlists = logical_render_ring_init,
+   .init_legacy = intel_init_render_ring_buffer,
+   },
+   [COPY_ENGINE_CLASS] = {
+   .name = "bcs",
+   .exec_id = I915_EXEC_BLT,
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_blt_ring_buffer,
+   },
+   [VIDEO_DECODE_CLASS] = {
+   .name = "vcs",
+   .exec_id = I915_EXEC_BSD,
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_bsd_ring_buffer,
+   },
+   [VIDEO_ENHANCEMENT_CLASS] = {
+   .name = "vecs",
+   .exec_id = I915_EXEC_VEBOX,
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_vebox_ring_buffer,
+   },
+};
+
+struct engine_info {
unsigned int hw_id;
enum intel_engine_class class;
u32 instance;
u32 mmio_base;
unsigned irq_shift;
-   int (*init_legacy)(struct intel_engine_cs *engine);
-   int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
[RCS] = {
-   .name = "rcs",
.hw_id = RCS_HW,
-   .exec_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
.instance = 0,
.mmio_base = RENDER_RING_BASE,
.irq_shift = GEN8_RCS_IRQ_SHIFT,
-   .init_execlists = logical_render_ring_init,
-   .init_legacy = intel_init_render_ring_buffer,
},
[BCS] = {
-   .name = "bcs",
.hw_id = BCS_HW,
-   .exec_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_base = BLT_RING_BASE,
.irq_shift = GEN8_BCS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_blt_ring_buffer,
},
[VCS] = {
-   .name = "vcs",
.hw_id = VCS_HW,
-   .exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_base = GEN6_BSD_RING_BASE,
.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VCS2] = {
-   .name = "vcs",
.hw_id = VCS2_HW,
-   .exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_base = GEN8_BSD2_RING_BASE,
.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VECS] = {
-   .name = "vecs",
.hw_id = VECS_HW,
-   .exec_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_base = VEBOX_RING_BASE,
.irq_shift = GEN8_VECS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_vebox_ring_buffer,
},
 };

@@ -99,6 +111,8 @@
   enum intel_engine_id id)
 {
const struct engine_info *info = &intel_engines[id];
+   const struct engine_class_info *class_info =
+   &intel_engine_classes[info->class];
struct intel_engine_cs *engine;
char instance[3] = "";

@@ -112,8 +126,8 @@
/* For historical reasons the engines are called: name, name2... */
if (info->instance)
snprintf(instance, sizeof(instance), "%u", info->instance + 1);
-   snprintf(engine->name, sizeof(engine->name), "%s%s", info->name, 
insta

[Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

2017-04-05 Thread Oscar Mateo 
Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 72 +-
 1 file changed, 44 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 530f822..691689c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,83 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
-static const struct engine_info {
+struct engine_class_info {
const char *name;
unsigned int exec_id;
+   int (*init_legacy)(struct intel_engine_cs *engine);
+   int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+   [RENDER_CLASS] = {
+   .name = "rcs",
+   .exec_id = I915_EXEC_RENDER,
+   .init_execlists = logical_render_ring_init,
+   .init_legacy = intel_init_render_ring_buffer,
+   },
+   [COPY_ENGINE_CLASS] = {
+   .name = "bcs",
+   .exec_id = I915_EXEC_BLT,
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_blt_ring_buffer,
+   },
+   [VIDEO_DECODE_CLASS] = {
+   .name = "vcs",
+   .exec_id = I915_EXEC_BSD,
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_bsd_ring_buffer,
+   },
+   [VIDEO_ENHANCEMENT_CLASS] = {
+   .name = "vecs",
+   .exec_id = I915_EXEC_VEBOX,
+   .init_execlists = logical_xcs_ring_init,
+   .init_legacy = intel_init_vebox_ring_buffer,
+   },
+};
+
+struct engine_info {
unsigned int hw_id;
enum intel_engine_class class;
u32 instance;
u32 mmio_base;
unsigned irq_shift;
-   int (*init_legacy)(struct intel_engine_cs *engine);
-   int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
[RCS] = {
-   .name = "rcs",
.hw_id = RCS_HW,
-   .exec_id = I915_EXEC_RENDER,
.class = RENDER_CLASS,
.instance = 0,
.mmio_base = RENDER_RING_BASE,
.irq_shift = GEN8_RCS_IRQ_SHIFT,
-   .init_execlists = logical_render_ring_init,
-   .init_legacy = intel_init_render_ring_buffer,
},
[BCS] = {
-   .name = "bcs",
.hw_id = BCS_HW,
-   .exec_id = I915_EXEC_BLT,
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_base = BLT_RING_BASE,
.irq_shift = GEN8_BCS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_blt_ring_buffer,
},
[VCS] = {
-   .name = "vcs",
.hw_id = VCS_HW,
-   .exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_base = GEN6_BSD_RING_BASE,
.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VCS2] = {
-   .name = "vcs",
.hw_id = VCS2_HW,
-   .exec_id = I915_EXEC_BSD,
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_base = GEN8_BSD2_RING_BASE,
.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_bsd_ring_buffer,
},
[VECS] = {
-   .name = "vecs",
.hw_id = VECS_HW,
-   .exec_id = I915_EXEC_VEBOX,
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_base = VEBOX_RING_BASE,
.irq_shift = GEN8_VECS_IRQ_SHIFT,
-   .init_execlists = logical_xcs_ring_init,
-   .init_legacy = intel_init_vebox_ring_buffer,
},
 };
 
@@ -99,6 +111,8 @@
   enum intel_engine_id id)
 {
const struct engine_info *info = &intel_engines[id];
+   const struct engine_class_info *class_info =
+   &intel_engine_classes[info->class];
struct intel_engine_cs *engine;
char instance[3] = "";
 
@@ -112,8 +126,8 @@
/* For historical reasons the engines are called: name, name2... */
if (info->instance)
snprintf(instance, sizeof(instance), "%u", info->instance + 1);
-   snprintf(engine->name, sizeof(engine->name), "%s%s", info->name, 
instance);
-   engine->exec_id = info->exec_id;
+   snprintf(en