Re: [Intel-gfx] [PATCH 4/5] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Ville Syrjälä]

On Tue, Sep 19, 2017 at 10:44:08PM +0300, Juha-Pekka Heikkila wrote:
> Move u32 dspaddr_offset from struct intel_crtc member into local
> variable in i9xx_update_primary_plane()

I would reorder the series so that this is done before you eliminate the
SKL primary plane functions. Would make it more obvious that there are
no real differences between the SKL primary vs. sprite functions.

> 
> Signed-off-by: Juha-Pekka Heikkila 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 12 ++--
>  drivers/gpu/drm/i915/intel_drv.h |  5 -
>  2 files changed, 6 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 48d5975..d214977 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3298,7 +3298,6 @@ static void i9xx_update_primary_plane(struct 
> intel_plane *primary,
> const struct intel_plane_state 
> *plane_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>   const struct drm_framebuffer *fb = plane_state->base.fb;
>   enum plane plane = primary->plane;
>   u32 linear_offset;
> @@ -3308,13 +3307,14 @@ static void i9xx_update_primary_plane(struct 
> intel_plane *primary,
>   int y = plane_state->main.y;
>   unsigned long irqflags;
>   struct intel_fbc *fbc = _priv->fbc;
> + u32 dspaddr_offset;
>  
>   linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>  
>   if (INTEL_GEN(dev_priv) >= 4)
> - crtc->dspaddr_offset = plane_state->main.offset;
> + dspaddr_offset = plane_state->main.offset;
>   else
> - crtc->dspaddr_offset = linear_offset;
> + dspaddr_offset = linear_offset;
>  
>   fbc->state_cache.plane.adjusted_x = x;
>   fbc->state_cache.plane.adjusted_y = y;
> @@ -3343,18 +3343,18 @@ static void i9xx_update_primary_plane(struct 
> intel_plane *primary,
>   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>   I915_WRITE_FW(DSPSURF(plane),
> intel_plane_ggtt_offset(plane_state) +
> -   crtc->dspaddr_offset);
> +   dspaddr_offset);
>   I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
>   } else if (INTEL_GEN(dev_priv) >= 4) {
>   I915_WRITE_FW(DSPSURF(plane),
> intel_plane_ggtt_offset(plane_state) +
> -   crtc->dspaddr_offset);
> +   dspaddr_offset);
>   I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
>   I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
>   } else {
>   I915_WRITE_FW(DSPADDR(plane),
> intel_plane_ggtt_offset(plane_state) +
> -   crtc->dspaddr_offset);
> +   dspaddr_offset);
>   }
>   POSTING_READ_FW(reg);
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 56fb493..a92c2e2 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -803,11 +803,6 @@ struct intel_crtc {
>   unsigned long long enabled_power_domains;
>   struct intel_overlay *overlay;
>  
> - /* Display surface base address adjustement for pageflips. Note that on
> -  * gen4+ this only adjusts up to a tile, offsets within a tile are
> -  * handled in the hw itself (with the TILEOFF register). */
> - u32 dspaddr_offset;
> -
>   struct intel_crtc_state *config;
>  
>   /* global reset count when the last flip was submitted */
> -- 
> 2.7.4
> 
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-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH 4/5] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Juha-Pekka Heikkila]

Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()

Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/intel_display.c | 12 ++--
 drivers/gpu/drm/i915/intel_drv.h |  5 -
 2 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 48d5975..d214977 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3298,7 +3298,6 @@ static void i9xx_update_primary_plane(struct intel_plane 
*primary,
  const struct intel_plane_state 
*plane_state)
 {
struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
const struct drm_framebuffer *fb = plane_state->base.fb;
enum plane plane = primary->plane;
u32 linear_offset;
@@ -3308,13 +3307,14 @@ static void i9xx_update_primary_plane(struct 
intel_plane *primary,
int y = plane_state->main.y;
unsigned long irqflags;
struct intel_fbc *fbc = _priv->fbc;
+   u32 dspaddr_offset;
 
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
if (INTEL_GEN(dev_priv) >= 4)
-   crtc->dspaddr_offset = plane_state->main.offset;
+   dspaddr_offset = plane_state->main.offset;
else
-   crtc->dspaddr_offset = linear_offset;
+   dspaddr_offset = linear_offset;
 
fbc->state_cache.plane.adjusted_x = x;
fbc->state_cache.plane.adjusted_y = y;
@@ -3343,18 +3343,18 @@ static void i9xx_update_primary_plane(struct 
intel_plane *primary,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE_FW(DSPSURF(plane),
  intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
} else if (INTEL_GEN(dev_priv) >= 4) {
I915_WRITE_FW(DSPSURF(plane),
  intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
} else {
I915_WRITE_FW(DSPADDR(plane),
  intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
}
POSTING_READ_FW(reg);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 56fb493..a92c2e2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -803,11 +803,6 @@ struct intel_crtc {
unsigned long long enabled_power_domains;
struct intel_overlay *overlay;
 
-   /* Display surface base address adjustement for pageflips. Note that on
-* gen4+ this only adjusts up to a tile, offsets within a tile are
-* handled in the hw itself (with the TILEOFF register). */
-   u32 dspaddr_offset;
-
struct intel_crtc_state *config;
 
/* global reset count when the last flip was submitted */
-- 
2.7.4

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