[Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen =8 or gen 5 before setting M/N registers
v3: Incorporated Jani's review comments
Re-use cpu_transcoder_set_m_n for BDW.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
drivers/gpu/drm/i915/intel_dp.c | 25 +++--
drivers/gpu/drm/i915/intel_drv.h |2 ++
3 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 86cd603..64ed4e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4901,7 +4901,7 @@ static void intel_pch_transcoder_set_m_n(struct
intel_crtc *crtc,
I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n-link_n);
}
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct drm_device *dev = crtc-base.dev;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3407af6..0cfba6b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -839,11 +839,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n-tu) | m_n-gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ if (INTEL_INFO(dev)-gen = 8) {
+ intel_cpu_transcoder_set_m_n(crtc, m_n);
+ } else if (INTEL_INFO(dev)-gen 6) {
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ }
}
bool
@@ -3749,7 +3753,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate)
mutex_lock(intel_dp-drrs_state.mutex);
- if (INTEL_INFO(dev)-gen 6 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)-gen 6) {
reg = PIPECONF(intel_crtc-config.cpu_transcoder);
val = I915_READ(reg);
if (index DRRS_HIGH_RR) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c8d6aa2..4da5abc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -751,6 +751,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
void intel_display_set_init_power(struct drm_device *dev, bool enable);
int valleyview_get_vco(struct drm_i915_private *dev_priv);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n);
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
On Jan-22-2014 8:04 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen =8 or gen 5 before setting M/N registers
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 7778808..f18a585 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,11 +798,20 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
-I915_WRITE(PIPE_DATA_M2(transcoder),
-TU_SIZE(m_n-tu) | m_n-gmch_m);
-I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
-I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
-I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+if (INTEL_INFO(dev)-gen = 8) {
+I915_WRITE(PIPE_DATA_M1(transcoder),
+TU_SIZE(m_n-tu) | m_n-gmch_m);
+I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
There's already a function for this part, called
intel_cpu_transcoder_set_m_n. Reuse it.
Ok. I will make necessary changes
+} else if (INTEL_INFO(dev)-gen = 5) {
+I915_WRITE(PIPE_DATA_M2(transcoder),
+TU_SIZE(m_n-tu) | m_n-gmch_m);
+I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
+I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
+I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+}
+
return;
}
@@ -3612,8 +3621,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate) {
mutex_lock(intel_dp-drrs_state.mutex);
-/* Haswell and below */
Forgot to mention in the earlier patch that comments like this are
redundant with the code. And in this case, it already *contradicts* the
code.
-if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+if (INTEL_INFO(dev)-gen = 8) {
+switch (index) {
+case DRRS_HIGH_RR:
+intel_dp_set_m2_n2(intel_crtc, config-dp_m_n);
+break;
+case DRRS_LOW_RR:
+intel_dp_set_m2_n2(intel_crtc, config-dp_m2_n2);
+break;
+};
+} else if (INTEL_INFO(dev)-gen = 5) {
+/* Haswell and below */
This comment can be removed.
reg = PIPECONF(intel_crtc-config.cpu_transcoder);
val = I915_READ(reg);
if (index DRRS_HIGH_RR) {
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen =8 or gen 5 before setting M/N registers
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7778808..f18a585 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,11 +798,20 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n-tu) | m_n-gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ if (INTEL_INFO(dev)-gen = 8) {
+ I915_WRITE(PIPE_DATA_M1(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
There's already a function for this part, called
intel_cpu_transcoder_set_m_n. Reuse it.
+ } else if (INTEL_INFO(dev)-gen = 5) {
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ }
+
return;
}
@@ -3612,8 +3621,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate) {
mutex_lock(intel_dp-drrs_state.mutex);
- /* Haswell and below */
Forgot to mention in the earlier patch that comments like this are
redundant with the code. And in this case, it already *contradicts* the
code.
- if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)-gen = 5) {
+ /* Haswell and below */
reg = PIPECONF(intel_crtc-config.cpu_transcoder);
val = I915_READ(reg);
if (index DRRS_HIGH_RR) {
--
1.7.9.5
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--
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[Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen =8 or gen 5 before setting M/N registers
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7778808..f18a585 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,11 +798,20 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n-tu) | m_n-gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ if (INTEL_INFO(dev)-gen = 8) {
+ I915_WRITE(PIPE_DATA_M1(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
+ } else if (INTEL_INFO(dev)-gen = 5) {
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ }
+
return;
}
@@ -3612,8 +3621,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate) {
mutex_lock(intel_dp-drrs_state.mutex);
- /* Haswell and below */
- if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)-gen = 5) {
+ /* Haswell and below */
reg = PIPECONF(intel_crtc-config.cpu_transcoder);
val = I915_READ(reg);
if (index DRRS_HIGH_RR) {
--
1.7.9.5
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[Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen =8 or gen 5 before setting M/N registers
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_dp.c | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d9c5aca..42aea17 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,11 +798,20 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n-tu) | m_n-gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ if (INTEL_INFO(dev)-gen = 8) {
+ I915_WRITE(PIPE_DATA_M1(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
+ } else if (INTEL_INFO(dev)-gen = 5) {
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ }
+
return;
}
@@ -3612,8 +3621,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate) {
mutex_lock(intel_dp-drrs_state.mutex);
- /* Haswell and below */
- if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)-gen = 5) {
+ /* Haswell and below */
reg = PIPECONF(intel_crtc-config.cpu_transcoder);
val = I915_READ(reg);
if (index DRRS_HIGH_RR) {
--
1.7.9.5
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[Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen =8 or gen 5 before setting M/N registers
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_dp.c | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c96ed34..be06d73 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,11 +798,19 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n-tu) | m_n-gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ if (INTEL_INFO(dev)-gen = 8) {
+ I915_WRITE(PIPE_DATA_M1(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
+ } else if (INTEL_INFO(dev)-gen = 5) {
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
+ }
return;
}
@@ -3616,8 +3624,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate)
mutex_lock(intel_dp-drrs_state.mutex);
- /* Haswell and below */
- if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)-gen = 5) {
+ /* Haswell and below */
reg = PIPECONF(intel_crtc-config.cpu_transcoder);
val = I915_READ(reg);
if (index DRRS_HIGH_RR) {
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
On Dec-17-2013 6:00 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote:
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 209be3c..183cfd7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
-if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+if (INTEL_INFO(dev)-gen = 8) {
+I915_WRITE(PIPE_DATA_M1(transcoder),
+TU_SIZE(m_n-tu) | m_n-gmch_m);
+I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
+} else if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
Ouch. Double ouch later.
-Chris
We are looking to write in M1/N1 registers for BDW and M2/N2 registers
for HSW and below. What is your suggestion on how to implement this ?
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
On Wed, Dec 18, 2013 at 01:54:56PM +0530, Vandana Kannan wrote:
On Dec-17-2013 6:00 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote:
For Broadwell, there is one instance of Transcoder MN values per
transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 209be3c..183cfd7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
- if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ I915_WRITE(PIPE_DATA_M1(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
+ } else if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
Ouch. Double ouch later.
-Chris
We are looking to write in M1/N1 registers for BDW and M2/N2 registers
for HSW and below. What is your suggestion on how to implement this ?
if (gen = 8) {
} else if (gen = 5) {
}
Or as you use gen = 5 gen 8 elsewhere, a feature macro would be
even more sensible, HAS_DRRS().
-Chris
--
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
On Dec-18-2013 2:31 PM, Chris Wilson wrote:
On Wed, Dec 18, 2013 at 01:54:56PM +0530, Vandana Kannan wrote:
On Dec-17-2013 6:00 PM, Chris Wilson wrote:
On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote:
For Broadwell, there is one instance of Transcoder MN values per
transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 209be3c..183cfd7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
- if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ I915_WRITE(PIPE_DATA_M1(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
+ } else if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
Ouch. Double ouch later.
-Chris
We are looking to write in M1/N1 registers for BDW and M2/N2 registers
for HSW and below. What is your suggestion on how to implement this ?
if (gen = 8) {
} else if (gen = 5) {
}
Or as you use gen = 5 gen 8 elsewhere, a feature macro would be
even more sensible, HAS_DRRS().
-Chris
I will make this change to
if (gen = 8) {
} else if (gen = 5) {
}
- Vandana
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote:
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 209be3c..183cfd7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
- if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ I915_WRITE(PIPE_DATA_M1(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
+ } else if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
Ouch. Double ouch later.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M N registers and the new M/N values will be used in the next frame
that is output.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: Pradeep Bhat pradeep.b...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 209be3c..183cfd7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev-dev_private;
enum transcoder transcoder = crtc-config.cpu_transcoder;
- if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ I915_WRITE(PIPE_DATA_M1(transcoder),
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
+ I915_WRITE(PIPE_DATA_N1(transcoder), m_n-gmch_n);
+ I915_WRITE(PIPE_LINK_M1(transcoder), m_n-link_m);
+ I915_WRITE(PIPE_LINK_N1(transcoder), m_n-link_n);
+ } else if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n-tu) | m_n-gmch_m);
+ TU_SIZE(m_n-tu) | m_n-gmch_m);
I915_WRITE(PIPE_DATA_N2(transcoder), m_n-gmch_n);
I915_WRITE(PIPE_LINK_M2(transcoder), m_n-link_m);
I915_WRITE(PIPE_LINK_N2(transcoder), m_n-link_n);
@@ -3617,8 +3623,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate)
mutex_lock(intel_dp-drrs_state.mutex);
- /* Haswell and below */
- if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ if (INTEL_INFO(dev)-gen = 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, config-dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)-gen = 5 INTEL_INFO(dev)-gen 8) {
+ /* Haswell and below */
reg = PIPECONF(intel_crtc-config.cpu_transcoder);
val = I915_READ(reg);
if (index DRRS_HIGH_RR) {
--
1.7.9.5
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