Re: [Intel-gfx] [PATCH 6/8] drm/i915/debugfs: Add perf_limit_reasons in debugfs
On Fri, 2022-09-09 at 08:38 -0700, Dixit, Ashutosh wrote: On Fri, 09 Sep 2022 03:13:05 -0700, Rodrigo Vivi wrote: On Wed, Sep 07, 2022 at 10:22:49PM -0700, Ashutosh Dixit wrote: From: Tilak Tangudu mailto:tilak.tang...@intel.com>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 24009786f88b..9492f8f43b25 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1802,6 +1802,7 @@ #define POWER_LIMIT_4_MASK REG_BIT(8) #define POWER_LIMIT_1_MASK REG_BIT(10) #define POWER_LIMIT_2_MASK REG_BIT(11) +#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) I'm kind of confused here because I saw the other bits in the patch 5. Sorry Rodrigo, patch 5 is a bug-fix patch which should probably be merged to -fixes independent of this series, I have posted it independently too: https://patchwork.freedesktop.org/series/108277/ yeap, better to merge this one first. I hope https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-apl4/igt@i915_pm_...@engine-order.html is not related to this patch. should we trigger a retest? I was debating including patch 5 as part of this series but then it was touching the same code so I ended up including it. Sorry for the confusion. no worries. it makes sense now. Thanks for the patience but, anyway, thanks for improving the commit msg. Reviewed-by: Rodrigo Vivi mailto:rodrigo.v...@intel.com>> Thanks. -- Ashutosh
Re: [Intel-gfx] [PATCH 6/8] drm/i915/debugfs: Add perf_limit_reasons in debugfs
On Fri, 09 Sep 2022 03:13:05 -0700, Rodrigo Vivi wrote: > > On Wed, Sep 07, 2022 at 10:22:49PM -0700, Ashutosh Dixit wrote: > > From: Tilak Tangudu > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 24009786f88b..9492f8f43b25 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1802,6 +1802,7 @@ > > #define POWER_LIMIT_4_MASK REG_BIT(8) > > #define POWER_LIMIT_1_MASK REG_BIT(10) > > #define POWER_LIMIT_2_MASK REG_BIT(11) > > +#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) > > > > I'm kind of confused here because I saw the other bits in the patch 5. Sorry Rodrigo, patch 5 is a bug-fix patch which should probably be merged to -fixes independent of this series, I have posted it independently too: https://patchwork.freedesktop.org/series/108277/ I was debating including patch 5 as part of this series but then it was touching the same code so I ended up including it. Sorry for the confusion. > but, anyway, thanks for improving the commit msg. > > Reviewed-by: Rodrigo Vivi Thanks. -- Ashutosh
Re: [Intel-gfx] [PATCH 6/8] drm/i915/debugfs: Add perf_limit_reasons in debugfs
On Wed, Sep 07, 2022 at 10:22:49PM -0700, Ashutosh Dixit wrote:
> From: Tilak Tangudu
>
> Add perf_limit_reasons in debugfs. The upper 16 perf_limit_reasons RW "log"
> bits are identical to the lower 16 RO "status" bits except that the "log"
> bits remain set until cleared, thereby ensuring the throttling occurrence
> is not missed. The clear fop clears the upper 16 "log" bits, the get fop
> gets all 32 "log" and "status" bits.
>
> v2: Expand commit message and clarify "log" and "status" bits in
> comment (Rodrigo)
>
> Cc: Rodrigo Vivi
> Signed-off-by: Ashutosh Dixit
> Signed-off-by: Tilak Tangudu
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 108b9e76c32e..a009cf69103a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -655,6 +655,36 @@ static bool rps_eval(void *data)
>
> DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
>
> +static int perf_limit_reasons_get(void *data, u64 *val)
> +{
> + struct intel_gt *gt = data;
> + intel_wakeref_t wakeref;
> +
> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> + *val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
> +
> + return 0;
> +}
> +
> +static int perf_limit_reasons_clear(void *data, u64 val)
> +{
> + struct intel_gt *gt = data;
> + intel_wakeref_t wakeref;
> +
> + /*
> + * Clear the upper 16 "log" bits, the lower 16 "status" bits are
> + * read-only. The upper 16 "log" bits are identical to the lower 16
> + * "status" bits except that the "log" bits remain set until cleared.
> + */
> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> + intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
> + GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
> +
> + return 0;
> +}
> +DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get,
> + perf_limit_reasons_clear, "%llu\n");
> +
> void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
> {
> static const struct intel_gt_debugfs_file files[] = {
> @@ -664,6 +694,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt,
> struct dentry *root)
> { "forcewake_user", &forcewake_user_fops, NULL},
> { "llc", &llc_fops, llc_eval },
> { "rps_boost", &rps_boost_fops, rps_eval },
> + { "perf_limit_reasons", &perf_limit_reasons_fops, NULL },
> };
>
> intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 24009786f88b..9492f8f43b25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1802,6 +1802,7 @@
> #define POWER_LIMIT_4_MASK REG_BIT(8)
> #define POWER_LIMIT_1_MASK REG_BIT(10)
> #define POWER_LIMIT_2_MASK REG_BIT(11)
> +#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
>
I'm kind of confused here because I saw the other bits in the patch 5.
but, anyway, thanks for improving the commit msg.
Reviewed-by: Rodrigo Vivi
> #define CHV_CLK_CTL1 _MMIO(0x101100)
> #define VLV_CLK_CTL2 _MMIO(0x101104)
> --
> 2.34.1
>
[Intel-gfx] [PATCH 6/8] drm/i915/debugfs: Add perf_limit_reasons in debugfs
From: Tilak Tangudu
Add perf_limit_reasons in debugfs. The upper 16 perf_limit_reasons RW "log"
bits are identical to the lower 16 RO "status" bits except that the "log"
bits remain set until cleared, thereby ensuring the throttling occurrence
is not missed. The clear fop clears the upper 16 "log" bits, the get fop
gets all 32 "log" and "status" bits.
v2: Expand commit message and clarify "log" and "status" bits in
comment (Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Ashutosh Dixit
Signed-off-by: Tilak Tangudu
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 108b9e76c32e..a009cf69103a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -655,6 +655,36 @@ static bool rps_eval(void *data)
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
+static int perf_limit_reasons_get(void *data, u64 *val)
+{
+ struct intel_gt *gt = data;
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ *val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
+
+ return 0;
+}
+
+static int perf_limit_reasons_clear(void *data, u64 val)
+{
+ struct intel_gt *gt = data;
+ intel_wakeref_t wakeref;
+
+ /*
+* Clear the upper 16 "log" bits, the lower 16 "status" bits are
+* read-only. The upper 16 "log" bits are identical to the lower 16
+* "status" bits except that the "log" bits remain set until cleared.
+*/
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
+GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get,
+ perf_limit_reasons_clear, "%llu\n");
+
void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
@@ -664,6 +694,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt,
struct dentry *root)
{ "forcewake_user", &forcewake_user_fops, NULL},
{ "llc", &llc_fops, llc_eval },
{ "rps_boost", &rps_boost_fops, rps_eval },
+ { "perf_limit_reasons", &perf_limit_reasons_fops, NULL },
};
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24009786f88b..9492f8f43b25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1802,6 +1802,7 @@
#define POWER_LIMIT_4_MASK REG_BIT(8)
#define POWER_LIMIT_1_MASK REG_BIT(10)
#define POWER_LIMIT_2_MASK REG_BIT(11)
+#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
#define CHV_CLK_CTL1 _MMIO(0x101100)
#define VLV_CLK_CTL2 _MMIO(0x101104)
--
2.34.1
