Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
Chris Wilson writes:
> There's very little variation in non-privileged registers for Tigerlake,
> so we can mostly inherit the set from gen11. There is no whitelist at
> present, so we do not need to add any special registers.
>
> v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a
> variety of huc readonly status registers.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_ctx_isolation.c | 30 +-
> 1 file changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index df1d655ae..58b824e84 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -55,10 +55,11 @@ enum {
> #define GEN9 (ALL << 9)
> #define GEN10 (ALL << 10)
> #define GEN11 (ALL << 11)
> +#define GEN12 (ALL << 12)
>
> #define NOCTX 0
>
> -#define LAST_KNOWN_GEN 11
> +#define LAST_KNOWN_GEN 12
>
> static const struct named_register {
> const char *name;
> @@ -116,9 +117,9 @@ static const struct named_register {
> { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> - { "L3_Config", GEN8, RCS0, 0x7034 },
> - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
> - { "TD_CTL2", GEN8, RCS0, 0xe404 },
> + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
> + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
> { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> @@ -142,7 +143,9 @@ static const struct named_register {
> /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
> { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
> { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
> + { "COMMON_SLICE_CHICKEN2", GEN9, RCS0, 0x7014, .masked = true },
> { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
> + { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(9, 11), 0x731c, .masked = true
> },
> { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask =
> ~0x10 },
> { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked =
> true },
> { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
> @@ -178,6 +181,23 @@ static const struct named_register {
> { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 },
> { "VECS timestamp", GEN11, ~0u, 0x1c8358 },
>
> + /* huc read only */
> + { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2000 },
> + { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2014 },
> + { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x23b0 },
> +
> + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 },
> + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 },
> + { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 },
> +
> + { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2000 },
> + { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2014 },
> + { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x23b0 },
> +
> + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 },
> + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 },
> + { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 },
> +
> {}
> };
>
> @@ -852,7 +872,7 @@ igt_main
> gen = intel_gen(intel_get_drm_devid(fd));
>
> igt_warn_on_f(gen > LAST_KNOWN_GEN,
> - "GEN not recognized! Test needs to be
> updated to run.");
> + "GEN not recognized! Test needs to be updated to
> run.\n");
> igt_skip_on(gen > LAST_KNOWN_GEN);
> }
>
> --
> 2.23.0
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[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
There's very little variation in non-privileged registers for Tigerlake,
so we can mostly inherit the set from gen11. There is no whitelist at
present, so we do not need to add any special registers.
v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a
variety of huc readonly status registers.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
tests/i915/gem_ctx_isolation.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index df1d655ae..58b824e84 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -55,10 +55,11 @@ enum {
#define GEN9 (ALL << 9)
#define GEN10 (ALL << 10)
#define GEN11 (ALL << 11)
+#define GEN12 (ALL << 12)
#define NOCTX 0
-#define LAST_KNOWN_GEN 11
+#define LAST_KNOWN_GEN 12
static const struct named_register {
const char *name;
@@ -116,9 +117,9 @@ static const struct named_register {
{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
{ "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
{ "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
- { "L3_Config", GEN8, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
- { "TD_CTL2", GEN8, RCS0, 0xe404 },
+ { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
+ { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
+ { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
{ "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
{ "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
{ "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
@@ -142,7 +143,9 @@ static const struct named_register {
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
{ "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
+ { "COMMON_SLICE_CHICKEN2", GEN9, RCS0, 0x7014, .masked = true },
{ "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
+ { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(9, 11), 0x731c, .masked = true
},
{ "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask =
~0x10 },
{ "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked =
true },
{ "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
@@ -178,6 +181,23 @@ static const struct named_register {
{ "VCS3 timestamp", GEN11, ~0u, 0x1d4358 },
{ "VECS timestamp", GEN11, ~0u, 0x1c8358 },
+ /* huc read only */
+ { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2000 },
+ { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2014 },
+ { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x23b0 },
+
+ { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 },
+ { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 },
+ { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 },
+
+ { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2000 },
+ { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2014 },
+ { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x23b0 },
+
+ { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 },
+ { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 },
+ { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 },
+
{}
};
@@ -852,7 +872,7 @@ igt_main
gen = intel_gen(intel_get_drm_devid(fd));
igt_warn_on_f(gen > LAST_KNOWN_GEN,
- "GEN not recognized! Test needs to be
updated to run.");
+ "GEN not recognized! Test needs to be updated to
run.\n");
igt_skip_on(gen > LAST_KNOWN_GEN);
}
--
2.23.0
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
Quoting Stimson, Dale B (2019-10-04 00:26:24)
> > On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote:
> > > There's very little variation in non-privileged registers for Tigerlake,
> > > so we can mostly inherit the set from gen11. There is no whitelist at
> > > present, so we do not need to add any special registers.
> > >
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> > > Signed-off-by: Chris Wilson
> > > ---
> > > tests/i915/gem_ctx_isolation.c | 11 ++-
> > > 1 file changed, 6 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/tests/i915/gem_ctx_isolation.c
> > > b/tests/i915/gem_ctx_isolation.c
> > > index df1d655ae..819daafc3 100644
> > > --- a/tests/i915/gem_ctx_isolation.c
> > > +++ b/tests/i915/gem_ctx_isolation.c
> > > @@ -55,10 +55,11 @@ enum {
> > > #define GEN9 (ALL << 9)
> > > #define GEN10 (ALL << 10)
> > > #define GEN11 (ALL << 11)
> > > +#define GEN12 (ALL << 12)
> > >
> > > #define NOCTX 0
> > >
> > > -#define LAST_KNOWN_GEN 11
> > > +#define LAST_KNOWN_GEN 12
> > >
> > > static const struct named_register {
> > > const char *name;
> > > @@ -116,9 +117,9 @@ static const struct named_register {
> > > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> > > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> > > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> > > - { "L3_Config", GEN8, RCS0, 0x7034 },
> > > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
> > > - { "TD_CTL2", GEN8, RCS0, 0xe404 },
> > > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> > > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
> > > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
> > > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> > > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> > > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> > > @@ -852,7 +853,7 @@ igt_main
> > > gen = intel_gen(intel_get_drm_devid(fd));
> > >
> > > igt_warn_on_f(gen > LAST_KNOWN_GEN,
> > > - "GEN not recognized! Test needs to
> > > be updated to run.");
> > > + "GEN not recognized! Test needs to be updated
> > > to run.");
> > > igt_skip_on(gen > LAST_KNOWN_GEN);
>
> On 2019-10-02 14:38:31, Petri Latvala wrote:
> > Thanks to this editorial change, we're able to see that this string is
> > missing a newline character.
>
> Your patch looks good (as does Petri's comment).
>
> I had identified the same registers as in the patch, but had one additional
> register. Should it be included?
>
> + { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked =
> true },
>
> I did some testing on a TGL with your patch. There are two pre-existing
> issues, both of which I have encountered before. These are that the S3/S4
> test
> never wakes up, and errors reported by nonpriv for vcs'2 registers. See
> below.
>
> Because of the S3/S4 issues, running gem_ctx_isolation for Gen12 will require
> subsequent reboot. Should gem_ctx_isolation temporarily disable the S3/S4
> tests for Gen12 until this problem is resolved?
No. Fix the problem; it's to do with the interrupts being fubar.
> I have been doing some work to address the vcs issue, which I will send
> to the mailing list soon. The vcs issue is due to confusion between the
> physical engine really being vcs'2, and the kernel presenting the engine to
> usermode as vcs1. The test refers to the vcs'2 registers via the mmio_base
> expected for vcs1 and therefore fails. Planned solution: "MMIO Remapping"
> for ICL and later.
Or see the patches to expose the mmio_base. If push comes to shove, it's
already given in debugfs for precisely this purpose.
-Chris
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
> On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote:
> > There's very little variation in non-privileged registers for Tigerlake,
> > so we can mostly inherit the set from gen11. There is no whitelist at
> > present, so we do not need to add any special registers.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> > Signed-off-by: Chris Wilson
> > ---
> > tests/i915/gem_ctx_isolation.c | 11 ++-
> > 1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > index df1d655ae..819daafc3 100644
> > --- a/tests/i915/gem_ctx_isolation.c
> > +++ b/tests/i915/gem_ctx_isolation.c
> > @@ -55,10 +55,11 @@ enum {
> > #define GEN9 (ALL << 9)
> > #define GEN10 (ALL << 10)
> > #define GEN11 (ALL << 11)
> > +#define GEN12 (ALL << 12)
> >
> > #define NOCTX 0
> >
> > -#define LAST_KNOWN_GEN 11
> > +#define LAST_KNOWN_GEN 12
> >
> > static const struct named_register {
> > const char *name;
> > @@ -116,9 +117,9 @@ static const struct named_register {
> > { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> > { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> > { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> > - { "L3_Config", GEN8, RCS0, 0x7034 },
> > - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
> > - { "TD_CTL2", GEN8, RCS0, 0xe404 },
> > + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> > + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
> > + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
> > { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> > { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> > { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> > @@ -852,7 +853,7 @@ igt_main
> > gen = intel_gen(intel_get_drm_devid(fd));
> >
> > igt_warn_on_f(gen > LAST_KNOWN_GEN,
> > - "GEN not recognized! Test needs to be
> > updated to run.");
> > + "GEN not recognized! Test needs to be updated to
> > run.");
> > igt_skip_on(gen > LAST_KNOWN_GEN);
On 2019-10-02 14:38:31, Petri Latvala wrote:
> Thanks to this editorial change, we're able to see that this string is
> missing a newline character.
Your patch looks good (as does Petri's comment).
I had identified the same registers as in the patch, but had one additional
register. Should it be included?
+ { "COMMON_SLICE_CHICKEN2", GEN_RANGE(12, 12), RCS0, 0x7014, .masked =
true },
I did some testing on a TGL with your patch. There are two pre-existing
issues, both of which I have encountered before. These are that the S3/S4 test
never wakes up, and errors reported by nonpriv for vcs'2 registers. See below.
Because of the S3/S4 issues, running gem_ctx_isolation for Gen12 will require
subsequent reboot. Should gem_ctx_isolation temporarily disable the S3/S4
tests for Gen12 until this problem is resolved?
I have been doing some work to address the vcs issue, which I will send
to the mailing list soon. The vcs issue is due to confusion between the
physical engine really being vcs'2, and the kernel presenting the engine to
usermode as vcs1. The test refers to the vcs'2 registers via the mmio_base
expected for vcs1 and therefore fails. Planned solution: "MMIO Remapping"
for ICL and later.
Results for gem_ctx_isolation
Never wakes from rcs0-S3 or rcs0-S4. (Probably also true for *-S3 and *-s4).
Starting subtest: rcs0-S3
[cmd] rtcwake: assuming RTC uses UTC ...
rtcwake: wakeup from "mem" using /dev/rtc0 at Thu Oct 3 17:45:41 2019
The following diagnostic is due to confusion between the physical engine
really being vcs'2, and the kernel presenting the engine to usermode as vcs1.
The test refers to the registers via the mmio_base expected for vcs1 and
therefore fails.
Starting subtest: vcs1-nonpriv
(gem_ctx_isolation:2152) WARNING: Register 0x1c4600 (VCS1_GPR[0]):
A= B=
(gem_ctx_isolation:2152) WARNING: Register 0x1c4604 (VCS1_GPR[1]):
A= B=
...and so on
Tested with:
-
Local kernel branch:
Based on git://anongit.freedesktop.org/drm-tip
Branch drm-tip
fd44976bff7a drm-tip: 2019y-10m-03d-15h-13m-54s UTC integration manifest
-
Local igt branch:
Based on https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
branch master:
74f55119 (public/master) i915/gem_eio: Relax timeout for forced resets
Plus your patch:
i915/gem_ctx_isolation: Bump support for Tigerlake
Plus a test patch to bypass S3 and S4 tests so other results could be seen:
tests/i915/gem_ctx_isolation.c - Suppress suspend/resume tests
-Dale
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Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
On Wed, Oct 02, 2019 at 12:26:48PM +0100, Chris Wilson wrote:
> There's very little variation in non-privileged registers for Tigerlake,
> so we can mostly inherit the set from gen11. There is no whitelist at
> present, so we do not need to add any special registers.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_ctx_isolation.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index df1d655ae..819daafc3 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -55,10 +55,11 @@ enum {
> #define GEN9 (ALL << 9)
> #define GEN10 (ALL << 10)
> #define GEN11 (ALL << 11)
> +#define GEN12 (ALL << 12)
>
> #define NOCTX 0
>
> -#define LAST_KNOWN_GEN 11
> +#define LAST_KNOWN_GEN 12
>
> static const struct named_register {
> const char *name;
> @@ -116,9 +117,9 @@ static const struct named_register {
> { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> - { "L3_Config", GEN8, RCS0, 0x7034 },
> - { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
> - { "TD_CTL2", GEN8, RCS0, 0xe404 },
> + { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
> + { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
> + { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
> { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
> { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
> { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
> @@ -852,7 +853,7 @@ igt_main
> gen = intel_gen(intel_get_drm_devid(fd));
>
> igt_warn_on_f(gen > LAST_KNOWN_GEN,
> - "GEN not recognized! Test needs to be
> updated to run.");
> + "GEN not recognized! Test needs to be updated to
> run.");
> igt_skip_on(gen > LAST_KNOWN_GEN);
Thanks to this editorial change, we're able to see that this string is
missing a newline character.
--
Petri Latvala
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[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake
There's very little variation in non-privileged registers for Tigerlake,
so we can mostly inherit the set from gen11. There is no whitelist at
present, so we do not need to add any special registers.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_isolation.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index df1d655ae..819daafc3 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -55,10 +55,11 @@ enum {
#define GEN9 (ALL << 9)
#define GEN10 (ALL << 10)
#define GEN11 (ALL << 11)
+#define GEN12 (ALL << 12)
#define NOCTX 0
-#define LAST_KNOWN_GEN 11
+#define LAST_KNOWN_GEN 12
static const struct named_register {
const char *name;
@@ -116,9 +117,9 @@ static const struct named_register {
{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
{ "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
{ "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
- { "L3_Config", GEN8, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
- { "TD_CTL2", GEN8, RCS0, 0xe404 },
+ { "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
+ { "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0x },
+ { "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
{ "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
{ "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
{ "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
@@ -852,7 +853,7 @@ igt_main
gen = intel_gen(intel_get_drm_devid(fd));
igt_warn_on_f(gen > LAST_KNOWN_GEN,
- "GEN not recognized! Test needs to be
updated to run.");
+ "GEN not recognized! Test needs to be updated to
run.");
igt_skip_on(gen > LAST_KNOWN_GEN);
}
--
2.23.0
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