Re: [Intel-gfx] [PATCH i-g-t v4 2/2] i915/gem_ctx_isolation: Check engine relative registers (revised)
On 2/14/20 6:33 PM, Dale B Stimson wrote: From: Chris Wilson Some of the non-privileged registers are at the same offset on each engine. We can improve our coverage for unknown HW layout by using the reported engine->mmio_base for relative offsets. Subsequent to sign-off by Chris Wilson, added by Dale B Stimson: Modify previous "i915/gem_ctx_isolation: Check engine relative registers" to support alternative mmio_base infrastructure API. Signed-off-by: Chris Wilson Signed-off-by: Dale B Stimson Acked-by: Robert M. Fosha --- lib/i915/gem_mmio_base.c | 7 +- tests/i915/gem_ctx_isolation.c | 229 - 2 files changed, 141 insertions(+), 95 deletions(-) diff --git a/lib/i915/gem_mmio_base.c b/lib/i915/gem_mmio_base.c index d1b83221a..c712b4431 100644 --- a/lib/i915/gem_mmio_base.c +++ b/lib/i915/gem_mmio_base.c @@ -286,13 +286,14 @@ struct eng_mmio_base_table_s *gem_engine_mmio_base_info_get(int fd_dev) { struct eng_mmio_base_table_s *mbp = NULL; - /* If and when better ways are provided to find the mmio_base -* information, they may be added them here in order of preference. + /* If and when more desirable ways exist to find the mmio_base +* information, they may be added here, in order of consideration. */ #if 0 + /* Anticipating a future method: */ if (!mbp) - mbp = _mmio_base_info_get_via_sysfs(fd_dev); + mbp = _gem_engine_mmio_base_info_get_sysfs(fd_dev); #endif if (!mbp) diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c index 1b66fec11..07ffbb84a 100644 --- a/tests/i915/gem_ctx_isolation.c +++ b/tests/i915/gem_ctx_isolation.c @@ -70,6 +70,7 @@ static const struct named_register { uint32_t ignore_bits; uint32_t write_mask; /* some registers bits do not exist */ bool masked; + bool relative; } nonpriv_registers[] = { { "NOPID", NOCTX, RCS0, 0x2094 }, { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc }, @@ -109,7 +110,6 @@ static const struct named_register { { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 }, { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 }, { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c }, - { "CS_GPR", GEN8, RCS0, 0x2600, 32 }, { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 }, { "OACTXID", GEN8, RCS0, 0x2364 }, { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 }, @@ -138,79 +138,56 @@ static const struct named_register { { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 }, { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true }, - { "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true }, /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */ { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 }, { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true }, { "COMMON_SLICE_CHICKEN2", GEN_RANGE(9, 9), RCS0, 0x7014, .masked = true }, - { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true }, + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true }, { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(11, 11) /* + glk */, RCS0, 0x731c, .masked = true }, { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x10 }, { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true }, { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true }, - { "BCS_GPR", GEN9, BCS0, 0x22600, 32 }, { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true }, { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 }, { "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 }, - { "VCS0_GPR", GEN_RANGE(9, 10), VCS0, 0x12600, 32 }, - { "VCS1_GPR", GEN_RANGE(9, 10), VCS1, 0x1c600, 32 }, - { "VECS_GPR", GEN_RANGE(9, 10), VECS0, 0x1a600, 32 }, - - { "VCS0_GPR", GEN11, VCS0, 0x1c0600, 32 }, - { "VCS1_GPR", GEN11, VCS1, 0x1c4600, 32 }, - { "VCS2_GPR", GEN11, VCS2, 0x1d0600, 32 }, - { "VCS3_GPR", GEN11, VCS3, 0x1d4600, 32 }, - { "VECS_GPR", GEN11, VECS0, 0x1c8600, 32 }, + { "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true }, {} }, ignore_registers[] = { { "RCS timestamp", GEN6, ~0u, 0x2358 }, { "BCS timestamp", GEN7, ~0u, 0x22358 }, - { "VCS0 timestamp", GEN_RANGE(7, 10), ~0u, 0x12358 }, - { "VCS1 timestamp", GEN_RANGE(7, 10), ~0u, 0x1c358 }, - { "VECS timestamp", GEN_RANGE(8, 10), ~0u, 0x1a358 }, - - { "VCS0 timestamp", GEN11, ~0u, 0x1c0358 }, - { "VCS1 timestamp", GEN11, ~0u, 0x1c4358 }, - { "VCS2 timestamp", GEN11, ~0u, 0x1d0358 }, - { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 }, - { "VECS timestamp", GEN11, ~0u, 0x1c8358 }, + { "xCS timestamp", GEN8, ALL, 0x358, .relative = true }, /* huc read only */ - { "BSD0 0x2000",
[Intel-gfx] [PATCH i-g-t v4 2/2] i915/gem_ctx_isolation: Check engine relative registers (revised)
From: Chris Wilson Some of the non-privileged registers are at the same offset on each engine. We can improve our coverage for unknown HW layout by using the reported engine->mmio_base for relative offsets. Subsequent to sign-off by Chris Wilson, added by Dale B Stimson: Modify previous "i915/gem_ctx_isolation: Check engine relative registers" to support alternative mmio_base infrastructure API. Signed-off-by: Chris Wilson Signed-off-by: Dale B Stimson --- lib/i915/gem_mmio_base.c | 7 +- tests/i915/gem_ctx_isolation.c | 229 - 2 files changed, 141 insertions(+), 95 deletions(-) diff --git a/lib/i915/gem_mmio_base.c b/lib/i915/gem_mmio_base.c index d1b83221a..c712b4431 100644 --- a/lib/i915/gem_mmio_base.c +++ b/lib/i915/gem_mmio_base.c @@ -286,13 +286,14 @@ struct eng_mmio_base_table_s *gem_engine_mmio_base_info_get(int fd_dev) { struct eng_mmio_base_table_s *mbp = NULL; - /* If and when better ways are provided to find the mmio_base -* information, they may be added them here in order of preference. + /* If and when more desirable ways exist to find the mmio_base +* information, they may be added here, in order of consideration. */ #if 0 + /* Anticipating a future method: */ if (!mbp) - mbp = _mmio_base_info_get_via_sysfs(fd_dev); + mbp = _gem_engine_mmio_base_info_get_sysfs(fd_dev); #endif if (!mbp) diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c index 1b66fec11..07ffbb84a 100644 --- a/tests/i915/gem_ctx_isolation.c +++ b/tests/i915/gem_ctx_isolation.c @@ -70,6 +70,7 @@ static const struct named_register { uint32_t ignore_bits; uint32_t write_mask; /* some registers bits do not exist */ bool masked; + bool relative; } nonpriv_registers[] = { { "NOPID", NOCTX, RCS0, 0x2094 }, { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc }, @@ -109,7 +110,6 @@ static const struct named_register { { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 }, { "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 }, { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c }, - { "CS_GPR", GEN8, RCS0, 0x2600, 32 }, { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 }, { "OACTXID", GEN8, RCS0, 0x2364 }, { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 }, @@ -138,79 +138,56 @@ static const struct named_register { { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 }, { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true }, - { "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true }, /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */ { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 }, { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true }, { "COMMON_SLICE_CHICKEN2", GEN_RANGE(9, 9), RCS0, 0x7014, .masked = true }, - { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true }, + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true }, { "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(11, 11) /* + glk */, RCS0, 0x731c, .masked = true }, { "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x10 }, { "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true }, { "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true }, - { "BCS_GPR", GEN9, BCS0, 0x22600, 32 }, { "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true }, { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 }, { "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 }, - { "VCS0_GPR", GEN_RANGE(9, 10), VCS0, 0x12600, 32 }, - { "VCS1_GPR", GEN_RANGE(9, 10), VCS1, 0x1c600, 32 }, - { "VECS_GPR", GEN_RANGE(9, 10), VECS0, 0x1a600, 32 }, - - { "VCS0_GPR", GEN11, VCS0, 0x1c0600, 32 }, - { "VCS1_GPR", GEN11, VCS1, 0x1c4600, 32 }, - { "VCS2_GPR", GEN11, VCS2, 0x1d0600, 32 }, - { "VCS3_GPR", GEN11, VCS3, 0x1d4600, 32 }, - { "VECS_GPR", GEN11, VECS0, 0x1c8600, 32 }, + { "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true }, {} }, ignore_registers[] = { { "RCS timestamp", GEN6, ~0u, 0x2358 }, { "BCS timestamp", GEN7, ~0u, 0x22358 }, - { "VCS0 timestamp", GEN_RANGE(7, 10), ~0u, 0x12358 }, - { "VCS1 timestamp", GEN_RANGE(7, 10), ~0u, 0x1c358 }, - { "VECS timestamp", GEN_RANGE(8, 10), ~0u, 0x1a358 }, - - { "VCS0 timestamp", GEN11, ~0u, 0x1c0358 }, - { "VCS1 timestamp", GEN11, ~0u, 0x1c4358 }, - { "VCS2 timestamp", GEN11, ~0u, 0x1d0358 }, - { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 }, - { "VECS timestamp", GEN11, ~0u, 0x1c8358 }, + { "xCS timestamp", GEN8, ALL, 0x358, .relative = true }, /* huc read only */ - { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2000 }, - { "BSD0