[Intel-gfx] [PATCH igt] igt/prime_mmap_coherency: Remove manual gem_sync() calls
Emphasize that we want to test synchronisation using the dmabuf API (prime_sync_start, prime_sync_end) and so drop the manual synchronisation using the GEM API (gem_sync). Signed-off-by: Chris Wilson Reviewed-by: Daniel Vetter --- tests/prime_mmap_coherency.c | 4 1 file changed, 4 deletions(-) diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c index ffd2d751..192b4348 100644 --- a/tests/prime_mmap_coherency.c +++ b/tests/prime_mmap_coherency.c @@ -62,7 +62,6 @@ static int test_read_flush(void) * the GTT domain. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); intel_copy_bo(batch, bo_1, bo_2, width * height); - gem_sync(fd, bo_1->handle); drm_intel_bo_unreference(bo_2); /* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */ @@ -86,7 +85,6 @@ static int test_read_flush(void) prime_sync_end(dma_buf_fd, false); intel_copy_bo(batch, bo_1, bo_2, width * height); - gem_sync(fd, bo_1->handle); drm_intel_bo_unreference(bo_2); /* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we @@ -129,7 +127,6 @@ static int test_write_flush(void) * the GTT domain. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); intel_copy_bo(batch, bo_1, bo_2, width * height); - gem_sync(fd, bo_1->handle); drm_intel_bo_unreference(bo_2); /* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */ @@ -149,7 +146,6 @@ static int test_write_flush(void) /* STEP #3: Copy BO 1 into BO 2, using blitter. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); intel_copy_bo(batch, bo_2, bo_1, width * height); - gem_sync(fd, bo_2->handle); /* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there * should be some cache lines that didn't get flushed out and are still 0, -- 2.15.0.rc2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt] igt/prime_mmap_coherency: Remove manual gem_sync() calls
Emphasize that we want to test synchronisation using the dmabuf API (prime_sync_start, prime_sync_end) and so drop the manual synchronisation using the GEM API (gem_sync). Signed-off-by: Chris Wilson Reviewed-by: Daniel Vetter --- tests/prime_mmap_coherency.c | 4 1 file changed, 4 deletions(-) diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c index ffd2d751..192b4348 100644 --- a/tests/prime_mmap_coherency.c +++ b/tests/prime_mmap_coherency.c @@ -62,7 +62,6 @@ static int test_read_flush(void) * the GTT domain. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); intel_copy_bo(batch, bo_1, bo_2, width * height); - gem_sync(fd, bo_1->handle); drm_intel_bo_unreference(bo_2); /* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */ @@ -86,7 +85,6 @@ static int test_read_flush(void) prime_sync_end(dma_buf_fd, false); intel_copy_bo(batch, bo_1, bo_2, width * height); - gem_sync(fd, bo_1->handle); drm_intel_bo_unreference(bo_2); /* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we @@ -129,7 +127,6 @@ static int test_write_flush(void) * the GTT domain. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); intel_copy_bo(batch, bo_1, bo_2, width * height); - gem_sync(fd, bo_1->handle); drm_intel_bo_unreference(bo_2); /* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */ @@ -149,7 +146,6 @@ static int test_write_flush(void) /* STEP #3: Copy BO 1 into BO 2, using blitter. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); intel_copy_bo(batch, bo_2, bo_1, width * height); - gem_sync(fd, bo_2->handle); /* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there * should be some cache lines that didn't get flushed out and are still 0, -- 2.15.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt] igt/prime_mmap_coherency: Remove manual gem_sync() calls
On Thu, Oct 19, 2017 at 07:23:07AM +0100, Chris Wilson wrote: > Emphasize that we want to test synchronisation using the dmabuf API > (prime_sync_start, prime_sync_end) and so drop the manual > synchronisation using the GEM API (gem_sync). > > Signed-off-by: Chris Wilson Assuming CI approves too: Reviewed-by: Daniel Vetter > --- > tests/prime_mmap_coherency.c | 4 > 1 file changed, 4 deletions(-) > > diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c > index ffd2d751..192b4348 100644 > --- a/tests/prime_mmap_coherency.c > +++ b/tests/prime_mmap_coherency.c > @@ -62,7 +62,6 @@ static int test_read_flush(void) >* the GTT domain. */ > bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); > intel_copy_bo(batch, bo_1, bo_2, width * height); > - gem_sync(fd, bo_1->handle); > drm_intel_bo_unreference(bo_2); > > /* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU > caches. */ > @@ -86,7 +85,6 @@ static int test_read_flush(void) > prime_sync_end(dma_buf_fd, false); > > intel_copy_bo(batch, bo_1, bo_2, width * height); > - gem_sync(fd, bo_1->handle); > drm_intel_bo_unreference(bo_2); > > /* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes > sure we > @@ -129,7 +127,6 @@ static int test_write_flush(void) >* the GTT domain. */ > bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); > intel_copy_bo(batch, bo_1, bo_2, width * height); > - gem_sync(fd, bo_1->handle); > drm_intel_bo_unreference(bo_2); > > /* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */ > @@ -149,7 +146,6 @@ static int test_write_flush(void) > /* STEP #3: Copy BO 1 into BO 2, using blitter. */ > bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); > intel_copy_bo(batch, bo_2, bo_1, width * height); > - gem_sync(fd, bo_2->handle); > > /* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there >* should be some cache lines that didn't get flushed out and are still > 0, > -- > 2.15.0.rc1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt] igt/prime_mmap_coherency: Remove manual gem_sync() calls
Emphasize that we want to test synchronisation using the dmabuf API (prime_sync_start, prime_sync_end) and so drop the manual synchronisation using the GEM API (gem_sync). Signed-off-by: Chris Wilson --- tests/prime_mmap_coherency.c | 4 1 file changed, 4 deletions(-) diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c index ffd2d751..192b4348 100644 --- a/tests/prime_mmap_coherency.c +++ b/tests/prime_mmap_coherency.c @@ -62,7 +62,6 @@ static int test_read_flush(void) * the GTT domain. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); intel_copy_bo(batch, bo_1, bo_2, width * height); - gem_sync(fd, bo_1->handle); drm_intel_bo_unreference(bo_2); /* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */ @@ -86,7 +85,6 @@ static int test_read_flush(void) prime_sync_end(dma_buf_fd, false); intel_copy_bo(batch, bo_1, bo_2, width * height); - gem_sync(fd, bo_1->handle); drm_intel_bo_unreference(bo_2); /* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we @@ -129,7 +127,6 @@ static int test_write_flush(void) * the GTT domain. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); intel_copy_bo(batch, bo_1, bo_2, width * height); - gem_sync(fd, bo_1->handle); drm_intel_bo_unreference(bo_2); /* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */ @@ -149,7 +146,6 @@ static int test_write_flush(void) /* STEP #3: Copy BO 1 into BO 2, using blitter. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); intel_copy_bo(batch, bo_2, bo_1, width * height); - gem_sync(fd, bo_2->handle); /* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there * should be some cache lines that didn't get flushed out and are still 0, -- 2.15.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
