Re: [Intel-gfx] [PATCH v1] drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation

2015-12-17 Thread kbuild test robot 
Hi Alex,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20151217]
[cannot apply to v4.4-rc5]

url:
https://github.com/0day-ci/linux/commits/yu-dai-intel-com/drm-i915-guc-Add-GuC-ADS-Addition-Data-Structure-allocation/20151218-030155
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-nfsroot (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/i915_guc_submission.c: In function 'guc_create_ads':
>> drivers/gpu/drm/i915/i915_guc_submission.c:870:28: error: implicit 
>> declaration of function 'intel_lr_context_size' 
>> [-Werror=implicit-function-declaration]
  ads->eng_state_size[i] = intel_lr_context_size(ring);
   ^
   cc1: some warnings being treated as errors

vim +/intel_lr_context_size +870 drivers/gpu/drm/i915/i915_guc_submission.c

   864   * to find it.
   865   */
   866  ring = _priv->ring[RCS];
   867  ads->golden_context_lrca = ring->status_page.gfx_addr;
   868  
   869  for_each_ring(ring, dev_priv, i)
 > 870  ads->eng_state_size[i] = intel_lr_context_size(ring);
   871  
   872  kunmap_atomic(ads);
   873  }

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data
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[Intel-gfx] [PATCH v1] drm/i915/guc: Add GuC ADS (Addition Data Structure) - allocation

2015-12-17 Thread yu . dai 
From: Alex Dai 

The GuC firmware uses this for various purposes. The ADS itself is
a chunk of memory created by driver to share with GuC. Its members
are usually addresses telling where GuC to access them, including
things like scheduler policies, register list that will be saved
and restored during reset etc.

This is the first patch of a series to enable GuC ADS. For now, we
only create the ADS obj whilst keep it disabled.

v1: remove dead code checking return of kmap_atomic (Chris Wilson)

Signed-off-by: Alex Dai 

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
b/drivers/gpu/drm/i915/i915_guc_reg.h
index 90a84b4..8d27c09 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -40,6 +40,7 @@
 #define   GS_MIA_CORE_STATE  (1 << GS_MIA_SHIFT)
 
 #define SOFT_SCRATCH(n)_MMIO(0xc180 + (n) * 4)
+#define SOFT_SCRATCH_COUNT 16
 
 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
 #define   UOS_RSA_SCRATCH_MAX_COUNT  64
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 7554d16..28531e6 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -842,6 +842,46 @@ static void guc_create_log(struct intel_guc *guc)
guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
 }
 
+static void guc_create_ads(struct intel_guc *guc)
+{
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   struct drm_i915_gem_object *obj;
+   struct guc_ads *ads;
+   struct intel_engine_cs *ring;
+   struct page *page;
+   u32 size, i;
+
+   /* The ads obj includes the struct itself and buffers passed to GuC */
+   size = sizeof(struct guc_ads);
+
+   obj = guc->ads_obj;
+   if (!obj) {
+   obj = gem_allocate_guc_obj(dev_priv->dev, PAGE_ALIGN(size));
+   if (!obj)
+   return;
+
+   guc->ads_obj = obj;
+   }
+
+   page = i915_gem_object_get_page(obj, 0);
+   ads = kmap_atomic(page);
+
+   /*
+* The GuC requires a "Golden Context" when it reinitialises
+* engines after a reset. Here we use the Render ring default
+* context, which must already exist and be pinned in the GGTT,
+* so its address won't change after we've told the GuC where
+* to find it.
+*/
+   ring = _priv->ring[RCS];
+   ads->golden_context_lrca = ring->status_page.gfx_addr;
+
+   for_each_ring(ring, dev_priv, i)
+   ads->eng_state_size[i] = intel_lr_context_size(ring);
+
+   kunmap_atomic(ads);
+}
+
 /*
  * Set up the memory resources to be shared with the GuC.  At this point,
  * we require just one object that can be mapped through the GGTT.
@@ -868,6 +908,8 @@ int i915_guc_submission_init(struct drm_device *dev)
 
guc_create_log(guc);
 
+   guc_create_ads(guc);
+
return 0;
 }
 
@@ -906,6 +948,9 @@ void i915_guc_submission_fini(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_guc *guc = _priv->guc;
 
+   gem_release_guc_obj(dev_priv->guc.ads_obj);
+   guc->ads_obj = NULL;
+
gem_release_guc_obj(dev_priv->guc.log_obj);
guc->log_obj = NULL;
 
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 5cf555d..5c9f894 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -89,6 +89,8 @@ struct intel_guc {
uint32_t log_flags;
struct drm_i915_gem_object *log_obj;
 
+   struct drm_i915_gem_object *ads_obj;
+
struct drm_i915_gem_object *ctx_pool_obj;
struct ida ctx_ids;
 
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index eaa50a4..76ecc85 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -81,11 +81,14 @@
 #define GUC_CTL_CTXINFO0
 #define   GUC_CTL_CTXNUM_IN16_SHIFT0
 #define   GUC_CTL_BASE_ADDR_SHIFT  12
+
 #define GUC_CTL_ARAT_HIGH  1
 #define GUC_CTL_ARAT_LOW   2
+
 #define GUC_CTL_DEVICE_INFO3
 #define   GUC_CTL_GTTYPE_SHIFT 0
 #define   GUC_CTL_COREFAMILY_SHIFT 7
+
 #define GUC_CTL_LOG_PARAMS 4
 #define   GUC_LOG_VALID(1 << 0)
 #define   GUC_LOG_NOTIFY_ON_HALF_FULL  (1 << 1)
@@ -97,9 +100,12 @@
 #define   GUC_LOG_ISR_PAGES3
 #define   GUC_LOG_ISR_SHIFT9
 #define   GUC_LOG_BUF_ADDR_SHIFT   12
+
 #define GUC_CTL_PAGE_FAULT_CONTROL 5
+
 #define GUC_CTL_WA 6
 #define   GUC_CTL_WA_UK_BY_DRIVER  (1 << 3)
+
 #define GUC_CTL_FEATURE7
 #define   GUC_CTL_VCS2_ENABLED (1 << 0)
 #define   GUC_CTL_KERNEL_SUBMISSIONS   (1 << 1)
@@ -109,6 +115,7 @@