Re: [Intel-gfx] [PATCH v1] drm/i915/icl: Define MOCS table for Icelake

2018-10-31 Thread Lucas De Marchi 
On Fri, Oct 19, 2018 at 05:19:28PM +0200, Tomasz Lis wrote:
> The table has been unified across OSes to minimize virtualization overhead.
> 
> The MOCS table is now versioned; the patch includes version 1 entries.
> 
> BSpec: 34007
> BSpec: 560
> Signed-off-by: Tomasz Lis 
> Cc: Joonas Lahtinen 
> Cc: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Zhenyu Wang 
> ---

Can you please resubmit this series with only the patches not dropped?
This currently fails CI as CI is adding/dropping patches:
https://patchwork.freedesktop.org/series/51258/

Lucas De Marchi

>  drivers/gpu/drm/i915/intel_mocs.c | 246 
> +-
>  1 file changed, 244 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
> b/drivers/gpu/drm/i915/intel_mocs.c
> index 77e9871..b76d6db 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
>  #define LE_SCC(value)((value) << 8)
>  #define LE_PFM(value)((value) << 11)
>  #define LE_SCF(value)((value) << 14)
> +#define LE_CoS(value)((value) << 15)
> +#define LE_SSE(value)((value) << 17)
>  
>  /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
>  #define L3_ESC(value)((value) << 0)
> @@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
>   *   may only be updated incrementally by adding entries at the
>   *   end.
>   */
> +static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
> + [0] = {
> +   /* Base - Uncached (Deprecated) */
> +   .control_value = LE_CACHEABILITY(LE_UC) |
> +LE_TGT_CACHE(LE_TC_LLC) |
> +LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +   .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> + },
> + [1] = {
> +   /* Base - L3 + LeCC:PAT (Deprecated) */
> +   .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +LE_TGT_CACHE(LE_TC_LLC) |
> +LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +   .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> + },
> + [2] = {
> +   /* Base - L3 + LLC */
> +   .control_value = LE_CACHEABILITY(LE_WB) |
> +LE_TGT_CACHE(LE_TC_LLC) |
> +LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +   .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> + },
> + [3] = {
> +   /* Base - Uncached */
> +   .control_value = LE_CACHEABILITY(LE_UC) |
> +LE_TGT_CACHE(LE_TC_LLC) |
> +LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +   .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> + },
> + [4] = {
> +   /* Base - L3 */
> +   .control_value = LE_CACHEABILITY(LE_UC) |
> +LE_TGT_CACHE(LE_TC_LLC) |
> +LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +   .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> + },
> + [5] = {
> +   /* Base - LLC */
> +   .control_value = LE_CACHEABILITY(LE_WB) |
> +LE_TGT_CACHE(LE_TC_LLC) |
> +LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +   .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> + },
> + [6] = {
> +   /* Age 0 - LLC */
> +   .control_value = LE_CACHEABILITY(LE_WB) |
> +LE_TGT_CACHE(LE_TC_LLC) |
> +LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +   .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> + },
> + [7] = {
> +   /* Age 0 - L3 + LLC */
> +   .control_value = LE_CACHEABILITY(LE_WB) |
> +LE_TGT_CACHE(LE_TC_LLC) |
> +LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +   .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> + },
> + [8] = {
> +   /* Age: Don't Chg. - LLC */
> +   .control_value = LE_CACHEABILITY(LE_WB) |
> +LE_TGT_CACHE(LE_TC_LLC) |
> +LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +

Re: [Intel-gfx] [PATCH v1] drm/i915/icl: Define MOCS table for Icelake

2018-10-19 Thread Lionel Landwerlin 

On 19/10/2018 17:19, Daniele Ceraolo Spurio wrote:
CC some mesa people here? not sure who the right contact would be for 
this 

Adding Anuj.

-
Lionel
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Re: [Intel-gfx] [PATCH v1] drm/i915/icl: Define MOCS table for Icelake

2018-10-19 Thread Daniele Ceraolo Spurio 



On 19/10/18 08:19, Tomasz Lis wrote:

The table has been unified across OSes to minimize virtualization overhead.

The MOCS table is now versioned; the patch includes version 1 entries.


A bit more explanation is required here. We need to make clear the fact 
that existing entries in the table for a given gen will not change in 
new versions of the table and only new entries might be added. Also the 
fact that since the table is in the specs we expect the users to know 
what each entry of the table means and we're therefore deprecating 
exposing the entries in the uapi with an enum.
Might also be worth mentioning that the first 3 entries are compatible 
with the legacy i915 entries for previous gen but that this is not 
guaranteed on future gens so userland drivers need to use the ICL 
timeframe to transition.


Lastly, we need a way to query what version of the table the kernel is 
programming in HW.




BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Zhenyu Wang 


CC some mesa people here? not sure who the right contact would be for this


---
  drivers/gpu/drm/i915/intel_mocs.c | 246 +-
  1 file changed, 244 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..b76d6db 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
  #define LE_SCC(value) ((value) << 8)
  #define LE_PFM(value) ((value) << 11)
  #define LE_SCF(value) ((value) << 14)
+#define LE_CoS(value)  ((value) << 15)
+#define LE_SSE(value)  ((value) << 17)
  
  /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */

  #define L3_ESC(value) ((value) << 0)
@@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
   *   may only be updated incrementally by adding entries at the
   *   end.
   */
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+   [0] = {
+ /* Base - Uncached (Deprecated) */
+ .control_value = LE_CACHEABILITY(LE_UC) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+   },
+   [1] = {
+ /* Base - L3 + LeCC:PAT (Deprecated) */
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+   },
+   [2] = {
+ /* Base - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+   },
+   [3] = {
+ /* Base - Uncached */
+ .control_value = LE_CACHEABILITY(LE_UC) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+   },
+   [4] = {
+ /* Base - L3 */
+ .control_value = LE_CACHEABILITY(LE_UC) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+   },
+   [5] = {
+ /* Base - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+   },
+   [6] = {
+ /* Age 0 - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+   },
+   [7] = {
+ /* Age 0 - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+

[Intel-gfx] [PATCH v1] drm/i915/icl: Define MOCS table for Icelake

2018-10-19 Thread Tomasz Lis 
The table has been unified across OSes to minimize virtualization overhead.

The MOCS table is now versioned; the patch includes version 1 entries.

BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis 
Cc: Joonas Lahtinen 
Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Zhenyu Wang 
---
 drivers/gpu/drm/i915/intel_mocs.c | 246 +-
 1 file changed, 244 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..b76d6db 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
 #define LE_SCC(value)  ((value) << 8)
 #define LE_PFM(value)  ((value) << 11)
 #define LE_SCF(value)  ((value) << 14)
+#define LE_CoS(value)  ((value) << 15)
+#define LE_SSE(value)  ((value) << 17)
 
 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
 #define L3_ESC(value)  ((value) << 0)
@@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
  *   may only be updated incrementally by adding entries at the
  *   end.
  */
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+   [0] = {
+ /* Base - Uncached (Deprecated) */
+ .control_value = LE_CACHEABILITY(LE_UC) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+   },
+   [1] = {
+ /* Base - L3 + LeCC:PAT (Deprecated) */
+ .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+   },
+   [2] = {
+ /* Base - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+   },
+   [3] = {
+ /* Base - Uncached */
+ .control_value = LE_CACHEABILITY(LE_UC) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+   },
+   [4] = {
+ /* Base - L3 */
+ .control_value = LE_CACHEABILITY(LE_UC) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+   },
+   [5] = {
+ /* Base - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+   },
+   [6] = {
+ /* Age 0 - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+   },
+   [7] = {
+ /* Age 0 - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+   },
+   [8] = {
+ /* Age: Don't Chg. - LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+  LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+ .l3cc_value =L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+   },
+   [9] = {
+ /* Age: Don't Chg. - L3 + LLC */
+ .control_value = LE_CACHEABILITY(LE_WB) |
+  LE_TGT_CACHE(LE_TC_LLC) |
+  LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) |