Re: [Intel-gfx] [PATCH v10] drm/i915/icl: Gen11 forcewake support

[kbuild test robot]

Hi Daniele,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180202]
[cannot apply to v4.15]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Michel-Thierry/drm-i915-icl-Gen11-forcewake-support/20180204-034751
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-u0-02040445 (attached as .config)
compiler: gcc-5 (Debian 5.5.0-3) 5.4.1 20171010
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 

All errors (new ones prefixed by >>):

   In file included from drivers/gpu//drm/i915/i915_drv.h:56:0,
from drivers/gpu//drm/i915/intel_uncore.c:24:
   drivers/gpu//drm/i915/intel_uncore.c:903:12: error: 'GEN11_BSD_RING_BASE' 
undeclared here (not in a function)
 RING_TAIL(GEN11_BSD_RING_BASE),  /* 0x1C (base) */
   ^
   drivers/gpu//drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu//drm/i915/intel_uncore.c:903:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_BSD_RING_BASE),  /* 0x1C (base) */
 ^
>> drivers/gpu//drm/i915/intel_uncore.c:904:12: error: 'GEN11_BSD2_RING_BASE' 
>> undeclared here (not in a function)
 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
   ^
   drivers/gpu//drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu//drm/i915/intel_uncore.c:904:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
 ^
>> drivers/gpu//drm/i915/intel_uncore.c:905:12: error: 'GEN11_VEBOX_RING_BASE' 
>> undeclared here (not in a function)
 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
   ^
   drivers/gpu//drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu//drm/i915/intel_uncore.c:905:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
 ^
>> drivers/gpu//drm/i915/intel_uncore.c:906:12: error: 'GEN11_BSD3_RING_BASE' 
>> undeclared here (not in a function)
 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D (base) */
   ^
   drivers/gpu//drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu//drm/i915/intel_uncore.c:906:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D (base) */
 ^
>> drivers/gpu//drm/i915/intel_uncore.c:907:12: error: 'GEN11_BSD4_RING_BASE' 
>> undeclared here (not in a function)
 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
   ^
   drivers/gpu//drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu//drm/i915/intel_uncore.c:907:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
 ^
>> drivers/gpu//drm/i915/intel_uncore.c:908:12: error: 'GEN11_VEBOX2_RING_BASE' 
>> undeclared here (not in a function)
 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
   ^
   drivers/gpu//drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu//drm/i915/intel_uncore.c:908:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
 ^
   drivers/gpu//drm/i915/intel_uncore.c: In function 
'intel_uncore_fw_domains_init':
>> drivers/gpu//drm/i915/intel_uncore.c:1382:19: error: 'I915_MAX_VCS' 
>> undeclared (first use in this function)
  for (i = 0; i < I915_MAX_VCS; i++) {
  ^
   drivers/gpu//drm/i915/intel_uncore.c:1382:19: note: each undeclared 
identifier is reported only once for each function it appears in
   drivers/gpu//drm/i915/intel_uncore.c:1382:17: warning: comparison between 
pointer and integer
  for (i = 0; i < I915_MAX_VCS; i++) {
^
>> drivers/gpu//drm/i915/intel_uncore.c:1390:19: error: 'I915_MAX_VECS' 
>> undeclared (first use in this function)
  for (i = 0; i < I915_MAX_VECS; i++) {
  ^
   drivers/gpu//drm/i915/intel_uncore.c:1390:17: warning: comparison between 
pointer and integer
  for (i = 0; i < I915_MAX_VECS; i++) {
^
   In 

Re: [Intel-gfx] [PATCH v10] drm/i915/icl: Gen11 forcewake support

[kbuild test robot]

Hi Daniele,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180202]
[cannot apply to v4.15]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Michel-Thierry/drm-i915-icl-Gen11-forcewake-support/20180204-034751
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x019-201805 (attached as .config)
compiler: gcc-7 (Debian 7.2.0-12) 7.2.1 20171025
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All error/warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/i915_drv.h:56:0,
from drivers/gpu/drm/i915/intel_uncore.c:24:
>> drivers/gpu/drm/i915/intel_uncore.c:903:12: error: 'GEN11_BSD_RING_BASE' 
>> undeclared here (not in a function); did you mean 'GEN6_BSD_RING_BASE'?
 RING_TAIL(GEN11_BSD_RING_BASE),  /* 0x1C (base) */
   ^
   drivers/gpu/drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
>> drivers/gpu/drm/i915/intel_uncore.c:903:2: note: in expansion of macro 
>> 'RING_TAIL'
 RING_TAIL(GEN11_BSD_RING_BASE),  /* 0x1C (base) */
 ^
>> drivers/gpu/drm/i915/intel_uncore.c:904:12: error: 'GEN11_BSD2_RING_BASE' 
>> undeclared here (not in a function); did you mean 'GEN11_BSD_RING_BASE'?
 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
   ^
   drivers/gpu/drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu/drm/i915/intel_uncore.c:904:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
 ^
>> drivers/gpu/drm/i915/intel_uncore.c:905:12: error: 'GEN11_VEBOX_RING_BASE' 
>> undeclared here (not in a function); did you mean 'GEN11_BSD_RING_BASE'?
 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
   ^
   drivers/gpu/drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu/drm/i915/intel_uncore.c:905:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
 ^
>> drivers/gpu/drm/i915/intel_uncore.c:906:12: error: 'GEN11_BSD3_RING_BASE' 
>> undeclared here (not in a function); did you mean 'GEN11_BSD2_RING_BASE'?
 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D (base) */
   ^
   drivers/gpu/drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu/drm/i915/intel_uncore.c:906:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D (base) */
 ^
>> drivers/gpu/drm/i915/intel_uncore.c:907:12: error: 'GEN11_BSD4_RING_BASE' 
>> undeclared here (not in a function); did you mean 'GEN11_BSD3_RING_BASE'?
 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
   ^
   drivers/gpu/drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu/drm/i915/intel_uncore.c:907:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
 ^
>> drivers/gpu/drm/i915/intel_uncore.c:908:12: error: 'GEN11_VEBOX2_RING_BASE' 
>> undeclared here (not in a function); did you mean 'GEN11_VEBOX_RING_BASE'?
 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
   ^
   drivers/gpu/drm/i915/i915_reg.h:123:47: note: in definition of macro '_MMIO'
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  ^
   drivers/gpu/drm/i915/intel_uncore.c:908:2: note: in expansion of macro 
'RING_TAIL'
 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
 ^
   drivers/gpu/drm/i915/intel_uncore.c: In function 
'intel_uncore_fw_domains_init':
>> drivers/gpu/drm/i915/intel_uncore.c:1382:19: error: 'I915_MAX_VCS' 
>> undeclared (first use in this function); did you mean 'I915_MAP_WC'?
  for (i = 0; i < I915_MAX_VCS; i++) {
  ^~~~
  I915_MAP_WC
   drivers/gpu/drm/i915/intel_uncore.c:1382:19: note: each undeclared 
identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/intel_uncore.c:1382:17: warning: comparison between 
>> pointer and integer
  for (i = 0; i < I915_MAX_VCS; i++) {
^
>> 

Re: [Intel-gfx] [PATCH v10] drm/i915/icl: Gen11 forcewake support

[Michel Thierry]

On 2/1/2018 2:25 AM, Tvrtko Ursulin wrote:


On 01/02/2018 00:52, Michel Thierry wrote:

From: Daniele Ceraolo Spurio 

The main difference with previous GENs is that starting from Gen11
each VCS and VECS engine has its own power well, which only exist
if the related engine exists in the HW.
The fallback forcewake request workaround is only needed on gen9
according to the HSDES WA entry (1604254524), so we can go back to using
the simpler fw_domains_get/put functions.

BSpec: 18331

v2: fix fwtable, use array to test shadow tables, create new
 accessors to avoid check on every access (Tvrtko)
v3 (from Paulo): Rebase.
v4:
   - Range 09400-097FF should be FORCEWAKE_ALL (Daniele)
   - Use the BIT macro for forcewake domains (Daniele)
   - Add a comment about the range ordering (Oscar)
   - Updated commit message (Oscar)
v5: Rebased
v6: Use I915_MAX_VCS/VECS (Michal)
v7: translate FORCEWAKE_ALL to available domains
v8: rebase, add clarification on fallback ack in commit message.
v9: fix rebase issue, change check in fw_domains_init from IS_GEN11
 to GEN >= 11
v10: Generate is_genX_shadowed with a macro (Daniele)
  Include gen11_fw_ranges in the selftest (Michel)

Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Acked-by: Michel Thierry 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
Signed-off-by: Michel Thierry 
---

  drivers/gpu/drm/i915/i915_reg.h   |   4 +
  drivers/gpu/drm/i915/intel_uncore.c   | 155 
--

  drivers/gpu/drm/i915/intel_uncore.h   |  27 -
  drivers/gpu/drm/i915/selftests/intel_uncore.c |  31 --
  4 files changed, 193 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h 
b/drivers/gpu/drm/i915/i915_reg.h

index d29e8a0e2ca3..eaca12292ffe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8015,9 +8015,13 @@ enum {
  #define   VLV_GTLC_PW_RENDER_STATUS_MASK    (1 << 7)
  #define  FORCEWAKE_MT    _MMIO(0xa188) /* multi-threaded */
  #define  FORCEWAKE_MEDIA_GEN9    _MMIO(0xa270)
+#define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)    _MMIO(0xa540 + (n) * 4)
+#define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)    _MMIO(0xa560 + (n) * 4)
  #define  FORCEWAKE_RENDER_GEN9    _MMIO(0xa278)
  #define  FORCEWAKE_BLITTER_GEN9    _MMIO(0xa188)
  #define  FORCEWAKE_ACK_MEDIA_GEN9    _MMIO(0x0D88)
+#define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)    _MMIO(0x0D50 + (n) * 4)
+#define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)    _MMIO(0x0D70 + (n) * 4)
  #define  FORCEWAKE_ACK_RENDER_GEN9    _MMIO(0x0D84)
  #define  FORCEWAKE_ACK_BLITTER_GEN9    _MMIO(0x130044)
  #define   FORCEWAKE_KERNEL    BIT(0)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c

index 164dbb8cfa36..c1953043604b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -37,6 +37,12 @@ static const char * const forcewake_domain_names[] = {
  "render",
  "blitter",
  "media",
+    "vdbox0",
+    "vdbox1",
+    "vdbox2",
+    "vdbox3",
+    "vebox0",
+    "vebox1",
  };
  const char *
@@ -773,6 +779,8 @@ void assert_forcewakes_active(struct 
drm_i915_private *dev_priv,

  /* We give fast paths for the really cool registers */
  #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x4)
+#define GEN11_NEEDS_FORCE_WAKE(reg) \
+    ((reg) < 0x4 || ((reg) >= 0x1c && (reg) < 0x1dc000))


Nitpick - I'd perhaps at least have a blank line between the two 
defines, or even moved the GEN11 lower in file, just before the first 
mention of GEN11 specific code starts appearing.




I'd go for a new blank line, it makes it obvious something changed 
between gens.



  #define __gen6_reg_read_fw_domains(offset) \
  ({ \
@@ -826,6 +834,14 @@ find_fw_domain(struct drm_i915_private *dev_priv, 
u32 offset)

  if (!entry)
  return 0;
+    /*
+ * The list of FW domains depends on the SKU in gen11+ so we
+ * can't determine it statically. We use FORCEWAKE_ALL and
+ * translate it here to the list of available domains.
+ */
+    if (entry->domains == FORCEWAKE_ALL)
+    return dev_priv->uncore.fw_domains;
+
  WARN(entry->domains & ~dev_priv->uncore.fw_domains,
   "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
   entry->domains & ~dev_priv->uncore.fw_domains, offset);
@@ -860,6 +876,14 @@ static const struct intel_forcewake_range 
__vlv_fw_ranges[] = {

  __fwd; \
  })
+#define __gen11_fwtable_reg_read_fw_domains(offset) \
+({ \
+    enum forcewake_domains __fwd = 0; \
+    if (GEN11_NEEDS_FORCE_WAKE((offset))) \
+    __fwd = find_fw_domain(dev_priv, offset); \
+    __fwd; \
+})
+
  /* *Must* be sorted 

Re: [Intel-gfx] [PATCH v10] drm/i915/icl: Gen11 forcewake support

[Tvrtko Ursulin]

On 01/02/2018 00:52, Michel Thierry wrote:

From: Daniele Ceraolo Spurio 

The main difference with previous GENs is that starting from Gen11
each VCS and VECS engine has its own power well, which only exist
if the related engine exists in the HW.
The fallback forcewake request workaround is only needed on gen9
according to the HSDES WA entry (1604254524), so we can go back to using
the simpler fw_domains_get/put functions.

BSpec: 18331

v2: fix fwtable, use array to test shadow tables, create new
 accessors to avoid check on every access (Tvrtko)
v3 (from Paulo): Rebase.
v4:
   - Range 09400-097FF should be FORCEWAKE_ALL (Daniele)
   - Use the BIT macro for forcewake domains (Daniele)
   - Add a comment about the range ordering (Oscar)
   - Updated commit message (Oscar)
v5: Rebased
v6: Use I915_MAX_VCS/VECS (Michal)
v7: translate FORCEWAKE_ALL to available domains
v8: rebase, add clarification on fallback ack in commit message.
v9: fix rebase issue, change check in fw_domains_init from IS_GEN11
 to GEN >= 11
v10: Generate is_genX_shadowed with a macro (Daniele)
  Include gen11_fw_ranges in the selftest (Michel)

Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Acked-by: Michel Thierry 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
Signed-off-by: Michel Thierry 
---

  drivers/gpu/drm/i915/i915_reg.h   |   4 +
  drivers/gpu/drm/i915/intel_uncore.c   | 155 --
  drivers/gpu/drm/i915/intel_uncore.h   |  27 -
  drivers/gpu/drm/i915/selftests/intel_uncore.c |  31 --
  4 files changed, 193 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d29e8a0e2ca3..eaca12292ffe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8015,9 +8015,13 @@ enum {
  #define   VLV_GTLC_PW_RENDER_STATUS_MASK  (1 << 7)
  #define  FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded 
*/
  #define  FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
+#define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)_MMIO(0xa540 + (n) * 4)
+#define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)_MMIO(0xa560 + (n) * 4)
  #define  FORCEWAKE_RENDER_GEN9_MMIO(0xa278)
  #define  FORCEWAKE_BLITTER_GEN9   _MMIO(0xa188)
  #define  FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
+#define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)_MMIO(0x0D50 + (n) * 4)
+#define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)_MMIO(0x0D70 + (n) * 4)
  #define  FORCEWAKE_ACK_RENDER_GEN9_MMIO(0x0D84)
  #define  FORCEWAKE_ACK_BLITTER_GEN9   _MMIO(0x130044)
  #define   FORCEWAKE_KERNELBIT(0)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 164dbb8cfa36..c1953043604b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -37,6 +37,12 @@ static const char * const forcewake_domain_names[] = {
"render",
"blitter",
"media",
+   "vdbox0",
+   "vdbox1",
+   "vdbox2",
+   "vdbox3",
+   "vebox0",
+   "vebox1",
  };
  
  const char *

@@ -773,6 +779,8 @@ void assert_forcewakes_active(struct drm_i915_private 
*dev_priv,
  
  /* We give fast paths for the really cool registers */

  #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x4)
+#define GEN11_NEEDS_FORCE_WAKE(reg) \
+   ((reg) < 0x4 || ((reg) >= 0x1c && (reg) < 0x1dc000))


Nitpick - I'd perhaps at least have a blank line between the two 
defines, or even moved the GEN11 lower in file, just before the first 
mention of GEN11 specific code starts appearing.


  
  #define __gen6_reg_read_fw_domains(offset) \

  ({ \
@@ -826,6 +834,14 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 
offset)
if (!entry)
return 0;
  
+	/*

+* The list of FW domains depends on the SKU in gen11+ so we
+* can't determine it statically. We use FORCEWAKE_ALL and
+* translate it here to the list of available domains.
+*/
+   if (entry->domains == FORCEWAKE_ALL)
+   return dev_priv->uncore.fw_domains;
+
WARN(entry->domains & ~dev_priv->uncore.fw_domains,
 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 entry->domains & ~dev_priv->uncore.fw_domains, offset);
@@ -860,6 +876,14 @@ static const struct intel_forcewake_range 
__vlv_fw_ranges[] = {
__fwd; \
  })
  
+#define __gen11_fwtable_reg_read_fw_domains(offset) \

+({ \
+   enum forcewake_domains __fwd = 0; \
+   if (GEN11_NEEDS_FORCE_WAKE((offset))) \
+   __fwd = find_fw_domain(dev_priv, offset); \
+   

[Intel-gfx] [PATCH v10] drm/i915/icl: Gen11 forcewake support

[Michel Thierry]

From: Daniele Ceraolo Spurio 

The main difference with previous GENs is that starting from Gen11
each VCS and VECS engine has its own power well, which only exist
if the related engine exists in the HW.
The fallback forcewake request workaround is only needed on gen9
according to the HSDES WA entry (1604254524), so we can go back to using
the simpler fw_domains_get/put functions.

BSpec: 18331

v2: fix fwtable, use array to test shadow tables, create new
accessors to avoid check on every access (Tvrtko)
v3 (from Paulo): Rebase.
v4:
  - Range 09400-097FF should be FORCEWAKE_ALL (Daniele)
  - Use the BIT macro for forcewake domains (Daniele)
  - Add a comment about the range ordering (Oscar)
  - Updated commit message (Oscar)
v5: Rebased
v6: Use I915_MAX_VCS/VECS (Michal)
v7: translate FORCEWAKE_ALL to available domains
v8: rebase, add clarification on fallback ack in commit message.
v9: fix rebase issue, change check in fw_domains_init from IS_GEN11
to GEN >= 11
v10: Generate is_genX_shadowed with a macro (Daniele)
 Include gen11_fw_ranges in the selftest (Michel)

Cc: Michal Wajdeczko 
Cc: Tvrtko Ursulin 
Cc: Paulo Zanoni 
Acked-by: Michel Thierry 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
Signed-off-by: Michel Thierry 
---

 drivers/gpu/drm/i915/i915_reg.h   |   4 +
 drivers/gpu/drm/i915/intel_uncore.c   | 155 --
 drivers/gpu/drm/i915/intel_uncore.h   |  27 -
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  31 --
 4 files changed, 193 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d29e8a0e2ca3..eaca12292ffe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8015,9 +8015,13 @@ enum {
 #define   VLV_GTLC_PW_RENDER_STATUS_MASK   (1 << 7)
 #define  FORCEWAKE_MT  _MMIO(0xa188) /* multi-threaded 
*/
 #define  FORCEWAKE_MEDIA_GEN9  _MMIO(0xa270)
+#define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)_MMIO(0xa540 + (n) * 4)
+#define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)_MMIO(0xa560 + (n) * 4)
 #define  FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
 #define  FORCEWAKE_BLITTER_GEN9_MMIO(0xa188)
 #define  FORCEWAKE_ACK_MEDIA_GEN9  _MMIO(0x0D88)
+#define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)_MMIO(0x0D50 + (n) * 4)
+#define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)_MMIO(0x0D70 + (n) * 4)
 #define  FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
 #define  FORCEWAKE_ACK_BLITTER_GEN9_MMIO(0x130044)
 #define   FORCEWAKE_KERNEL BIT(0)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 164dbb8cfa36..c1953043604b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -37,6 +37,12 @@ static const char * const forcewake_domain_names[] = {
"render",
"blitter",
"media",
+   "vdbox0",
+   "vdbox1",
+   "vdbox2",
+   "vdbox3",
+   "vebox0",
+   "vebox1",
 };
 
 const char *
@@ -773,6 +779,8 @@ void assert_forcewakes_active(struct drm_i915_private 
*dev_priv,
 
 /* We give fast paths for the really cool registers */
 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x4)
+#define GEN11_NEEDS_FORCE_WAKE(reg) \
+   ((reg) < 0x4 || ((reg) >= 0x1c && (reg) < 0x1dc000))
 
 #define __gen6_reg_read_fw_domains(offset) \
 ({ \
@@ -826,6 +834,14 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 
offset)
if (!entry)
return 0;
 
+   /*
+* The list of FW domains depends on the SKU in gen11+ so we
+* can't determine it statically. We use FORCEWAKE_ALL and
+* translate it here to the list of available domains.
+*/
+   if (entry->domains == FORCEWAKE_ALL)
+   return dev_priv->uncore.fw_domains;
+
WARN(entry->domains & ~dev_priv->uncore.fw_domains,
 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 entry->domains & ~dev_priv->uncore.fw_domains, offset);
@@ -860,6 +876,14 @@ static const struct intel_forcewake_range 
__vlv_fw_ranges[] = {
__fwd; \
 })
 
+#define __gen11_fwtable_reg_read_fw_domains(offset) \
+({ \
+   enum forcewake_domains __fwd = 0; \
+   if (GEN11_NEEDS_FORCE_WAKE((offset))) \
+   __fwd = find_fw_domain(dev_priv, offset); \
+   __fwd; \
+})
+
 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 static const i915_reg_t gen8_shadowed_regs[] = {
RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
@@ -871,6 +895,20 @@ static const i915_reg_t gen8_shadowed_regs[] = {