[Intel-gfx] [PATCH v10 0/3] Apply Wa_16018031267 / Wa_16018063123

2023-09-19 Thread Jonathan Cavitt
Apply Wa_16018031267 / Wa_16018063123.  This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.

v2:
- Rename old platform check in second patch to match
  declaration in first patch.
- Refactor second patch name to match first patch.

v3:
- Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h.
- Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more
  streamlined to use.
- Stop dividing PAGE_SIZE by sizeof(u32) when computing
  ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
- Reduce comment complexity.
- Fix several checkpatch warnings.

v4:
- Actually stop dividing PAGE_SIZE by sizeof(u32) when
  computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.

v5:
- Stop dividing PAGE_SIZE by sizeof(u32) in
  check_ring_start during lrc live selftest.

v6:
- Append MI_BATCH_BUFFER_END to end of all PER_CTX_BB
  command streams.
- No longer skip on empty, as command stream will never
  be empty (always contains at least MI_BATCH_BUFFER_END).
- No longer append MI_NOOP until cachline aligned (was a
  fragment from INDIRECT_CTX setup).

v7:
- Use 0x6b instead of 0 for color to maintain functionality.

v8:
- Revert v7.
- Add some reserved kernel space per vm to run the
  workaround on.

v9:
- Hide reserved kernel space per vm from userspace.

v10:
- Revert v7 properly.
- Test on updated IGT.

Test-with: 20230919170230.3307408-1-jonathan.cav...@intel.com

Signed-off-by: Nirmoy Das 
Signed-off-by: Jonathan Cavitt 
CC: Joonas Lahtinen 
CC: Rodrigo Vivi 
CC: Tomasz Mistat 
CC: Gregory F Germano 
CC: Matt Roper 
CC: James Ausmus 
CC: Chris Wilson 
CC: Andi Shyti 

Jonathan Cavitt (3):
  drm/i915: Reserve some kernel space per vm
  drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
  drm/i915: Set copy engine arbitration for Wa_16018031267 /
Wa_16018063123

 drivers/gpu/drm/i915/gt/gen8_ppgtt.c|   7 ++
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h  |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h|   2 +
 drivers/gpu/drm/i915/gt/intel_gtt.h |   1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c | 100 +++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   5 +
 drivers/gpu/drm/i915/gt/selftest_lrc.c  |  65 +
 8 files changed, 169 insertions(+), 21 deletions(-)

-- 
2.25.1



[Intel-gfx] [PATCH v10 0/3] Apply Wa_16018031267 / Wa_16018063123

2023-09-14 Thread Jonathan Cavitt
Apply Wa_16018031267 / Wa_16018063123.  This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.

v2:
- Rename old platform check in second patch to match
  declaration in first patch.
- Refactor second patch name to match first patch.

v3:
- Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h.
- Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more
  streamlined to use.
- Stop dividing PAGE_SIZE by sizeof(u32) when computing
  ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
- Reduce comment complexity.
- Fix several checkpatch warnings.

v4:
- Actually stop dividing PAGE_SIZE by sizeof(u32) when
  computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.

v5:
- Stop dividing PAGE_SIZE by sizeof(u32) in
  check_ring_start during lrc live selftest.

v6:
- Append MI_BATCH_BUFFER_END to end of all PER_CTX_BB
  command streams.
- No longer skip on empty, as command stream will never
  be empty (always contains at least MI_BATCH_BUFFER_END).
- No longer append MI_NOOP until cachline aligned (was a
  fragment from INDIRECT_CTX setup).

v7:
- Use 0x6b instead of 0 for color to maintain functionality.

v8:
- Revert v7.
- Add some reserved kernel space per vm to run the
  workaround on.

v9:
- Hide reserved kernel space per vm from userspace.

v10:
- Revert v7 properly.
- Test on updated IGT.

Test-with: 20230914172332.2322524-2-jonathan.cav...@intel.com

Signed-off-by: Nirmoy Das 
Signed-off-by: Jonathan Cavitt 
CC: Joonas Lahtinen 
CC: Rodrigo Vivi 
CC: Tomasz Mistat 
CC: Gregory F Germano 
CC: Matt Roper 
CC: James Ausmus 
CC: Chris Wilson 
CC: Andi Shyti 

Jonathan Cavitt (3):
  drm/i915: Reserve some kernel space per vm
  drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
  drm/i915: Set copy engine arbitration for Wa_16018031267 /
Wa_16018063123

 drivers/gpu/drm/i915/gt/gen8_ppgtt.c|   7 ++
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h  |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h|   2 +
 drivers/gpu/drm/i915/gt/intel_gtt.h |   1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c | 100 +++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   5 +
 drivers/gpu/drm/i915/gt/selftest_lrc.c  |  65 +
 8 files changed, 169 insertions(+), 21 deletions(-)

-- 
2.25.1