Re: [Intel-gfx] [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-15 Thread Deepak S 



On Wednesday 15 April 2015 04:48 PM, Ville Syrjälä wrote:

On Wed, Apr 15, 2015 at 02:16:18PM +0530, deepa...@linux.intel.com wrote:

From: Deepak S deepa...@linux.intel.com

This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

Signed-off-by: Deepak S deepa...@linux.intel.com
---
  drivers/gpu/drm/i915/i915_reg.h | 2 ++
  drivers/gpu/drm/i915/intel_pm.c | 5 +
  2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
  #define  GTFIFOCTL0x120008
  #defineGT_FIFO_FREE_ENTRIES_MASK  0x7f
  #defineGT_FIFO_NUM_RESERVED_ENTRIES   20
+#define   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1  12)
+#define   GT_FIFO_CTL_RC6_POLICY_STALL (1  11)
  
  #define  HSW_IDICR0x9008

  #defineIDIHASHMSK(x)  (((x)  0x3f)  16)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4dd8b41..2b86915 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct 
drm_device *dev)
/* WaDisableSDEUnitClockGating:chv */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+   /* WaDisableShadowRegForCpd */
+   I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+ 
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+ GT_FIFO_CTL_RC6_POLICY_STALL);

uncore early sanitize would still seem like the better place for this.


you mean intel_uncore_early_sanitize(). But func is called during early resume 
right?
Since  GTFIFOCTL will be saved and resorted by gunit. I think programming reg in
cherryview_init_clock_gating should be good enough?


  }
  
  static void g4x_init_clock_gating(struct drm_device *dev)

--
1.9.1


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Re: [Intel-gfx] [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-15 Thread shuang . he 
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 6196
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  276/276  276/276
ILK  302/302  302/302
SNB  318/318  318/318
IVB  341/341  341/341
BYT  287/287  287/287
HSW -1  395/395  394/395
BDW  318/318  318/318
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*HSW  igt@gem_pwrite_pread@snooped-copy-performance  PASS(2)  
DMESG_WARN(1)PASS(1)
(dmesg patch 
applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck
 timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
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[Intel-gfx] [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-15 Thread deepak . s 
From: Deepak S deepa...@linux.intel.com

This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

Signed-off-by: Deepak S deepa...@linux.intel.com
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 5 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL 0x120008
 #defineGT_FIFO_FREE_ENTRIES_MASK   0x7f
 #defineGT_FIFO_NUM_RESERVED_ENTRIES20
+#define   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1  12)
+#define   GT_FIFO_CTL_RC6_POLICY_STALL (1  11)
 
 #define  HSW_IDICR 0x9008
 #defineIDIHASHMSK(x)   (((x)  0x3f)  16)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4dd8b41..2b86915 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct 
drm_device *dev)
/* WaDisableSDEUnitClockGating:chv */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+   /* WaDisableShadowRegForCpd */
+   I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+ 
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+ GT_FIFO_CTL_RC6_POLICY_STALL);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.9.1

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Re: [Intel-gfx] [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-15 Thread Ville Syrjälä 
On Wed, Apr 15, 2015 at 02:16:18PM +0530, deepa...@linux.intel.com wrote:
 From: Deepak S deepa...@linux.intel.com
 
 This WA is avoid problem between shadow vs wake FIFO unload
 problem during CPD/RC6 transactions on CHV.
 
 v2: Define individual bits GTFIFOCTL (Ville)
 
 Signed-off-by: Deepak S deepa...@linux.intel.com
 ---
  drivers/gpu/drm/i915/i915_reg.h | 2 ++
  drivers/gpu/drm/i915/intel_pm.c | 5 +
  2 files changed, 7 insertions(+)
 
 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
 index 9c97842..a642a58 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
  #define  GTFIFOCTL   0x120008
  #defineGT_FIFO_FREE_ENTRIES_MASK 0x7f
  #defineGT_FIFO_NUM_RESERVED_ENTRIES  20
 +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1  12)
 +#define GT_FIFO_CTL_RC6_POLICY_STALL (1  11)
  
  #define  HSW_IDICR   0x9008
  #defineIDIHASHMSK(x) (((x)  0x3f)  16)
 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
 index 4dd8b41..2b86915 100644
 --- a/drivers/gpu/drm/i915/intel_pm.c
 +++ b/drivers/gpu/drm/i915/intel_pm.c
 @@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct 
 drm_device *dev)
   /* WaDisableSDEUnitClockGating:chv */
   I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 +
 + /* WaDisableShadowRegForCpd */
 + I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
 +   
 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 +   GT_FIFO_CTL_RC6_POLICY_STALL);

uncore early sanitize would still seem like the better place for this.

  }
  
  static void g4x_init_clock_gating(struct drm_device *dev)
 -- 
 1.9.1

-- 
Ville Syrjälä
Intel OTC
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