Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add Wa_1509727124
On Wed, Aug 24, 2022 at 02:26:38PM +0300, Joonas Lahtinen wrote: > Quoting Matt Roper (2022-08-02 18:09:16) > > On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote: > > > Bspec: 46052 > > > Reviewed-by: Matt Roper > > > Signed-off-by: Harish Chegondi > > > > Applied to drm-intel-gt-next. Thanks for the patch. > > This patch is completely lacking the commit message. > > That is unacceptable, please make sure there is a proper commit message > for any merged patches going forward. > > Please do explain the patch rationale in this mail thread so it at least > becomes available from the Link: that gets added by DIM when this was > committed. > > Regards, Joonas There isn't really too much to say on this one. For the record, the justification is that we're implementing Wa_1509727124 from the workaround database which simply tells us that we need to program 0xE18C[9] to 1; this patch is just following that guidance from the spec. There's no further information available beyond that. Going forward we'll make sure we put some kind of statement in the commit message body to make it clear that the workaround number and register/bit setting are the only information we have and that this isn't an oversight. Thanks. Matt -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add Wa_1509727124
Quoting Matt Roper (2022-08-02 18:09:16) > On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote: > > Bspec: 46052 > > Reviewed-by: Matt Roper > > Signed-off-by: Harish Chegondi > > Applied to drm-intel-gt-next. Thanks for the patch. This patch is completely lacking the commit message. That is unacceptable, please make sure there is a proper commit message for any merged patches going forward. Please do explain the patch rationale in this mail thread so it at least becomes available from the Link: that gets added by DIM when this was committed. Regards, Joonas
Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add Wa_1509727124
On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote:
> Bspec: 46052
> Reviewed-by: Matt Roper
> Signed-off-by: Harish Chegondi
Applied to drm-intel-gt-next. Thanks for the patch.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 60d6eb5f245b..b3b49f6d6d1c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1078,6 +1078,7 @@
>
> #define GEN10_SAMPLER_MODE _MMIO(0xe18c)
> #define ENABLE_SMALLPL REG_BIT(15)
> +#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>
> #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e8111fce56d0..59cf28baa472 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2119,6 +2119,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> }
>
> + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> + IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> + /* Wa_1509727124:dg2 */
> + wa_masked_en(wal, GEN10_SAMPLER_MODE,
> + SC_DISABLE_POWER_OPTIMIZATION_EBB);
> + }
> +
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> /* Wa_14012419201:dg2 */
> --
> 2.37.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
[Intel-gfx] [PATCH v2] drm/i915/dg2: Add Wa_1509727124
Bspec: 46052
Reviewed-by: Matt Roper
Signed-off-by: Harish Chegondi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 60d6eb5f245b..b3b49f6d6d1c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1078,6 +1078,7 @@
#define GEN10_SAMPLER_MODE _MMIO(0xe18c)
#define ENABLE_SMALLPL REG_BIT(15)
+#define SC_DISABLE_POWER_OPTIMIZATION_EBBREG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSGREG_BIT(5)
#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e8111fce56d0..59cf28baa472 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2119,6 +2119,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
}
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2 */
+ wa_masked_en(wal, GEN10_SAMPLER_MODE,
+SC_DISABLE_POWER_OPTIMIZATION_EBB);
+ }
+
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012419201:dg2 */
--
2.37.1
