Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init

2017-08-09 Thread Rodrigo Vivi 
merged to dinq.

Thanks for the patch and reviews

On Wed, Aug 9, 2017 at 10:37 AM, Rodrigo Vivi  wrote:
> Reviewed-by: Rodrigo Vivi 
>
> On Tue, Aug 8, 2017 at 2:51 PM, Jim Bride  wrote:
>> Bit 29 of SRD_CTL needs to have its value preserved according to the
>> B-Spec, so right before we write out the register we go ahead and read
>> the register and preserve the value of that bit before we write out
>> the configured register value.
>>
>> v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)
>>
>> Cc: Rodrigo Vivi 
>> Cc: Chris Wilson 
>> Cc: Jani Nikula 
>> Signed-off-by: Jim Bride 
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h  | 1 +
>>  drivers/gpu/drm/i915/intel_psr.c | 1 +
>>  2 files changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index b2546ad..56df86e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3872,6 +3872,7 @@ enum {
>>  #define EDP_PSR_CTL
>> _MMIO(dev_priv->psr_mmio_base + 0)
>>  #define   EDP_PSR_ENABLE   (1<<31)
>>  #define   BDW_PSR_SINGLE_FRAME (1<<30)
>> +#define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK  (1<<29) /* SW can't modify */
>>  #define   EDP_PSR_LINK_STANDBY (1<<27)
>>  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
>>  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES  (0<<25)
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index 559f1ab..1b31ab0 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
>> *intel_dp)
>> else
>> val |= EDP_PSR_TP1_TP2_SEL;
>>
>> +   val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
>> I915_WRITE(EDP_PSR_CTL, val);
>>  }
>>
>> --
>> 2.7.4
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br



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Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init

2017-08-09 Thread Rodrigo Vivi 
Reviewed-by: Rodrigo Vivi 

On Tue, Aug 8, 2017 at 2:51 PM, Jim Bride  wrote:
> Bit 29 of SRD_CTL needs to have its value preserved according to the
> B-Spec, so right before we write out the register we go ahead and read
> the register and preserve the value of that bit before we write out
> the configured register value.
>
> v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)
>
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Cc: Jani Nikula 
> Signed-off-by: Jim Bride 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 1 +
>  drivers/gpu/drm/i915/intel_psr.c | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b2546ad..56df86e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3872,6 +3872,7 @@ enum {
>  #define EDP_PSR_CTL_MMIO(dev_priv->psr_mmio_base 
> + 0)
>  #define   EDP_PSR_ENABLE   (1<<31)
>  #define   BDW_PSR_SINGLE_FRAME (1<<30)
> +#define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK  (1<<29) /* SW can't modify */
>  #define   EDP_PSR_LINK_STANDBY (1<<27)
>  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
>  #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES  (0<<25)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 559f1ab..1b31ab0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
> *intel_dp)
> else
> val |= EDP_PSR_TP1_TP2_SEL;
>
> +   val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
> I915_WRITE(EDP_PSR_CTL, val);
>  }
>
> --
> 2.7.4
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



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[Intel-gfx] [PATCH v2] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init

2017-08-08 Thread Jim Bride 
Bit 29 of SRD_CTL needs to have its value preserved according to the
B-Spec, so right before we write out the register we go ahead and read
the register and preserve the value of that bit before we write out
the configured register value.

v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)

Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Cc: Jani Nikula 
Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_psr.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b2546ad..56df86e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3872,6 +3872,7 @@ enum {
 #define EDP_PSR_CTL_MMIO(dev_priv->psr_mmio_base + 
0)
 #define   EDP_PSR_ENABLE   (1<<31)
 #define   BDW_PSR_SINGLE_FRAME (1<<30)
+#define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK  (1<<29) /* SW can't modify */
 #define   EDP_PSR_LINK_STANDBY (1<<27)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES  (0<<25)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..1b31ab0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp 
*intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
 
+   val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
I915_WRITE(EDP_PSR_CTL, val);
 }
 
-- 
2.7.4

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