Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source()

2018-10-19 Thread Dhinakaran Pandiyan 
On Wednesday, October 10, 2018 5:41:19 PM PDT José Roberto de Souza wrote:
> Both functions have the same code to disable PSR, so let's reuse that
> code instead of duplicate.
> 
> Suggested-by: Dhinakaran Pandiyan 
> Cc: Dhinakaran Pandiyan 
Reviewed-by: Dhinakaran Pandiyan 

> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 50 ++--
>  1 file changed, 21 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c index 423cdf84059c..f698b3f45c6d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -657,6 +657,25 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>   mutex_unlock(&dev_priv->psr.lock);
>  }
> 
> +static void intel_psr_exit(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + if (!dev_priv->psr.active)
> + return;
> +
> + if (dev_priv->psr.psr2_enabled) {
> + val = I915_READ(EDP_PSR2_CTL);
> + WARN_ON(!(val & EDP_PSR2_ENABLE));
> + I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
> + } else {
> + val = I915_READ(EDP_PSR_CTL);
> + WARN_ON(!(val & EDP_PSR_ENABLE));
> + I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
> + }
> + dev_priv->psr.active = false;
> +}
> +
>  static void
>  intel_psr_disable_source(struct intel_dp *intel_dp)
>  {
> @@ -666,20 +685,14 @@ intel_psr_disable_source(struct intel_dp *intel_dp)
>   i915_reg_t psr_status;
>   u32 psr_status_mask;
> 
> + intel_psr_exit(dev_priv);
> +
>   if (dev_priv->psr.psr2_enabled) {
>   psr_status = EDP_PSR2_STATUS;
>   psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> -
> - I915_WRITE(EDP_PSR2_CTL,
> -I915_READ(EDP_PSR2_CTL) &
> -~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
> -
>   } else {
>   psr_status = EDP_PSR_STATUS;
>   psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
> -
> - I915_WRITE(EDP_PSR_CTL,
> -I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
>   }
> 
>   /* Wait till PSR is idle */
> @@ -687,8 +700,6 @@ intel_psr_disable_source(struct intel_dp *intel_dp)
>   psr_status, psr_status_mask, 0,
>   2000))
>   DRM_ERROR("Timed out waiting for PSR Idle State\n");
> -
> - dev_priv->psr.active = false;
>   } else {
>   if (dev_priv->psr.psr2_enabled)
>   WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
> @@ -926,25 +937,6 @@ static void intel_psr_work(struct work_struct *work)
>   mutex_unlock(&dev_priv->psr.lock);
>  }
> 
> -static void intel_psr_exit(struct drm_i915_private *dev_priv)
> -{
> - u32 val;
> -
> - if (!dev_priv->psr.active)
> - return;
> -
> - if (dev_priv->psr.psr2_enabled) {
> - val = I915_READ(EDP_PSR2_CTL);
> - WARN_ON(!(val & EDP_PSR2_ENABLE));
> - I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
> - } else {
> - val = I915_READ(EDP_PSR_CTL);
> - WARN_ON(!(val & EDP_PSR_ENABLE));
> - I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
> - }
> - dev_priv->psr.active = false;
> -}
> -
>  /**
>   * intel_psr_invalidate - Invalidade PSR
>   * @dev_priv: i915 device




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[Intel-gfx] [PATCH v2 1/6] drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source()

2018-10-10 Thread José Roberto de Souza 
Both functions have the same code to disable PSR, so let's reuse that
code instead of duplicate.

Suggested-by: Dhinakaran Pandiyan 
Cc: Dhinakaran Pandiyan 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/intel_psr.c | 50 ++--
 1 file changed, 21 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 423cdf84059c..f698b3f45c6d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -657,6 +657,25 @@ void intel_psr_enable(struct intel_dp *intel_dp,
mutex_unlock(&dev_priv->psr.lock);
 }
 
+static void intel_psr_exit(struct drm_i915_private *dev_priv)
+{
+   u32 val;
+
+   if (!dev_priv->psr.active)
+   return;
+
+   if (dev_priv->psr.psr2_enabled) {
+   val = I915_READ(EDP_PSR2_CTL);
+   WARN_ON(!(val & EDP_PSR2_ENABLE));
+   I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
+   } else {
+   val = I915_READ(EDP_PSR_CTL);
+   WARN_ON(!(val & EDP_PSR_ENABLE));
+   I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
+   }
+   dev_priv->psr.active = false;
+}
+
 static void
 intel_psr_disable_source(struct intel_dp *intel_dp)
 {
@@ -666,20 +685,14 @@ intel_psr_disable_source(struct intel_dp *intel_dp)
i915_reg_t psr_status;
u32 psr_status_mask;
 
+   intel_psr_exit(dev_priv);
+
if (dev_priv->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS;
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
-
-   I915_WRITE(EDP_PSR2_CTL,
-  I915_READ(EDP_PSR2_CTL) &
-  ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
-
} else {
psr_status = EDP_PSR_STATUS;
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
-
-   I915_WRITE(EDP_PSR_CTL,
-  I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
}
 
/* Wait till PSR is idle */
@@ -687,8 +700,6 @@ intel_psr_disable_source(struct intel_dp *intel_dp)
psr_status, psr_status_mask, 0,
2000))
DRM_ERROR("Timed out waiting for PSR Idle State\n");
-
-   dev_priv->psr.active = false;
} else {
if (dev_priv->psr.psr2_enabled)
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
@@ -926,25 +937,6 @@ static void intel_psr_work(struct work_struct *work)
mutex_unlock(&dev_priv->psr.lock);
 }
 
-static void intel_psr_exit(struct drm_i915_private *dev_priv)
-{
-   u32 val;
-
-   if (!dev_priv->psr.active)
-   return;
-
-   if (dev_priv->psr.psr2_enabled) {
-   val = I915_READ(EDP_PSR2_CTL);
-   WARN_ON(!(val & EDP_PSR2_ENABLE));
-   I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
-   } else {
-   val = I915_READ(EDP_PSR_CTL);
-   WARN_ON(!(val & EDP_PSR_ENABLE));
-   I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
-   }
-   dev_priv->psr.active = false;
-}
-
 /**
  * intel_psr_invalidate - Invalidade PSR
  * @dev_priv: i915 device
-- 
2.19.1

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