Re: [Intel-gfx] [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color

[Sripada, Radhakrishna]

HI,

> -Original Message-
> From: Pandiyan, Dhinakaran
> Sent: Friday, October 4, 2019 5:08 PM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Cc: Syrjala, Ville ; Sharma, Shashank
> ; Antognolli, Rafael
> ; Roper, Matthew D
> ; Chery, Nanley G
> ; Ville Syrjala ;
> Kondapally, Kalyan 
> Subject: Re: [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel
> Gen 12 render compression with Clear Color
> 
> On Mon, 2019-09-23 at 17:03 -0700, Radhakrishna Sripada wrote:
> > Gen12 display can decompress surfaces compressed by render engine with
> > Clear Color, add a new modifier as the driver needs to know the surface
> was compressed by render engine.
> >
> > V2: Description changes as suggested by Rafael.
> >
> > Cc: Ville Syrjala 
> > Cc: Dhinakaran Pandiyan 
> > Cc: Kalyan Kondapally 
> > Cc: Rafael Antognolli 
> > Cc: Nanley Chery 
> > Signed-off-by: Radhakrishna Sripada 
> > ---
> >  include/uapi/drm/drm_fourcc.h | 11 +++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/include/uapi/drm/drm_fourcc.h
> > b/include/uapi/drm/drm_fourcc.h index c4a4e0fdbee5..99c61ee9b61f
> > 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -434,6 +434,17 @@ extern "C" {
> >   */
> >  #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL,
> > 7)
> >
> > +/*
> > + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render
> compression.
> > + *
> > + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC
> > +is linear
> > + * and at index 1.
> 
> Clear color data is fixed size - 64b, that should be in the documentation 
> here.
Sure will update the documentation in next rev.

Thanks,
Radhakrishna(RK) Sripada
> 
> 
> > The clear color is stored at index 2, and the pitch should
> > + * be ignored. A CCS_CC cache line corresponds to an area of 4x1
> > + tiles in the
> That's a CCS cache line, not a CCS_CC cache line, right?
> 
> > + * main surface. The main surface pitch is required to be a multiple
> > +of 4 tile
> > + * widths.
> > + */
> > +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > +fourcc_mod_code(INTEL, 8)
> > +
> >  /*
> >   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> >   *

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Re: [Intel-gfx] [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color

[Dhinakaran Pandiyan]

On Mon, 2019-09-23 at 17:03 -0700, Radhakrishna Sripada wrote:
> Gen12 display can decompress surfaces compressed by render engine with Clear 
> Color, add
> a new modifier as the driver needs to know the surface was compressed by 
> render engine.
> 
> V2: Description changes as suggested by Rafael.
> 
> Cc: Ville Syrjala 
> Cc: Dhinakaran Pandiyan 
> Cc: Kalyan Kondapally 
> Cc: Rafael Antognolli 
> Cc: Nanley Chery 
> Signed-off-by: Radhakrishna Sripada 
> ---
>  include/uapi/drm/drm_fourcc.h | 11 +++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index c4a4e0fdbee5..99c61ee9b61f 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,17 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>  
> +/*
> + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render 
> compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is 
> linear
> + * and at index 1. 

Clear color data is fixed size - 64b, that should be in the documentation here.


> The clear color is stored at index 2, and the pitch should
> + * be ignored. A CCS_CC cache line corresponds to an area of 4x1 tiles in the
That's a CCS cache line, not a CCS_CC cache line, right?

> + * main surface. The main surface pitch is required to be a multiple of 4 
> tile
> + * widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *

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[Intel-gfx] [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color

[Radhakrishna Sripada]

Gen12 display can decompress surfaces compressed by render engine with Clear 
Color, add
a new modifier as the driver needs to know the surface was compressed by render 
engine.

V2: Description changes as suggested by Rafael.

Cc: Ville Syrjala 
Cc: Dhinakaran Pandiyan 
Cc: Kalyan Kondapally 
Cc: Rafael Antognolli 
Cc: Nanley Chery 
Signed-off-by: Radhakrishna Sripada 
---
 include/uapi/drm/drm_fourcc.h | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index c4a4e0fdbee5..99c61ee9b61f 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,17 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
 
+/*
+ * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render 
compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. A CCS_CC cache line corresponds to an area of 4x1 tiles in the
+ * main surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.20.1

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