Re: [Intel-gfx] [PATCH v2 14/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color
On 2021-10-25 at 14:20:02 +0300, Juha-Pekka Heikkila wrote: > On 21.10.2021 17.35, Ville Syrjälä wrote: > > On Thu, Oct 21, 2021 at 07:56:24PM +0530, Ramalingam C wrote: > > > From: Matt Roper > > > > > > DG2 unifies render compression and media compression into a single > > > format for the first time. The programming and buffer layout is > > > supposed to match compression on older gen12 platforms, but the > > > actual compression algorithm is different from any previous platform; as > > > such, we need a new framebuffer modifier to represent buffers in this > > > format, but otherwise we can re-use the existing gen12 compression driver > > > logic. > > > > > > DG2 clear color render compression uses Tile4 layout. Therefore, we need > > > to define a new format modifier for uAPI to support clear color rendering. > > > > > > Signed-off-by: Matt Roper > > > Signed-off-by: Mika Kahola (v2) > > > Signed-off-by: Juha-Pekka Heikkilä > > > Signed-off-by: Ramalingam C > > > cc: Simon Ser > > > Cc: Pekka Paalanen > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 3 ++ > > > .../drm/i915/display/intel_display_types.h| 10 +++- > > > drivers/gpu/drm/i915/display/intel_fb.c | 7 +++ > > > .../drm/i915/display/skl_universal_plane.c| 49 +-- > > > include/uapi/drm/drm_fourcc.h | 30 > > > 5 files changed, 94 insertions(+), 5 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > index 9b678839bf2b..2949fe9f5b9f 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -1013,6 +1013,9 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 > > > *cmd) > > > cmd->pixel_format); > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > > > + case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS: > > > + case I915_FORMAT_MOD_F_TILED_DG2_MC_CCS: > > > + case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC: > > > return lookup_format_info(gen12_ccs_formats, > > > ARRAY_SIZE(gen12_ccs_formats), > > > cmd->pixel_format); > > > > That seems not right. Flat CCS is invisible to the user so the format > > info should not include a CCS plane. > > > > I had cleaned out those rc and mc ccs from here long time ago, I wonder > where did they come back from? On my development tree they're not there. > Also I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC is here in totally wrong place, > it should have its own gen12_flat_ccs_cc_formats table. Oops, there was another piece missed from this upstreaming effort. I will push that too... Ram > > /Juha-Pekka
Re: [Intel-gfx] [PATCH v2 14/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color
On 21.10.2021 17.35, Ville Syrjälä wrote: On Thu, Oct 21, 2021 at 07:56:24PM +0530, Ramalingam C wrote: From: Matt Roper DG2 unifies render compression and media compression into a single format for the first time. The programming and buffer layout is supposed to match compression on older gen12 platforms, but the actual compression algorithm is different from any previous platform; as such, we need a new framebuffer modifier to represent buffers in this format, but otherwise we can re-use the existing gen12 compression driver logic. DG2 clear color render compression uses Tile4 layout. Therefore, we need to define a new format modifier for uAPI to support clear color rendering. Signed-off-by: Matt Roper Signed-off-by: Mika Kahola (v2) Signed-off-by: Juha-Pekka Heikkilä Signed-off-by: Ramalingam C cc: Simon Ser Cc: Pekka Paalanen --- drivers/gpu/drm/i915/display/intel_display.c | 3 ++ .../drm/i915/display/intel_display_types.h| 10 +++- drivers/gpu/drm/i915/display/intel_fb.c | 7 +++ .../drm/i915/display/skl_universal_plane.c| 49 +-- include/uapi/drm/drm_fourcc.h | 30 5 files changed, 94 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9b678839bf2b..2949fe9f5b9f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1013,6 +1013,9 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) cmd->pixel_format); case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_F_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC: return lookup_format_info(gen12_ccs_formats, ARRAY_SIZE(gen12_ccs_formats), cmd->pixel_format); That seems not right. Flat CCS is invisible to the user so the format info should not include a CCS plane. I had cleaned out those rc and mc ccs from here long time ago, I wonder where did they come back from? On my development tree they're not there. Also I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC is here in totally wrong place, it should have its own gen12_flat_ccs_cc_formats table. /Juha-Pekka
Re: [Intel-gfx] [PATCH v2 14/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color
On Thu, Oct 21, 2021 at 07:56:24PM +0530, Ramalingam C wrote: > From: Matt Roper > > DG2 unifies render compression and media compression into a single > format for the first time. The programming and buffer layout is > supposed to match compression on older gen12 platforms, but the > actual compression algorithm is different from any previous platform; as > such, we need a new framebuffer modifier to represent buffers in this > format, but otherwise we can re-use the existing gen12 compression driver > logic. > > DG2 clear color render compression uses Tile4 layout. Therefore, we need > to define a new format modifier for uAPI to support clear color rendering. > > Signed-off-by: Matt Roper > Signed-off-by: Mika Kahola (v2) > Signed-off-by: Juha-Pekka Heikkilä > Signed-off-by: Ramalingam C > cc: Simon Ser > Cc: Pekka Paalanen > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 ++ > .../drm/i915/display/intel_display_types.h| 10 +++- > drivers/gpu/drm/i915/display/intel_fb.c | 7 +++ > .../drm/i915/display/skl_universal_plane.c| 49 +-- > include/uapi/drm/drm_fourcc.h | 30 > 5 files changed, 94 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 9b678839bf2b..2949fe9f5b9f 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1013,6 +1013,9 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 > *cmd) > cmd->pixel_format); > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > + case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS: > + case I915_FORMAT_MOD_F_TILED_DG2_MC_CCS: > + case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC: > return lookup_format_info(gen12_ccs_formats, > ARRAY_SIZE(gen12_ccs_formats), > cmd->pixel_format); That seems not right. Flat CCS is invisible to the user so the format info should not include a CCS plane. -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH v2 14/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color
For the include/uapi/drm/drm_fourcc.h changes: Acked-by: Simon Ser
[Intel-gfx] [PATCH v2 14/17] uapi/drm/dg2: Format modifier for DG2 unified compression and clear color
From: Matt Roper
DG2 unifies render compression and media compression into a single
format for the first time. The programming and buffer layout is
supposed to match compression on older gen12 platforms, but the
actual compression algorithm is different from any previous platform; as
such, we need a new framebuffer modifier to represent buffers in this
format, but otherwise we can re-use the existing gen12 compression driver
logic.
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
Signed-off-by: Matt Roper
Signed-off-by: Mika Kahola (v2)
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
cc: Simon Ser
Cc: Pekka Paalanen
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++
.../drm/i915/display/intel_display_types.h| 10 +++-
drivers/gpu/drm/i915/display/intel_fb.c | 7 +++
.../drm/i915/display/skl_universal_plane.c| 49 +--
include/uapi/drm/drm_fourcc.h | 30
5 files changed, 94 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9b678839bf2b..2949fe9f5b9f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1013,6 +1013,9 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
cmd->pixel_format);
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_F_TILED_DG2_MC_CCS:
+ case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC:
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39e11eaec1a3..3aa47a9965d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2047,14 +2047,20 @@ static inline bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+ modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+ modifier == I915_FORMAT_MOD_F_TILED_DG2_RC_CCS ||
+ modifier == I915_FORMAT_MOD_F_TILED_DG2_MC_CCS ||
+ modifier == I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC;
}
static inline bool is_gen12_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_F_TILED_DG2_RC_CCS ||
+ modifier == I915_FORMAT_MOD_F_TILED_DG2_MC_CCS ||
+ modifier == I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC;
}
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index e19739fef825..8216b03b8aae 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -127,6 +127,9 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_F_TILED_DG2_MC_CCS:
+ case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED:
/*
* Each 4K tile consists of 64B(8*8) subtiles, with
@@ -314,6 +317,10 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
+ case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC:
+ case I915_FORMAT_MOD_F_TILED_DG2_MC_CCS:
+ return 16 * 1024;
default:
MISSING_CASE(fb->modifier);
return 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 0eb4509f7f7a..0aaccaff46f7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -207,7 +207,19 @@ static const u64 adlp_step_a_plane_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+static const u64 dg2_step_a_b_plane_format_modifiers[] = {
+
