Re: [Intel-gfx] [PATCH v2 14/25] drm/i915: sanitize enable_rc6 option
On Mon, Apr 14, 2014 at 08:24:35PM +0300, Imre Deak wrote: Atm, an invalid enable_rc6 module option will be silently ignored, so emit an info message about it. Doing an early sanitization we can also reuse intel_enable_rc6() in a follow-up patch to see if RC6 is actually enabled. Currently the caller would have to filter a non-zero return value based on the platform we are running on. For example on VLV with i915.enable_rc6 set to 2, RC6 won't be enabled but atm intel_enable_rc6() would still return 2 in this case. Signed-off-by: Imre Deak imre.d...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 27 --- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a56f6b1..89fe0a7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3262,15 +3262,29 @@ static void intel_print_rc6_info(struct drm_device *dev, u32 mode) (mode GEN6_RC_CTL_RC6pp_ENABLE) ? on : off); } -int intel_enable_rc6(const struct drm_device *dev) +static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) { /* No RC6 before Ironlake */ if (INTEL_INFO(dev)-gen 5) return 0; /* Respect the kernel parameter if it is set */ - if (i915.enable_rc6 = 0) - return i915.enable_rc6; + if (enable_rc6 = 0) { + int mask = 0; + + if (IS_BROADWELL(dev) || IS_HASWELL(dev) || + IS_VALLEYVIEW(dev) || IS_IRONLAKE_M(dev)) + mask = INTEL_RC6_ENABLE; + else if (INTEL_INFO(dev)-gen = 6) + mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | +INTEL_RC6pp_ENABLE; You forgot ILK. Also this would seem simpler: if (SNB|IVB) mask = rc6 | rc6p | rc6pp; else mask = rc6; + + if ((enable_rc6 mask) != enable_rc6) + DRM_INFO(Adjusting RC6 mask to %d (requested %d, valid %d)\n, + enable_rc6, enable_rc6 mask, mask); + + return enable_rc6 mask; + } /* Disable RC6 on Ironlake */ if (INTEL_INFO(dev)-gen == 5) @@ -3282,6 +3296,11 @@ int intel_enable_rc6(const struct drm_device *dev) return INTEL_RC6_ENABLE; } +int intel_enable_rc6(const struct drm_device *dev) +{ + return i915.enable_rc6; +} + static void gen6_enable_rps_interrupts(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev-dev_private; @@ -4496,6 +4515,8 @@ static void intel_init_emon(struct drm_device *dev) void intel_init_gt_powersave(struct drm_device *dev) { + i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); + if (IS_VALLEYVIEW(dev)) valleyview_setup_pctx(dev); } -- 1.8.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 14/25] drm/i915: sanitize enable_rc6 option
On Wed, 2014-04-16 at 15:28 +0300, Ville Syrjälä wrote: On Mon, Apr 14, 2014 at 08:24:35PM +0300, Imre Deak wrote: Atm, an invalid enable_rc6 module option will be silently ignored, so emit an info message about it. Doing an early sanitization we can also reuse intel_enable_rc6() in a follow-up patch to see if RC6 is actually enabled. Currently the caller would have to filter a non-zero return value based on the platform we are running on. For example on VLV with i915.enable_rc6 set to 2, RC6 won't be enabled but atm intel_enable_rc6() would still return 2 in this case. Signed-off-by: Imre Deak imre.d...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 27 --- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a56f6b1..89fe0a7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3262,15 +3262,29 @@ static void intel_print_rc6_info(struct drm_device *dev, u32 mode) (mode GEN6_RC_CTL_RC6pp_ENABLE) ? on : off); } -int intel_enable_rc6(const struct drm_device *dev) +static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) { /* No RC6 before Ironlake */ if (INTEL_INFO(dev)-gen 5) return 0; /* Respect the kernel parameter if it is set */ - if (i915.enable_rc6 = 0) - return i915.enable_rc6; + if (enable_rc6 = 0) { + int mask = 0; + + if (IS_BROADWELL(dev) || IS_HASWELL(dev) || + IS_VALLEYVIEW(dev) || IS_IRONLAKE_M(dev)) + mask = INTEL_RC6_ENABLE; + else if (INTEL_INFO(dev)-gen = 6) + mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | + INTEL_RC6pp_ENABLE; You forgot ILK. For desktop ILK intel_enable_gt_powersave() will keep RC6 disabled, so the above is correct based on that. Also this would seem simpler: if (SNB|IVB) mask = rc6 | rc6p | rc6pp; else mask = rc6; Ok, can rewrite it with the above exception for desktop ILK. --Imre + + if ((enable_rc6 mask) != enable_rc6) + DRM_INFO(Adjusting RC6 mask to %d (requested %d, valid %d)\n, +enable_rc6, enable_rc6 mask, mask); + + return enable_rc6 mask; + } /* Disable RC6 on Ironlake */ if (INTEL_INFO(dev)-gen == 5) @@ -3282,6 +3296,11 @@ int intel_enable_rc6(const struct drm_device *dev) return INTEL_RC6_ENABLE; } +int intel_enable_rc6(const struct drm_device *dev) +{ + return i915.enable_rc6; +} + static void gen6_enable_rps_interrupts(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev-dev_private; @@ -4496,6 +4515,8 @@ static void intel_init_emon(struct drm_device *dev) void intel_init_gt_powersave(struct drm_device *dev) { + i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); + if (IS_VALLEYVIEW(dev)) valleyview_setup_pctx(dev); } -- 1.8.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 14/25] drm/i915: sanitize enable_rc6 option
Atm, an invalid enable_rc6 module option will be silently ignored, so emit an info message about it. Doing an early sanitization we can also reuse intel_enable_rc6() in a follow-up patch to see if RC6 is actually enabled. Currently the caller would have to filter a non-zero return value based on the platform we are running on. For example on VLV with i915.enable_rc6 set to 2, RC6 won't be enabled but atm intel_enable_rc6() would still return 2 in this case. Signed-off-by: Imre Deak imre.d...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 27 --- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a56f6b1..89fe0a7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3262,15 +3262,29 @@ static void intel_print_rc6_info(struct drm_device *dev, u32 mode) (mode GEN6_RC_CTL_RC6pp_ENABLE) ? on : off); } -int intel_enable_rc6(const struct drm_device *dev) +static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) { /* No RC6 before Ironlake */ if (INTEL_INFO(dev)-gen 5) return 0; /* Respect the kernel parameter if it is set */ - if (i915.enable_rc6 = 0) - return i915.enable_rc6; + if (enable_rc6 = 0) { + int mask = 0; + + if (IS_BROADWELL(dev) || IS_HASWELL(dev) || + IS_VALLEYVIEW(dev) || IS_IRONLAKE_M(dev)) + mask = INTEL_RC6_ENABLE; + else if (INTEL_INFO(dev)-gen = 6) + mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | + INTEL_RC6pp_ENABLE; + + if ((enable_rc6 mask) != enable_rc6) + DRM_INFO(Adjusting RC6 mask to %d (requested %d, valid %d)\n, +enable_rc6, enable_rc6 mask, mask); + + return enable_rc6 mask; + } /* Disable RC6 on Ironlake */ if (INTEL_INFO(dev)-gen == 5) @@ -3282,6 +3296,11 @@ int intel_enable_rc6(const struct drm_device *dev) return INTEL_RC6_ENABLE; } +int intel_enable_rc6(const struct drm_device *dev) +{ + return i915.enable_rc6; +} + static void gen6_enable_rps_interrupts(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev-dev_private; @@ -4496,6 +4515,8 @@ static void intel_init_emon(struct drm_device *dev) void intel_init_gt_powersave(struct drm_device *dev) { + i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); + if (IS_VALLEYVIEW(dev)) valleyview_setup_pctx(dev); } -- 1.8.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx