Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Disable/Enable PM Intrrupts based on the current freq.

[S, Deepak]

Hi Chris,

If I understand correctly we are using GEN6_RP_INTERRUPT_LIMITS to  Make sure 
we continue to get interrupts until we hit the minimum or maximum frequencies 
for gen6 right? Also, we do setup the 
gen6_set_rps_thresholds based on the power in gen6_set_rps right?

Instead of adding it in set_rps_thresholds, would it be better to add the 
Disable/Enable PM Intrrupts based on the current freq in valleyview_set_rps?

Let me know if my understanding is right.

Thanks
Deepak

-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] 
Sent: Tuesday, December 17, 2013 8:46 PM
To: S, Deepak
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Disable/Enable PM Intrrupts 
based on the current freq.

On Tue, Dec 17, 2013 at 08:35:40PM +0530, deepa...@intel.com wrote:
 From: Deepak S deepa...@intel.com
 
 When current delay is already at max delay, Let's disable the PM UP 
 THRESHOLD INTRRUPTS, so that we will not get further interrupts until 
 current delay is less than max delay, Also request for the PM DOWN 
 THRESHOLD INTRRUPTS to indicate the decrease in clock freq. and 
 viceversa for PM DOWN THRESHOLD INTRRUPTS.
 
 v2: Use bool variables (Daniel)
 
 Signed-off-by: Deepak S deepa...@intel.com

Nak. Why not do this with the rest of the threshold interrupt adjusting code?
-Chris

--
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[Intel-gfx] [PATCH v2 2/3] drm/i915: Disable/Enable PM Intrrupts based on the current freq.

[deepak . s]

From: Deepak S deepa...@intel.com

When current delay is already at max delay, Let's disable the PM UP
THRESHOLD INTRRUPTS, so that we will not get further interrupts until
current delay is less than max delay, Also request for the PM DOWN
THRESHOLD INTRRUPTS to indicate the decrease in clock freq. and
viceversa for PM DOWN THRESHOLD INTRRUPTS.

v2: Use bool variables (Daniel)

Signed-off-by: Deepak S deepa...@intel.com
---
 drivers/gpu/drm/i915/i915_drv.h |  3 +++
 drivers/gpu/drm/i915/i915_irq.c | 31 +--
 drivers/gpu/drm/i915/intel_pm.c |  3 +++
 3 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c638547..1a6cc69 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -914,6 +914,9 @@ struct intel_gen6_power_mgmt {
u8 rp0_delay;
u8 hw_max;
 
+   bool rp_up_masked;
+   bool rp_down_masked;
+
int last_adj;
enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1d44c79..9dd65a8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -988,7 +988,20 @@ static void gen6_pm_rps_work(struct work_struct *work)
adj *= 2;
else
adj = 1;
-   new_delay = dev_priv-rps.cur_delay + adj;
+
+   if (dev_priv-rps.cur_delay = dev_priv-rps.max_delay) {
+   I915_WRITE(GEN6_PMINTRMSK,
+   I915_READ(GEN6_PMINTRMSK) | 1  5);
+   dev_priv-rps.rp_up_masked = true;
+   new_delay = dev_priv-rps.cur_delay;
+   } else
+   new_delay = dev_priv-rps.cur_delay + adj;
+
+   if (dev_priv-rps.rp_down_masked) {
+   I915_WRITE(GEN6_PMINTRMSK,
+   I915_READ(GEN6_PMINTRMSK) | ~(1  4));
+   dev_priv-rps.rp_down_masked = false;
+   }
 
/*
 * For better performance, jump directly
@@ -1007,7 +1020,21 @@ static void gen6_pm_rps_work(struct work_struct *work)
adj *= 2;
else
adj = -1;
-   new_delay = dev_priv-rps.cur_delay + adj;
+
+   if (dev_priv-rps.cur_delay = dev_priv-rps.max_delay) {
+   I915_WRITE(GEN6_PMINTRMSK,
+   I915_READ(GEN6_PMINTRMSK) | 1  4);
+   dev_priv-rps.rp_down_masked = true;
+   new_delay = dev_priv-rps.cur_delay;
+   } else
+   new_delay = dev_priv-rps.cur_delay + adj;
+
+   if (dev_priv-rps.rp_up_masked) {
+   I915_WRITE(GEN6_PMINTRMSK,
+   I915_READ(GEN6_PMINTRMSK) | ~(1  5));
+   dev_priv-rps.rp_up_masked = false;
+   }
+
} else { /* unknown event */
new_delay = dev_priv-rps.cur_delay;
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7c98694..e6e933b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4166,6 +4166,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
 vlv_gpu_freq(dev_priv, dev_priv-rps.rpe_delay),
 dev_priv-rps.rpe_delay);
 
+   dev_priv-rps.rp_up_masked = 0;
+   dev_priv-rps.rp_down_masked = 0;
+
valleyview_set_rps(dev_priv-dev, dev_priv-rps.rpe_delay);
 
gen6_enable_rps_interrupts(dev);
-- 
1.8.4.2

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Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Disable/Enable PM Intrrupts based on the current freq.

[Chris Wilson]

On Tue, Dec 17, 2013 at 08:35:40PM +0530, deepa...@intel.com wrote:
 From: Deepak S deepa...@intel.com
 
 When current delay is already at max delay, Let's disable the PM UP
 THRESHOLD INTRRUPTS, so that we will not get further interrupts until
 current delay is less than max delay, Also request for the PM DOWN
 THRESHOLD INTRRUPTS to indicate the decrease in clock freq. and
 viceversa for PM DOWN THRESHOLD INTRRUPTS.
 
 v2: Use bool variables (Daniel)
 
 Signed-off-by: Deepak S deepa...@intel.com

Nak. Why not do this with the rest of the threshold interrupt adjusting
code?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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