subject:"\[Intel\-gfx\] \[PATCH v2 4\/8\] drm\/i915\: Flatten a bunch of the pfit functions"

Re: [Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions

2020-04-21 Thread Manasi Navare

On Thu, Apr 02, 2020 at 04:55:06PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 01, 2020 at 04:53:23PM -0700, Manasi Navare wrote:
> > On Wed, Feb 12, 2020 at 06:17:34PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä 
> > > 
> > > Most of the pfit functions are of the form:
> > > 
> > > func()
> > > {
> > >   if (pfit_enabled) {
> > >   ...
> > >   }
> > > }
> > > 
> > > Flip the pfit_enabled check around to flatten the functions.
> > > 
> > > And while we're touching all this let's do the usual
> > > s/pipe_config/crtc_state/ replacement.
> > > 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 233 +--
> > >  1 file changed, 115 insertions(+), 118 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index becc6322b7dc..796e27c4aece 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -6233,42 +6233,42 @@ static void skl_pfit_enable(const struct 
> > > intel_crtc_state *crtc_state)
> > >   enum pipe pipe = crtc->pipe;
> > >   const struct intel_crtc_scaler_state *scaler_state =
> > >   _state->scaler_state;
> > > + u16 uv_rgb_hphase, uv_rgb_vphase;
> > > + int pfit_w, pfit_h, hscale, vscale;
> > > + unsigned long irqflags;
> > > + int id;
> > >  
> > > - if (crtc_state->pch_pfit.enabled) {
> > > - u16 uv_rgb_hphase, uv_rgb_vphase;
> > > - int pfit_w, pfit_h, hscale, vscale;
> > > - unsigned long irqflags;
> > > - int id;
> > > + if (!crtc_state->pch_pfit.enabled)
> > > + return;
> > >  
> > > - if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> > > - return;
> > > + if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> > > + return;
> > >  
> > > - pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
> > > - pfit_h = crtc_state->pch_pfit.size & 0x;
> > > + pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
> > > + pfit_h = crtc_state->pch_pfit.size & 0x;
> > >  
> > > - hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
> > > - vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
> > > + hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
> > > + vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
> > >  
> > > - uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
> > > - uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> > > + uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
> > > + uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> > >  
> > > - id = scaler_state->scaler_id;
> > > + id = scaler_state->scaler_id;
> > >  
> > > - spin_lock_irqsave(_priv->uncore.lock, irqflags);
> > > + spin_lock_irqsave(_priv->uncore.lock, irqflags);
> > >  
> > > - intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN 
> > > |
> > > -   PS_FILTER_MEDIUM | 
> > > scaler_state->scalers[id].mode);
> > > - intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
> > > -   PS_Y_PHASE(0) | 
> > > PS_UV_RGB_PHASE(uv_rgb_vphase));
> > > - intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> > > -   PS_Y_PHASE(0) | 
> > > PS_UV_RGB_PHASE(uv_rgb_hphase));
> > > - intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> > > -   crtc_state->pch_pfit.pos);
> > > - intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> > > -   crtc_state->pch_pfit.size);
> > > + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
> > > +   PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
> > > + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
> > > +   PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
> > > + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> > > +   PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> > > + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> > > +   crtc_state->pch_pfit.pos);
> > > + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> > > +   crtc_state->pch_pfit.size);
> > >  
> > > - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> > > - }
> > > + spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> > >  }
> > >  
> > >  static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> > > @@ -6277,22 +6277,23 @@ static void ilk_pfit_enable(const struct 
> > > intel_crtc_state *crtc_state)
> > >   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >   enum pipe pipe = crtc->pipe;
> > >  
> > > - if (crtc_state->pch_pfit.enabled) {
> > > - /* Force use of hard-coded filter coefficients
> > > -  * as some pre-programmed values are broken,
> > > -  * e.g. x201.
> > >

Re: [Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions

2020-04-02 Thread Ville Syrjälä

On Wed, Apr 01, 2020 at 04:53:23PM -0700, Manasi Navare wrote:
> On Wed, Feb 12, 2020 at 06:17:34PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Most of the pfit functions are of the form:
> > 
> > func()
> > {
> > if (pfit_enabled) {
> > ...
> > }
> > }
> > 
> > Flip the pfit_enabled check around to flatten the functions.
> > 
> > And while we're touching all this let's do the usual
> > s/pipe_config/crtc_state/ replacement.
> > 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 233 +--
> >  1 file changed, 115 insertions(+), 118 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index becc6322b7dc..796e27c4aece 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6233,42 +6233,42 @@ static void skl_pfit_enable(const struct 
> > intel_crtc_state *crtc_state)
> > enum pipe pipe = crtc->pipe;
> > const struct intel_crtc_scaler_state *scaler_state =
> > _state->scaler_state;
> > +   u16 uv_rgb_hphase, uv_rgb_vphase;
> > +   int pfit_w, pfit_h, hscale, vscale;
> > +   unsigned long irqflags;
> > +   int id;
> >  
> > -   if (crtc_state->pch_pfit.enabled) {
> > -   u16 uv_rgb_hphase, uv_rgb_vphase;
> > -   int pfit_w, pfit_h, hscale, vscale;
> > -   unsigned long irqflags;
> > -   int id;
> > +   if (!crtc_state->pch_pfit.enabled)
> > +   return;
> >  
> > -   if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> > -   return;
> > +   if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> > +   return;
> >  
> > -   pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
> > -   pfit_h = crtc_state->pch_pfit.size & 0x;
> > +   pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
> > +   pfit_h = crtc_state->pch_pfit.size & 0x;
> >  
> > -   hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
> > -   vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
> > +   hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
> > +   vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
> >  
> > -   uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
> > -   uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> > +   uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
> > +   uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> >  
> > -   id = scaler_state->scaler_id;
> > +   id = scaler_state->scaler_id;
> >  
> > -   spin_lock_irqsave(_priv->uncore.lock, irqflags);
> > +   spin_lock_irqsave(_priv->uncore.lock, irqflags);
> >  
> > -   intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN 
> > |
> > - PS_FILTER_MEDIUM | 
> > scaler_state->scalers[id].mode);
> > -   intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
> > - PS_Y_PHASE(0) | 
> > PS_UV_RGB_PHASE(uv_rgb_vphase));
> > -   intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> > - PS_Y_PHASE(0) | 
> > PS_UV_RGB_PHASE(uv_rgb_hphase));
> > -   intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> > - crtc_state->pch_pfit.pos);
> > -   intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> > - crtc_state->pch_pfit.size);
> > +   intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
> > + PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
> > +   intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
> > + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
> > +   intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> > + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> > +   intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> > + crtc_state->pch_pfit.pos);
> > +   intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> > + crtc_state->pch_pfit.size);
> >  
> > -   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> > -   }
> > +   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> >  }
> >  
> >  static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> > @@ -6277,22 +6277,23 @@ static void ilk_pfit_enable(const struct 
> > intel_crtc_state *crtc_state)
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum pipe pipe = crtc->pipe;
> >  
> > -   if (crtc_state->pch_pfit.enabled) {
> > -   /* Force use of hard-coded filter coefficients
> > -* as some pre-programmed values are broken,
> > -* e.g. x201.
> > -*/
> > -   if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
> > -   intel_de_write(dev_priv, PF_CTL(pipe),
> > -

Re: [Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions

2020-04-01 Thread Manasi Navare

On Wed, Feb 12, 2020 at 06:17:34PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Most of the pfit functions are of the form:
> 
> func()
> {
>   if (pfit_enabled) {
>   ...
>   }
> }
> 
> Flip the pfit_enabled check around to flatten the functions.
> 
> And while we're touching all this let's do the usual
> s/pipe_config/crtc_state/ replacement.
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 233 +--
>  1 file changed, 115 insertions(+), 118 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index becc6322b7dc..796e27c4aece 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6233,42 +6233,42 @@ static void skl_pfit_enable(const struct 
> intel_crtc_state *crtc_state)
>   enum pipe pipe = crtc->pipe;
>   const struct intel_crtc_scaler_state *scaler_state =
>   _state->scaler_state;
> + u16 uv_rgb_hphase, uv_rgb_vphase;
> + int pfit_w, pfit_h, hscale, vscale;
> + unsigned long irqflags;
> + int id;
>  
> - if (crtc_state->pch_pfit.enabled) {
> - u16 uv_rgb_hphase, uv_rgb_vphase;
> - int pfit_w, pfit_h, hscale, vscale;
> - unsigned long irqflags;
> - int id;
> + if (!crtc_state->pch_pfit.enabled)
> + return;
>  
> - if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> - return;
> + if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
> + return;
>  
> - pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
> - pfit_h = crtc_state->pch_pfit.size & 0x;
> + pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
> + pfit_h = crtc_state->pch_pfit.size & 0x;
>  
> - hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
> - vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
> + hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
> + vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
>  
> - uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
> - uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
> + uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
> + uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
>  
> - id = scaler_state->scaler_id;
> + id = scaler_state->scaler_id;
>  
> - spin_lock_irqsave(_priv->uncore.lock, irqflags);
> + spin_lock_irqsave(_priv->uncore.lock, irqflags);
>  
> - intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN 
> |
> -   PS_FILTER_MEDIUM | 
> scaler_state->scalers[id].mode);
> - intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
> -   PS_Y_PHASE(0) | 
> PS_UV_RGB_PHASE(uv_rgb_vphase));
> - intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> -   PS_Y_PHASE(0) | 
> PS_UV_RGB_PHASE(uv_rgb_hphase));
> - intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> -   crtc_state->pch_pfit.pos);
> - intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> -   crtc_state->pch_pfit.size);
> + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
> +   PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
> + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
> +   PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
> + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> +   PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> +   crtc_state->pch_pfit.pos);
> + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> +   crtc_state->pch_pfit.size);
>  
> - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> - }
> + spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
>  }
>  
>  static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> @@ -6277,22 +6277,23 @@ static void ilk_pfit_enable(const struct 
> intel_crtc_state *crtc_state)
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   enum pipe pipe = crtc->pipe;
>  
> - if (crtc_state->pch_pfit.enabled) {
> - /* Force use of hard-coded filter coefficients
> -  * as some pre-programmed values are broken,
> -  * e.g. x201.
> -  */
> - if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
> - intel_de_write(dev_priv, PF_CTL(pipe),
> -PF_ENABLE | PF_FILTER_MED_3x3 | 
> PF_PIPE_SEL_IVB(pipe));
> - else
> -

[Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions

2020-02-12 Thread Ville Syrjala

From: Ville Syrjälä 

Most of the pfit functions are of the form:

func()
{
if (pfit_enabled) {
...
}
}

Flip the pfit_enabled check around to flatten the functions.

And while we're touching all this let's do the usual
s/pipe_config/crtc_state/ replacement.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c | 233 +--
 1 file changed, 115 insertions(+), 118 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index becc6322b7dc..796e27c4aece 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6233,42 +6233,42 @@ static void skl_pfit_enable(const struct 
intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
const struct intel_crtc_scaler_state *scaler_state =
_state->scaler_state;
+   u16 uv_rgb_hphase, uv_rgb_vphase;
+   int pfit_w, pfit_h, hscale, vscale;
+   unsigned long irqflags;
+   int id;
 
-   if (crtc_state->pch_pfit.enabled) {
-   u16 uv_rgb_hphase, uv_rgb_vphase;
-   int pfit_w, pfit_h, hscale, vscale;
-   unsigned long irqflags;
-   int id;
+   if (!crtc_state->pch_pfit.enabled)
+   return;
 
-   if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
-   return;
+   if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
+   return;
 
-   pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
-   pfit_h = crtc_state->pch_pfit.size & 0x;
+   pfit_w = (crtc_state->pch_pfit.size >> 16) & 0x;
+   pfit_h = crtc_state->pch_pfit.size & 0x;
 
-   hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
-   vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
+   hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
+   vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
 
-   uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
-   uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
+   uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
+   uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
 
-   id = scaler_state->scaler_id;
+   id = scaler_state->scaler_id;
 
-   spin_lock_irqsave(_priv->uncore.lock, irqflags);
+   spin_lock_irqsave(_priv->uncore.lock, irqflags);
 
-   intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN 
|
- PS_FILTER_MEDIUM | 
scaler_state->scalers[id].mode);
-   intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
- PS_Y_PHASE(0) | 
PS_UV_RGB_PHASE(uv_rgb_vphase));
-   intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
- PS_Y_PHASE(0) | 
PS_UV_RGB_PHASE(uv_rgb_hphase));
-   intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
- crtc_state->pch_pfit.pos);
-   intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
- crtc_state->pch_pfit.size);
+   intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
+ PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
+   intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
+   intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
+   intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
+ crtc_state->pch_pfit.pos);
+   intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
+ crtc_state->pch_pfit.size);
 
-   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
-   }
+   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
 }
 
 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -6277,22 +6277,23 @@ static void ilk_pfit_enable(const struct 
intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
 
-   if (crtc_state->pch_pfit.enabled) {
-   /* Force use of hard-coded filter coefficients
-* as some pre-programmed values are broken,
-* e.g. x201.
-*/
-   if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
-   intel_de_write(dev_priv, PF_CTL(pipe),
-  PF_ENABLE | PF_FILTER_MED_3x3 | 
PF_PIPE_SEL_IVB(pipe));
-   else
-   intel_de_write(dev_priv, PF_CTL(pipe),
-  PF_ENABLE | PF_FILTER_MED_3x3);
-   intel_de_write(dev_priv, PF_WIN_POS(pipe),
-

Re: [Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions

Re: [Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions

Re: [Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions

[Intel-gfx] [PATCH v2 4/8] drm/i915: Flatten a bunch of the pfit functions

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