On Mon, Apr 28, 2014 at 02:00:42PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Rafael Barbalho
>
> Add support for the third pipe in cherrview
>
> v2: Don't use spaces for indentation (Jani)
> Wrap long lines
>
> Reviewed-by: Imre Deak
> Signed-off-by: Rafael Barbalho
> [vsyrjala: slightly massaged the patch]
> Signed-off-by: Ville Syrjälä
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.c | 12
> drivers/gpu/drm/i915/i915_reg.h | 11 ---
> 2 files changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 3f57237..0fd3046 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,17 @@ static struct drm_driver driver;
> .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
> .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
>
> +#define GEN_CHV_PIPEOFFSETS \
> + .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> + CHV_PIPE_C_OFFSET }, \
> + .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> +CHV_TRANSCODER_C_OFFSET, }, \
> + .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
> + CHV_DPLL_C_OFFSET }, \
> + .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
> + CHV_DPLL_C_MD_OFFSET }, \
> + .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
> + CHV_PALETTE_C_OFFSET }
>
> static const struct intel_device_info intel_i830_info = {
> .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> @@ -286,6 +297,7 @@ static const struct intel_device_info
> intel_cherryview_info = {
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> .is_valleyview = 1,
> .display_mmio_offset = VLV_DISPLAY_BASE,
> + GEN_CHV_PIPEOFFSETS,
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 74ac1c2..9138eff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1440,6 +1440,7 @@ enum punit_power_well {
> */
> #define DPLL_A_OFFSET 0x6014
> #define DPLL_B_OFFSET 0x6018
> +#define CHV_DPLL_C_OFFSET 0x6030
> #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
> dev_priv->info.display_mmio_offset)
>
> @@ -1531,6 +1532,7 @@ enum punit_power_well {
>
> #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
> #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
> +#define CHV_DPLL_C_MD_OFFSET 0x603c
> #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
> dev_priv->info.display_mmio_offset)
>
> @@ -1727,6 +1729,7 @@ enum punit_power_well {
> */
> #define PALETTE_A_OFFSET 0xa000
> #define PALETTE_B_OFFSET 0xa800
> +#define CHV_PALETTE_C_OFFSET 0xc000
> #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
> dev_priv->info.display_mmio_offset)
>
> @@ -2216,6 +2219,7 @@ enum punit_power_well {
> #define TRANSCODER_A_OFFSET 0x6
> #define TRANSCODER_B_OFFSET 0x61000
> #define TRANSCODER_C_OFFSET 0x62000
> +#define CHV_TRANSCODER_C_OFFSET 0x63000
> #define TRANSCODER_EDP_OFFSET 0x6f000
>
> #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
> @@ -3543,9 +3547,10 @@ enum punit_power_well {
> #define PIPESTAT_INT_ENABLE_MASK 0x7fff
> #define PIPESTAT_INT_STATUS_MASK 0x
>
> -#define PIPE_A_OFFSET0x7
> -#define PIPE_B_OFFSET0x71000
> -#define PIPE_C_OFFSET0x72000
> +#define PIPE_A_OFFSET0x7
> +#define PIPE_B_OFFSET0x71000
> +#define PIPE_C_OFFSET0x72000
> +#define CHV_PIPE_C_OFFSET0x74000
> /*
> * There's actually no pipe EDP. Some pipe registers have
> * simply shifted from the pipe to the transcoder, while
> --
> 1.8.3.2
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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