Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible
On Wed, Mar 09, 2022 at 09:34:58PM +0200, Lisovskiy, Stanislav wrote: > On Wed, Mar 09, 2022 at 09:08:12PM +0200, Ville Syrjälä wrote: > > On Wed, Mar 09, 2022 at 08:59:59PM +0200, Lisovskiy, Stanislav wrote: > > > On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote: > > > > From: Ville Syrjälä > > > > > > > > Don't just mask off all the PSF GV points when SAGV gets disabled. > > > > This should in fact cause the Pcode to reject the request since > > > > at least one PSF point must remain enabled at all times. > > > > > > Good point, however I think this is not the full fix: > > > > > > BSpec says: > > > > > > "At least one GV point of each type must always remain unmasked." > > > > > > and > > > > > > "The GV point of each type providing the highest bandwidth > > > for display must always remain unmasked." > > > > > > So I guess we should then also choose thr PSF GV point with > > > the highest bandwidth as well. > > > > The spec says PSF GV is fast enough to now stall the display data > > fetch so we don't need to restrict the PSF points here. > > But why it asks to ensure that we have the PSF GV of highest bandwidth to > stay always unmasked then? > > Stan Reviewed-by: Stanislav Lisovskiy > > > > > -- > > Ville Syrjälä > > Intel
Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible
On Wed, Mar 09, 2022 at 09:34:58PM +0200, Lisovskiy, Stanislav wrote: > On Wed, Mar 09, 2022 at 09:08:12PM +0200, Ville Syrjälä wrote: > > On Wed, Mar 09, 2022 at 08:59:59PM +0200, Lisovskiy, Stanislav wrote: > > > On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote: > > > > From: Ville Syrjälä > > > > > > > > Don't just mask off all the PSF GV points when SAGV gets disabled. > > > > This should in fact cause the Pcode to reject the request since > > > > at least one PSF point must remain enabled at all times. > > > > > > Good point, however I think this is not the full fix: > > > > > > BSpec says: > > > > > > "At least one GV point of each type must always remain unmasked." > > > > > > and > > > > > > "The GV point of each type providing the highest bandwidth > > > for display must always remain unmasked." > > > > > > So I guess we should then also choose thr PSF GV point with > > > the highest bandwidth as well. > > > > The spec says PSF GV is fast enough to now stall the display data > > fetch so we don't need to restrict the PSF points here. > > But why it asks to ensure that we have the PSF GV of highest bandwidth to > stay always unmasked then? I presume so you don't lock the memory bandwdith to some lower performance point and hurt all the other things that need memory bandwidth. Either that or there is some internal implementation detail that simply doesn't work if you try to permanently run at a lower performance point. -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible
On Wed, Mar 09, 2022 at 09:08:12PM +0200, Ville Syrjälä wrote: > On Wed, Mar 09, 2022 at 08:59:59PM +0200, Lisovskiy, Stanislav wrote: > > On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > > > Don't just mask off all the PSF GV points when SAGV gets disabled. > > > This should in fact cause the Pcode to reject the request since > > > at least one PSF point must remain enabled at all times. > > > > Good point, however I think this is not the full fix: > > > > BSpec says: > > > > "At least one GV point of each type must always remain unmasked." > > > > and > > > > "The GV point of each type providing the highest bandwidth > > for display must always remain unmasked." > > > > So I guess we should then also choose thr PSF GV point with > > the highest bandwidth as well. > > The spec says PSF GV is fast enough to now stall the display data > fetch so we don't need to restrict the PSF points here. But why it asks to ensure that we have the PSF GV of highest bandwidth to stay always unmasked then? Stan > > -- > Ville Syrjälä > Intel
Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible
On Wed, Mar 09, 2022 at 08:59:59PM +0200, Lisovskiy, Stanislav wrote: > On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Don't just mask off all the PSF GV points when SAGV gets disabled. > > This should in fact cause the Pcode to reject the request since > > at least one PSF point must remain enabled at all times. > > Good point, however I think this is not the full fix: > > BSpec says: > > "At least one GV point of each type must always remain unmasked." > > and > > "The GV point of each type providing the highest bandwidth > for display must always remain unmasked." > > So I guess we should then also choose thr PSF GV point with > the highest bandwidth as well. The spec says PSF GV is fast enough to now stall the display data fetch so we don't need to restrict the PSF points here. -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible
On Wed, Mar 09, 2022 at 06:49:46PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Don't just mask off all the PSF GV points when SAGV gets disabled.
> This should in fact cause the Pcode to reject the request since
> at least one PSF point must remain enabled at all times.
Good point, however I think this is not the full fix:
BSpec says:
"At least one GV point of each type must always remain unmasked."
and
"The GV point of each type providing the highest bandwidth
for display must always remain unmasked."
So I guess we should then also choose thr PSF GV point with
the highest bandwidth as well.
Stan
>
> Cc: sta...@vger.kernel.org
> Cc: Stanislav Lisovskiy
> Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index ad1564ca7269..adf58c58513b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
>* cause.
>*/
> if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
> - allowed_points = BIT(max_bw_point);
> + allowed_points &= ADLS_PSF_PT_MASK;
> + allowed_points |= BIT(max_bw_point);
> drm_dbg_kms(_priv->drm, "No SAGV, using single QGV point
> %d\n",
> max_bw_point);
> }
> --
> 2.34.1
>
[Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible
From: Ville Syrjälä
Don't just mask off all the PSF GV points when SAGV gets disabled.
This should in fact cause the Pcode to reject the request since
at least one PSF point must remain enabled at all times.
Cc: sta...@vger.kernel.org
Cc: Stanislav Lisovskiy
Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index ad1564ca7269..adf58c58513b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
* cause.
*/
if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
- allowed_points = BIT(max_bw_point);
+ allowed_points &= ADLS_PSF_PT_MASK;
+ allowed_points |= BIT(max_bw_point);
drm_dbg_kms(_priv->drm, "No SAGV, using single QGV point
%d\n",
max_bw_point);
}
--
2.34.1
