Re: [Intel-gfx] [PATCH v2 6/9] drm/i915: Enable DisplayPort in Valleyview
On Thu, Sep 27, 2012 at 08:23:37AM -0700, Jesse Barnes wrote:
On Thu, 27 Sep 2012 19:13:06 +0530
Vijay Purushothaman vijay.a.purushotha...@intel.com wrote:
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.
Cleaned up DPLL calculations for Valleyview to support multi display
configurations.
v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as
separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Small bikeshed: I've killed some spurious whitespace changs while
applying ...
-Daniel
---
drivers/gpu/drm/i915/i915_reg.h |8 +--
drivers/gpu/drm/i915/intel_display.c | 90
--
2 files changed, 66 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index 3f75ee6..0fe4aad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -385,12 +385,8 @@
#define DPIO_FASTCLK_DISABLE 0x8100
-#define _DPIO_DATA_LANE0 0x0220
-#define _DPIO_DATA_LANE1 0x0420
-#define _DPIO_DATA_LANE2 0x2620
-#define _DPIO_DATA_LANE3 0x2820
-#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0,
_DPIO_DATA_LANE2)
-#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1,
_DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1 0x8220
+#define DPIO_DATA_CHANNEL2 0x8420
/*
* Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 68828e7..ed749c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4017,7 +4017,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
intel_clock_t *clock, intel_clock_t *reduced_clock,
- int refclk, int num_connectors)
+ int num_connectors)
{
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -4025,9 +4025,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
int pipe = intel_crtc-pipe;
u32 dpll, mdiv, pdiv;
u32 bestn, bestm1, bestm2, bestp1, bestp2;
- bool is_hdmi;
+ bool is_sdvo;
+ u32 temp;
+
+ is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
- is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+ dpll = DPLL_VGA_MODE_DIS;
+ dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+ dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+ dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+
+ I915_WRITE(DPLL(pipe), dpll);
+ POSTING_READ(DPLL(pipe));
bestn = clock-n;
bestm1 = clock-m1;
@@ -4035,12 +4045,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
bestp1 = clock-p1;
bestp2 = clock-p2;
- /* Enable DPIO clock input */
- dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
- DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
- I915_WRITE(DPLL(pipe), dpll);
- POSTING_READ(DPLL(pipe));
-
+ /*
+* In Valleyview PLL and program lane counter registers are exposed
+* through DPIO interface
+*/
mdiv = ((bestm1 DPIO_M1DIV_SHIFT) | (bestm2 DPIO_M2DIV_MASK));
mdiv |= ((bestp1 DPIO_P1_SHIFT) | (bestp2 DPIO_P2_SHIFT));
mdiv |= ((bestn DPIO_N_SHIFT));
@@ -4051,12 +4059,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x0100);
- pdiv = DPIO_REFSEL_OVERRIDE | (5 DPIO_PLL_MODESEL_SHIFT) |
+ pdiv = (1 DPIO_REFSEL_OVERRIDE) | (5 DPIO_PLL_MODESEL_SHIFT) |
(3 DPIO_BIAS_CURRENT_CTL_SHIFT) | (120) |
- (8 DPIO_DRIVER_CTL_SHIFT) | (5 DPIO_CLK_BIAS_CTL_SHIFT);
+ (7 DPIO_PLL_REFCLK_SEL_SHIFT) | (8 DPIO_DRIVER_CTL_SHIFT)
|
+ (5 DPIO_CLK_BIAS_CTL_SHIFT);
intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
- intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+ intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
@@ -4064,21 +4073,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
if (wait_for(((I915_READ(DPLL(pipe)) DPLL_LOCK_VLV) ==
DPLL_LOCK_VLV), 1))
DRM_ERROR(DPLL %d failed to lock\n, pipe);
- if (is_hdmi) {
- u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+ intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+
[Intel-gfx] [PATCH v2 6/9] drm/i915: Enable DisplayPort in Valleyview
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.
Cleaned up DPLL calculations for Valleyview to support multi display
configurations.
v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as
separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8 +--
drivers/gpu/drm/i915/intel_display.c | 90 --
2 files changed, 66 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f75ee6..0fe4aad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -385,12 +385,8 @@
#define DPIO_FASTCLK_DISABLE 0x8100
-#define _DPIO_DATA_LANE0 0x0220
-#define _DPIO_DATA_LANE1 0x0420
-#define _DPIO_DATA_LANE2 0x2620
-#define _DPIO_DATA_LANE3 0x2820
-#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
-#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1 0x8220
+#define DPIO_DATA_CHANNEL2 0x8420
/*
* Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 68828e7..ed749c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4017,7 +4017,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
intel_clock_t *clock, intel_clock_t *reduced_clock,
- int refclk, int num_connectors)
+ int num_connectors)
{
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -4025,9 +4025,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
int pipe = intel_crtc-pipe;
u32 dpll, mdiv, pdiv;
u32 bestn, bestm1, bestm2, bestp1, bestp2;
- bool is_hdmi;
+ bool is_sdvo;
+ u32 temp;
+
+ is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
- is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+ dpll = DPLL_VGA_MODE_DIS;
+ dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+ dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+ dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+
+ I915_WRITE(DPLL(pipe), dpll);
+ POSTING_READ(DPLL(pipe));
bestn = clock-n;
bestm1 = clock-m1;
@@ -4035,12 +4045,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
bestp1 = clock-p1;
bestp2 = clock-p2;
- /* Enable DPIO clock input */
- dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
- DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
- I915_WRITE(DPLL(pipe), dpll);
- POSTING_READ(DPLL(pipe));
-
+ /*
+* In Valleyview PLL and program lane counter registers are exposed
+* through DPIO interface
+*/
mdiv = ((bestm1 DPIO_M1DIV_SHIFT) | (bestm2 DPIO_M2DIV_MASK));
mdiv |= ((bestp1 DPIO_P1_SHIFT) | (bestp2 DPIO_P2_SHIFT));
mdiv |= ((bestn DPIO_N_SHIFT));
@@ -4051,12 +4059,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x0100);
- pdiv = DPIO_REFSEL_OVERRIDE | (5 DPIO_PLL_MODESEL_SHIFT) |
+ pdiv = (1 DPIO_REFSEL_OVERRIDE) | (5 DPIO_PLL_MODESEL_SHIFT) |
(3 DPIO_BIAS_CURRENT_CTL_SHIFT) | (120) |
- (8 DPIO_DRIVER_CTL_SHIFT) | (5 DPIO_CLK_BIAS_CTL_SHIFT);
+ (7 DPIO_PLL_REFCLK_SEL_SHIFT) | (8 DPIO_DRIVER_CTL_SHIFT)
|
+ (5 DPIO_CLK_BIAS_CTL_SHIFT);
intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
- intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+ intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
@@ -4064,21 +4073,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
if (wait_for(((I915_READ(DPLL(pipe)) DPLL_LOCK_VLV) ==
DPLL_LOCK_VLV), 1))
DRM_ERROR(DPLL %d failed to lock\n, pipe);
- if (is_hdmi) {
- u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+ intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ intel_dp_set_m_n(crtc, mode, adjusted_mode);
+
+ I915_WRITE(DPLL(pipe), dpll);
+
+ /* Wait for the clocks to stabilize. */
+ POSTING_READ(DPLL(pipe));
+
Re: [Intel-gfx] [PATCH v2 6/9] drm/i915: Enable DisplayPort in Valleyview
On Thu, 27 Sep 2012 19:13:06 +0530
Vijay Purushothaman vijay.a.purushotha...@intel.com wrote:
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.
Cleaned up DPLL calculations for Valleyview to support multi display
configurations.
v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as
separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8 +--
drivers/gpu/drm/i915/intel_display.c | 90
--
2 files changed, 66 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f75ee6..0fe4aad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -385,12 +385,8 @@
#define DPIO_FASTCLK_DISABLE 0x8100
-#define _DPIO_DATA_LANE0 0x0220
-#define _DPIO_DATA_LANE1 0x0420
-#define _DPIO_DATA_LANE2 0x2620
-#define _DPIO_DATA_LANE3 0x2820
-#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0,
_DPIO_DATA_LANE2)
-#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1,
_DPIO_DATA_LANE3)
+#define DPIO_DATA_CHANNEL1 0x8220
+#define DPIO_DATA_CHANNEL2 0x8420
/*
* Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 68828e7..ed749c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4017,7 +4017,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
intel_clock_t *clock, intel_clock_t *reduced_clock,
-int refclk, int num_connectors)
+int num_connectors)
{
struct drm_device *dev = crtc-dev;
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -4025,9 +4025,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
int pipe = intel_crtc-pipe;
u32 dpll, mdiv, pdiv;
u32 bestn, bestm1, bestm2, bestp1, bestp2;
- bool is_hdmi;
+ bool is_sdvo;
+ u32 temp;
+
+ is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
- is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+ dpll = DPLL_VGA_MODE_DIS;
+ dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
+ dpll |= DPLL_REFA_CLK_ENABLE_VLV;
+ dpll |= DPLL_INTEGRATED_CLOCK_VLV;
+
+ I915_WRITE(DPLL(pipe), dpll);
+ POSTING_READ(DPLL(pipe));
bestn = clock-n;
bestm1 = clock-m1;
@@ -4035,12 +4045,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
bestp1 = clock-p1;
bestp2 = clock-p2;
- /* Enable DPIO clock input */
- dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
- DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
- I915_WRITE(DPLL(pipe), dpll);
- POSTING_READ(DPLL(pipe));
-
+ /*
+ * In Valleyview PLL and program lane counter registers are exposed
+ * through DPIO interface
+ */
mdiv = ((bestm1 DPIO_M1DIV_SHIFT) | (bestm2 DPIO_M2DIV_MASK));
mdiv |= ((bestp1 DPIO_P1_SHIFT) | (bestp2 DPIO_P2_SHIFT));
mdiv |= ((bestn DPIO_N_SHIFT));
@@ -4051,12 +4059,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x0100);
- pdiv = DPIO_REFSEL_OVERRIDE | (5 DPIO_PLL_MODESEL_SHIFT) |
+ pdiv = (1 DPIO_REFSEL_OVERRIDE) | (5 DPIO_PLL_MODESEL_SHIFT) |
(3 DPIO_BIAS_CURRENT_CTL_SHIFT) | (120) |
- (8 DPIO_DRIVER_CTL_SHIFT) | (5 DPIO_CLK_BIAS_CTL_SHIFT);
+ (7 DPIO_PLL_REFCLK_SEL_SHIFT) | (8 DPIO_DRIVER_CTL_SHIFT)
|
+ (5 DPIO_CLK_BIAS_CTL_SHIFT);
intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
- intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+ intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
dpll |= DPLL_VCO_ENABLE;
I915_WRITE(DPLL(pipe), dpll);
@@ -4064,21 +4073,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
if (wait_for(((I915_READ(DPLL(pipe)) DPLL_LOCK_VLV) ==
DPLL_LOCK_VLV), 1))
DRM_ERROR(DPLL %d failed to lock\n, pipe);
- if (is_hdmi) {
- u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+ intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
+
+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+ intel_dp_set_m_n(crtc, mode, adjusted_mode);
+
+ I915_WRITE(DPLL(pipe),
