[Intel-gfx] [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-15 Thread deepak . s 
From: Deepak S deepa...@linux.intel.com

This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by: Deepak S deepa...@linux.intel.com
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_uncore.c | 8 
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL 0x120008
 #defineGT_FIFO_FREE_ENTRIES_MASK   0x7f
 #defineGT_FIFO_NUM_RESERVED_ENTRIES20
+#define   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1  12)
+#define   GT_FIFO_CTL_RC6_POLICY_STALL (1  11)
 
 #define  HSW_IDICR 0x9008
 #defineIDIHASHMSK(x)   (((x)  0x3f)  16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index d96d15f..26d6dda 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct 
drm_device *dev,
__raw_i915_write32(dev_priv, GTFIFODBG,
   __raw_i915_read32(dev_priv, GTFIFODBG));
 
+   /* WaDisableShadowRegForCpd */
+   if (IS_CHERRYVIEW(dev)) {
+   __raw_i915_write32(dev_priv, GTFIFOCTL,
+   __raw_i915_read32(dev_priv, GTFIFOCTL) |
+   
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+   GT_FIFO_CTL_RC6_POLICY_STALL);
+   }
+
intel_uncore_forcewake_reset(dev, restore_forcewake);
 }
 
-- 
1.9.1

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Re: [Intel-gfx] [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-15 Thread Ville Syrjälä 
On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepa...@linux.intel.com wrote:
 From: Deepak S deepa...@linux.intel.com
 
 This WA is avoid problem between shadow vs wake FIFO unload
 problem during CPD/RC6 transactions on CHV.
 
 v2: Define individual bits GTFIFOCTL (Ville)
 
 v3: move WA to uncore_early_sanitize (ville)
 
 Signed-off-by: Deepak S deepa...@linux.intel.com
 ---
  drivers/gpu/drm/i915/i915_reg.h | 2 ++
  drivers/gpu/drm/i915/intel_uncore.c | 8 
  2 files changed, 10 insertions(+)
 
 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
 index 9c97842..a642a58 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
  #define  GTFIFOCTL   0x120008
  #defineGT_FIFO_FREE_ENTRIES_MASK 0x7f
  #defineGT_FIFO_NUM_RESERVED_ENTRIES  20
 +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1  12)
 +#define GT_FIFO_CTL_RC6_POLICY_STALL (1  11)
  
  #define  HSW_IDICR   0x9008
  #defineIDIHASHMSK(x) (((x)  0x3f)  16)
 diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
 b/drivers/gpu/drm/i915/intel_uncore.c
 index d96d15f..26d6dda 100644
 --- a/drivers/gpu/drm/i915/intel_uncore.c
 +++ b/drivers/gpu/drm/i915/intel_uncore.c
 @@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct 
 drm_device *dev,
   __raw_i915_write32(dev_priv, GTFIFODBG,
  __raw_i915_read32(dev_priv, GTFIFODBG));
  
 + /* WaDisableShadowRegForCpd */

I couldn't find this w/a name anywhere official, but I guess it's fine.
Should be WaDisableShadowRegForCpd:chv though. Otherwise looks good, so

Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com

 + if (IS_CHERRYVIEW(dev)) {
 + __raw_i915_write32(dev_priv, GTFIFOCTL,
 + __raw_i915_read32(dev_priv, GTFIFOCTL) |
 + 
 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 + GT_FIFO_CTL_RC6_POLICY_STALL);
 + }
 +
   intel_uncore_forcewake_reset(dev, restore_forcewake);
  }
  
 -- 
 1.9.1

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-15 Thread Deepak S 



On Thursday 16 April 2015 12:09 AM, Ville Syrjälä wrote:

On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepa...@linux.intel.com wrote:

From: Deepak S deepa...@linux.intel.com

This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by: Deepak S deepa...@linux.intel.com
---
  drivers/gpu/drm/i915/i915_reg.h | 2 ++
  drivers/gpu/drm/i915/intel_uncore.c | 8 
  2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
  #define  GTFIFOCTL0x120008
  #defineGT_FIFO_FREE_ENTRIES_MASK  0x7f
  #defineGT_FIFO_NUM_RESERVED_ENTRIES   20
+#define   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1  12)
+#define   GT_FIFO_CTL_RC6_POLICY_STALL (1  11)
  
  #define  HSW_IDICR0x9008

  #defineIDIHASHMSK(x)  (((x)  0x3f)  16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index d96d15f..26d6dda 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct 
drm_device *dev,
__raw_i915_write32(dev_priv, GTFIFODBG,
   __raw_i915_read32(dev_priv, GTFIFODBG));
  
+	/* WaDisableShadowRegForCpd */

I couldn't find this w/a name anywhere official, but I guess it's fine.
Should be WaDisableShadowRegForCpd:chv though. Otherwise looks good, so

Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com


Thanks Ville for reviewing. I this the WA still not added to the chv list.


+   if (IS_CHERRYVIEW(dev)) {
+   __raw_i915_write32(dev_priv, GTFIFOCTL,
+   __raw_i915_read32(dev_priv, GTFIFOCTL) |
+   
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+   GT_FIFO_CTL_RC6_POLICY_STALL);
+   }
+
intel_uncore_forcewake_reset(dev, restore_forcewake);
  }
  
--

1.9.1


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Re: [Intel-gfx] [PATCH v3] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-15 Thread shuang . he 
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 6201
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  276/276  276/276
ILK -1  302/302  301/302
SNB  318/318  318/318
IVB  341/341  341/341
BYT  287/287  287/287
HSW -1  395/395  394/395
BDW  318/318  318/318
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*ILK  igt@gem_fenced_exec_thrash@no-spare-fences-busy  PASS(2)  
DMESG_WARN(1)PASS(1)
(dmesg patch 
applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...bsd_ring_idle@Hangcheck
 timer elapsed... bsd ring idle
*HSW  igt@gem_pwrite_pread@snooped-pwrite-blt-cpu_mmap-performance  PASS(5) 
 DMESG_WARN(1)PASS(1)
(dmesg patch 
applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck
 timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'
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