Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Add initial gt workarounds
On Fri, 2023-01-06 at 19:33 +, Sripada, Radhakrishna wrote:
Pushed with the nit's fixed. Thanks for the patch and review.
Next time please modify, resend and wait the BAT. We had
seen cases in the past where the modification ended in a bad code
that broken compilation and everyone else.
Small modifications while merging are only acceptable in the commit
messages.
Thanks,
Rodrigo.
- Radhakrishna(RK) Sripada
-Original Message-
From: Intel-gfx
mailto:intel-gfx-boun...@lists.freedesktop.org>>
On Behalf Of Rodrigo
Vivi
Sent: Friday, January 6, 2023 5:04 AM
To: Atwood, Matthew S
mailto:matthew.s.atw...@intel.com>>
Cc: intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org>; De
Marchi, Lucas
mailto:lucas.demar...@intel.com>>
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Add initial gt workarounds
On Thu, Jan 05, 2023 at 03:44:08PM -0800, Matt Atwood wrote:
From: Matt Roper mailto:matthew.d.ro...@intel.com>>
This patch introduces initial gt workarounds for the MTL platform.
v2: drop redundant/stale comments specifying wa platforms affected
(Lucas).
v3: drop additional redundant stale comments (MattR)
Bspec: 66622
Signed-off-by: Matt Roper
mailto:matthew.d.ro...@intel.com>>
Signed-off-by: Matt Atwood
mailto:matthew.s.atw...@intel.com>>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 11 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 115 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 9 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/intel_device_info.c | 6 +
9 files changed, 128 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 99c4b866addd..e3f30bdf7e61 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1494,10 +1494,12 @@ static int __intel_engine_stop_cs(struct
intel_engine_cs *engine,
intel_uncore_write_fw(uncore, mode,
_MASKED_BIT_ENABLE(STOP_RING));
/*
-* Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
+* Wa_22011802037 : Prior to doing a reset, ensure CS is
^ you could've had also removed the extra space
* stopped, set ring stop bit and prefetch disable bit to halt CS
*/
- if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ (GRAPHICS_VER(engine->i915) >= 11 &&
+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
this is getting hard to read, but yeap, this is the only way...
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
mmio_base),
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2daffa7c7dfd..18ffe55282e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2989,10 +2989,12 @@ static void execlists_reset_prepare(struct
intel_engine_cs *engine)
intel_engine_stop_cs(engine);
/*
-* Wa_22011802037:gen11/gen12: In addition to stopping the cs, we
need
+* Wa_22011802037: In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
- if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ (GRAPHICS_VER(engine->i915) >= 11 &&
+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
intel_engine_wait_for_pending_mi_fw(engine);
engine->execlists.reset_ccid = active_ccid(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 41a237509dcf..4127830c33ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -164,8 +164,15 @@ void intel_gt_mcr_init(struct intel_gt *gt)
if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
gt->steering_table[OADDRM] =
xelpmp_oaddrm_steering_table;
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
- fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
-intel_uncore_read(gt->uncore,
XEHP_FUSE4));
+ /* Wa_14016747170 */
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
+
Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Add initial gt workarounds
Pushed with the nit's fixed. Thanks for the patch and review.
- Radhakrishna(RK) Sripada
> -Original Message-
> From: Intel-gfx On Behalf Of Rodrigo
> Vivi
> Sent: Friday, January 6, 2023 5:04 AM
> To: Atwood, Matthew S
> Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
>
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Add initial gt workarounds
>
> On Thu, Jan 05, 2023 at 03:44:08PM -0800, Matt Atwood wrote:
> > From: Matt Roper
> >
> > This patch introduces initial gt workarounds for the MTL platform.
> >
> > v2: drop redundant/stale comments specifying wa platforms affected
> > (Lucas).
> > v3: drop additional redundant stale comments (MattR)
> >
> > Bspec: 66622
> >
> > Signed-off-by: Matt Roper
> > Signed-off-by: Matt Atwood
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
> > .../drm/i915/gt/intel_execlists_submission.c | 6 +-
> > drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 11 +-
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 115 +-
> > drivers/gpu/drm/i915/gt/uc/intel_guc.c| 9 +-
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +-
> > drivers/gpu/drm/i915/i915_drv.h | 4 +
> > drivers/gpu/drm/i915/intel_device_info.c | 6 +
> > 9 files changed, 128 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 99c4b866addd..e3f30bdf7e61 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -1494,10 +1494,12 @@ static int __intel_engine_stop_cs(struct
> intel_engine_cs *engine,
> > intel_uncore_write_fw(uncore, mode,
> _MASKED_BIT_ENABLE(STOP_RING));
> >
> > /*
> > -* Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
> > +* Wa_22011802037 : Prior to doing a reset, ensure CS is
>
> ^ you could've had also removed the extra space
>
> > * stopped, set ring stop bit and prefetch disable bit to halt CS
> > */
> > - if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + (GRAPHICS_VER(engine->i915) >= 11 &&
> > + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>
> this is getting hard to read, but yeap, this is the only way...
>
> > intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine-
> >mmio_base),
> >
> _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index 2daffa7c7dfd..18ffe55282e5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -2989,10 +2989,12 @@ static void execlists_reset_prepare(struct
> intel_engine_cs *engine)
> > intel_engine_stop_cs(engine);
> >
> > /*
> > -* Wa_22011802037:gen11/gen12: In addition to stopping the cs, we
> need
> > +* Wa_22011802037: In addition to stopping the cs, we need
> > * to wait for any pending mi force wakeups
> > */
> > - if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> > + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + (GRAPHICS_VER(engine->i915) >= 11 &&
> > + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> > intel_engine_wait_for_pending_mi_fw(engine);
> >
> > engine->execlists.reset_ccid = active_ccid(engine);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > index 41a237509dcf..4127830c33ca 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > @@ -164,8 +164,15 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> > if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
> > gt->steering_table[OADDRM] =
> xelpmp_oaddrm_steering_table;
> > } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> > - fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
> > -intel_uncore_read(gt->uncore,
> XEHP_FUSE4));
> > + /* Wa_14016747170 */
> > + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > +
Re: [Intel-gfx] [PATCH v3] drm/i915/mtl: Add initial gt workarounds
On Thu, Jan 05, 2023 at 03:44:08PM -0800, Matt Atwood wrote:
> From: Matt Roper
>
> This patch introduces initial gt workarounds for the MTL platform.
>
> v2: drop redundant/stale comments specifying wa platforms affected
> (Lucas).
> v3: drop additional redundant stale comments (MattR)
>
> Bspec: 66622
>
> Signed-off-by: Matt Roper
> Signed-off-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
> .../drm/i915/gt/intel_execlists_submission.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 11 +-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 115 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 9 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 +
> drivers/gpu/drm/i915/intel_device_info.c | 6 +
> 9 files changed, 128 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 99c4b866addd..e3f30bdf7e61 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1494,10 +1494,12 @@ static int __intel_engine_stop_cs(struct
> intel_engine_cs *engine,
> intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
>
> /*
> - * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
> + * Wa_22011802037 : Prior to doing a reset, ensure CS is
^ you could've had also removed the extra space
>* stopped, set ring stop bit and prefetch disable bit to halt CS
>*/
> - if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + (GRAPHICS_VER(engine->i915) >= 11 &&
> + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
this is getting hard to read, but yeap, this is the only way...
> intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
>
> _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 2daffa7c7dfd..18ffe55282e5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2989,10 +2989,12 @@ static void execlists_reset_prepare(struct
> intel_engine_cs *engine)
> intel_engine_stop_cs(engine);
>
> /*
> - * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
> + * Wa_22011802037: In addition to stopping the cs, we need
>* to wait for any pending mi force wakeups
>*/
> - if (IS_GRAPHICS_VER(engine->i915, 11, 12))
> + if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + (GRAPHICS_VER(engine->i915) >= 11 &&
> + GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
> intel_engine_wait_for_pending_mi_fw(engine);
>
> engine->execlists.reset_ccid = active_ccid(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 41a237509dcf..4127830c33ca 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -164,8 +164,15 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
> gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> - fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
> - intel_uncore_read(gt->uncore, XEHP_FUSE4));
> + /* Wa_14016747170 */
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> + intel_uncore_read(gt->uncore,
> +
> MTL_GT_ACTIVITY_FACTOR));
> + else
> + fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
> + intel_uncore_read(gt->uncore,
> XEHP_FUSE4));
>
> /*
>* Despite the register field being named "exclude mask" the
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index f8eb807b56f9..8ad084bd35d5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -414,6 +414,7 @@
> #define TBIMR_FAST_CLIPREG_BIT(5)
>
> #define VFLSKPD MCR_REG(0x62a8)
> +#define VF_PREFETCH_TLB_DISREG_BIT(5)
> #define
[Intel-gfx] [PATCH v3] drm/i915/mtl: Add initial gt workarounds
From: Matt Roper
This patch introduces initial gt workarounds for the MTL platform.
v2: drop redundant/stale comments specifying wa platforms affected
(Lucas).
v3: drop additional redundant stale comments (MattR)
Bspec: 66622
Signed-off-by: Matt Roper
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 11 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 115 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 9 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/intel_device_info.c | 6 +
9 files changed, 128 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 99c4b866addd..e3f30bdf7e61 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1494,10 +1494,12 @@ static int __intel_engine_stop_cs(struct
intel_engine_cs *engine,
intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
/*
-* Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
+* Wa_22011802037 : Prior to doing a reset, ensure CS is
* stopped, set ring stop bit and prefetch disable bit to halt CS
*/
- if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ (GRAPHICS_VER(engine->i915) >= 11 &&
+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2daffa7c7dfd..18ffe55282e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2989,10 +2989,12 @@ static void execlists_reset_prepare(struct
intel_engine_cs *engine)
intel_engine_stop_cs(engine);
/*
-* Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need
+* Wa_22011802037: In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
- if (IS_GRAPHICS_VER(engine->i915, 11, 12))
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ (GRAPHICS_VER(engine->i915) >= 11 &&
+ GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
intel_engine_wait_for_pending_mi_fw(engine);
engine->execlists.reset_ccid = active_ccid(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 41a237509dcf..4127830c33ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -164,8 +164,15 @@ void intel_gt_mcr_init(struct intel_gt *gt)
if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
- fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
-intel_uncore_read(gt->uncore, XEHP_FUSE4));
+ /* Wa_14016747170 */
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
+intel_uncore_read(gt->uncore,
+
MTL_GT_ACTIVITY_FACTOR));
+ else
+ fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
+intel_uncore_read(gt->uncore,
XEHP_FUSE4));
/*
* Despite the register field being named "exclude mask" the
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f8eb807b56f9..8ad084bd35d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -414,6 +414,7 @@
#define TBIMR_FAST_CLIP REG_BIT(5)
#define VFLSKPDMCR_REG(0x62a8)
+#define VF_PREFETCH_TLB_DIS REG_BIT(5)
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
@@ -1535,6 +1536,10 @@
#define MTL_MEDIA_MC6 _MMIO(0x138048)
+/* Wa_14016747170 */
+#define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010)
+#define MTL_GT_L3_EXC_MASK
