Re: [Intel-gfx] [PATCH v3 08/14] drm/i915: Define MCR registers explicitly
On 14.10.2022 16:02, Matt Roper wrote: > Rather than using the same _MMIO() macro to define MCR registers as > singleton registers, let's use a new MCR_REG() macro to make it clear > that these registers are special and should be handled accordingly. For > now MCR_REG() will still generate an i915_reg_t with the given offset, > but we'll change that in future patches. > > Bspec: 66673, 66696, 66534, 67609 > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 134 > 1 file changed, 68 insertions(+), 66 deletions(-) Reviewed-by: Balasubramani Vivekanandan Regards, Bala > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 890960b56b9e..ad9985015b0e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -8,6 +8,8 @@ > > #include "i915_reg_defs.h" > > +#define MCR_REG(offset) _MMIO(offset) > + > /* RPM unit config (Gen8+) */ > #define RPM_CONFIG0 _MMIO(0xd00) > #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 > @@ -333,12 +335,12 @@ > #define GEN7_TLB_RD_ADDR _MMIO(0x4700) > > #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) > * 4) > -#define XEHP_PAT_INDEX(index)_MMIO(0x4800 + (index) > * 4) > +#define XEHP_PAT_INDEX(index)MCR_REG(0x4800 + > (index) * 4) > > -#define XEHP_TILE0_ADDR_RANGE_MMIO(0x4900) > +#define XEHP_TILE0_ADDR_RANGEMCR_REG(0x4900) > #define XEHP_TILE_LMEM_RANGE_SHIFT 8 > > -#define XEHP_FLAT_CCS_BASE_ADDR _MMIO(0x4910) > +#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910) > #define XEHP_CCS_BASE_SHIFT8 > > #define GAMTARBMODE _MMIO(0x4a08) > @@ -388,18 +390,18 @@ > #define CHICKEN_RASTER_2 _MMIO(0x6208) > #define TBIMR_FAST_CLIPREG_BIT(5) > > -#define VFLSKPD _MMIO(0x62a8) > +#define VFLSKPD MCR_REG(0x62a8) > #define DIS_OVER_FETCH_CACHE REG_BIT(1) > #define DIS_MULT_MISS_RD_SQUASHREG_BIT(0) > > #define GEN12_FF_MODE2 _MMIO(0x6604) > -#define XEHP_FF_MODE2_MMIO(0x6604) > +#define XEHP_FF_MODE2MCR_REG(0x6604) > #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) > #define FF_MODE2_GS_TIMER_224 > REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) > #define FF_MODE2_TDS_TIMER_MASKREG_GENMASK(23, 16) > #define FF_MODE2_TDS_TIMER_128 > REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) > > -#define XEHPG_INSTDONE_GEOM_SVG _MMIO(0x666c) > +#define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c) > > #define CACHE_MODE_0_GEN7_MMIO(0x7000) /* IVB+ */ > #define RC_OP_FLUSH_ENABLE (1 << 0) > @@ -448,14 +450,14 @@ > #define GEN8_HDC_CHICKEN1_MMIO(0x7304) > > #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) > -#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) > +#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304) > #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) > #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) > #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) > #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) > > #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) > -#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) > +#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c) > #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) > #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) > > @@ -486,7 +488,7 @@ > > #define GEN8_RC6_CTX_INFO_MMIO(0x8504) > > -#define XEHP_SQCM_MMIO(0x8724) > +#define XEHP_SQCMMCR_REG(0x8724) > #define EN_32B_ACCESS REG_BIT(30) > > #define HSW_IDICR_MMIO(0x9008) > @@ -647,7 +649,7 @@ > #define GEN7_MISCCPCTL _MMIO(0x9424) > #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) > > -#define GEN8_MISCCPCTL _MMIO(0x9424) > +#define GEN8_MISCCPCTL MCR_REG(0x9424) > #define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0) > #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) > #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) > @@ -703,7 +705,7 @@ > #define LTCDD_CLKGATE_DIS REG_BIT(10) > > #define
[Intel-gfx] [PATCH v3 08/14] drm/i915: Define MCR registers explicitly
Rather than using the same _MMIO() macro to define MCR registers as singleton registers, let's use a new MCR_REG() macro to make it clear that these registers are special and should be handled accordingly. For now MCR_REG() will still generate an i915_reg_t with the given offset, but we'll change that in future patches. Bspec: 66673, 66696, 66534, 67609 Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 134 1 file changed, 68 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 890960b56b9e..ad9985015b0e 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -8,6 +8,8 @@ #include "i915_reg_defs.h" +#define MCR_REG(offset)_MMIO(offset) + /* RPM unit config (Gen8+) */ #define RPM_CONFIG0_MMIO(0xd00) #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT3 @@ -333,12 +335,12 @@ #define GEN7_TLB_RD_ADDR _MMIO(0x4700) #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) -#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) +#define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4) -#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900) +#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900) #define XEHP_TILE_LMEM_RANGE_SHIFT 8 -#define XEHP_FLAT_CCS_BASE_ADDR_MMIO(0x4910) +#define XEHP_FLAT_CCS_BASE_ADDRMCR_REG(0x4910) #define XEHP_CCS_BASE_SHIFT 8 #define GAMTARBMODE_MMIO(0x4a08) @@ -388,18 +390,18 @@ #define CHICKEN_RASTER_2 _MMIO(0x6208) #define TBIMR_FAST_CLIP REG_BIT(5) -#define VFLSKPD_MMIO(0x62a8) +#define VFLSKPDMCR_REG(0x62a8) #define DIS_OVER_FETCH_CACHE REG_BIT(1) #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) #define GEN12_FF_MODE2 _MMIO(0x6604) -#define XEHP_FF_MODE2 _MMIO(0x6604) +#define XEHP_FF_MODE2 MCR_REG(0x6604) #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) -#define XEHPG_INSTDONE_GEOM_SVG_MMIO(0x666c) +#define XEHPG_INSTDONE_GEOM_SVGMCR_REG(0x666c) #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ #define RC_OP_FLUSH_ENABLE (1 << 0) @@ -448,14 +450,14 @@ #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) #define GEN11_COMMON_SLICE_CHICKEN3_MMIO(0x7304) -#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) +#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304) #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLEREG_BIT(12) #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) -#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) +#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c) #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) @@ -486,7 +488,7 @@ #define GEN8_RC6_CTX_INFO _MMIO(0x8504) -#define XEHP_SQCM _MMIO(0x8724) +#define XEHP_SQCM MCR_REG(0x8724) #define EN_32B_ACCESSREG_BIT(30) #define HSW_IDICR _MMIO(0x9008) @@ -647,7 +649,7 @@ #define GEN7_MISCCPCTL _MMIO(0x9424) #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) -#define GEN8_MISCCPCTL _MMIO(0x9424) +#define GEN8_MISCCPCTL MCR_REG(0x9424) #define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0) #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) @@ -703,7 +705,7 @@ #define LTCDD_CLKGATE_DISREG_BIT(10) #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) -#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) +#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4) #define SARBUNIT_CLKGATE_DIS (1 << 5) #define RCCUNIT_CLKGATE_DIS (1 << 7) #define MSCUNIT_CLKGATE_DIS (1 << 10)
