Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: provide interface for audio driver to query cdclk

2014-07-04 Thread Takashi Iwai 
At Fri,  4 Jul 2014 10:00:37 +0800,
mengdong@intel.com wrote:
 
 From: Jani Nikula jani.nik...@intel.com
 
 For Haswell and Broadwell, if the display power well has been disabled,
 the display audio controller divider values EM4 M VALUE and EM5 N VALUE
 will have been lost. The CDCLK frequency is required for reprogramming them
 to generate 24MHz HD-A link BCLK. So provide a private interface for the
 audio driver to query CDCLK.
 
 This is a stopgap solution until a more generic interface between audio
 and display drivers has been implemented.
 
 Signed-off-by: Jani Nikula jani.nik...@intel.com
 Reviewed-by: Damien Lespiau damien.lesp...@intel.com
 Signed-off-by: Mengdong Lin mengdong@intel.com

Thanks, applied (with Cc to stable).


Takashi

 
 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
 index a90fdbd..21170e5 100644
 --- a/drivers/gpu/drm/i915/intel_pm.c
 +++ b/drivers/gpu/drm/i915/intel_pm.c
 @@ -6256,6 +6256,27 @@ int i915_release_power_well(void)
  }
  EXPORT_SYMBOL_GPL(i915_release_power_well);
  
 +/*
 + * Private interface for the audio driver to get CDCLK in kHz.
 + *
 + * Caller must request power well using i915_request_power_well() prior to
 + * making the call.
 + */
 +int i915_get_cdclk_freq(void)
 +{
 + struct drm_i915_private *dev_priv;
 +
 + if (!hsw_pwr)
 + return -ENODEV;
 +
 + dev_priv = container_of(hsw_pwr, struct drm_i915_private,
 + power_domains);
 +
 + return intel_ddi_get_cdclk_freq(dev_priv);
 +}
 +EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
 +
 +
  #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
  
  #define HSW_ALWAYS_ON_POWER_DOMAINS (\
 diff --git a/include/drm/i915_powerwell.h b/include/drm/i915_powerwell.h
 index 2baba99..baa6f11 100644
 --- a/include/drm/i915_powerwell.h
 +++ b/include/drm/i915_powerwell.h
 @@ -32,5 +32,6 @@
  /* For use by hda_i915 driver */
  extern int i915_request_power_well(void);
  extern int i915_release_power_well(void);
 +extern int i915_get_cdclk_freq(void);
  
  #endif   /* _I915_POWERWELL_H_ */
 -- 
 1.8.1.2
 
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[Intel-gfx] [PATCH v3 1/2] drm/i915: provide interface for audio driver to query cdclk

2014-07-03 Thread mengdong . lin 
From: Jani Nikula jani.nik...@intel.com

For Haswell and Broadwell, if the display power well has been disabled,
the display audio controller divider values EM4 M VALUE and EM5 N VALUE
will have been lost. The CDCLK frequency is required for reprogramming them
to generate 24MHz HD-A link BCLK. So provide a private interface for the
audio driver to query CDCLK.

This is a stopgap solution until a more generic interface between audio
and display drivers has been implemented.

Signed-off-by: Jani Nikula jani.nik...@intel.com
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Mengdong Lin mengdong@intel.com

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a90fdbd..21170e5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6256,6 +6256,27 @@ int i915_release_power_well(void)
 }
 EXPORT_SYMBOL_GPL(i915_release_power_well);
 
+/*
+ * Private interface for the audio driver to get CDCLK in kHz.
+ *
+ * Caller must request power well using i915_request_power_well() prior to
+ * making the call.
+ */
+int i915_get_cdclk_freq(void)
+{
+   struct drm_i915_private *dev_priv;
+
+   if (!hsw_pwr)
+   return -ENODEV;
+
+   dev_priv = container_of(hsw_pwr, struct drm_i915_private,
+   power_domains);
+
+   return intel_ddi_get_cdclk_freq(dev_priv);
+}
+EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
+
+
 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 
 #define HSW_ALWAYS_ON_POWER_DOMAINS (  \
diff --git a/include/drm/i915_powerwell.h b/include/drm/i915_powerwell.h
index 2baba99..baa6f11 100644
--- a/include/drm/i915_powerwell.h
+++ b/include/drm/i915_powerwell.h
@@ -32,5 +32,6 @@
 /* For use by hda_i915 driver */
 extern int i915_request_power_well(void);
 extern int i915_release_power_well(void);
+extern int i915_get_cdclk_freq(void);
 
 #endif /* _I915_POWERWELL_H_ */
-- 
1.8.1.2

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