Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
Hi Matt,
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, October 4, 2019 4:53 PM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> ; Syrjala, Ville ;
> Sharma, Shashank ; Antognolli, Rafael
> ; Chery, Nanley G
> Subject: Re: [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL
> Render Decompression
>
> On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > Render Decompression is supported with Y-Tiled main surface. The CCS
> > is linear and has 4 bits of data for each main surface cache line
> > pair, a ratio of 1:256. Additional Clear Color information is passed
> > from the user-space through an offset in the GEM BO. Add a new
> > modifier to identify and parse new Clear Color information and extend
> > Gen12 render decompression functionality to the newly added modifier.
> >
> > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> > plane config(Matt). Fix Lookup error.
> > v3: Fix the panic while running kms_cube
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Ville Syrjala
> > Cc: Shashank Sharma
> > Cc: Rafael Antognolli
> > Cc: Matt Roper
> > Cc: Nanley G Chery
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 52 +++
> > .../drm/i915/display/intel_display_types.h| 3 ++
> > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> > drivers/gpu/drm/i915/i915_reg.h | 12 +
> > 4 files changed, 77 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4971c296f951..822237e98f00 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int color_plane)
> > if (color_plane == 1)
> > return 64;
> > /* fall through */
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + if (color_plane == 1 || color_plane == 2)
> > + return 64;
> > + /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > if (IS_GEN(dev_priv, 2) ||
> HAS_128_BYTE_Y_TILING(dev_priv))
> > return 128;
> > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const
> struct drm_framebuffer *fb,
> > return 256 * 1024;
> > return 0;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return 16 * 1024;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
> color_plane)
> > return true;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > return color_plane == 1;
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + return color_plane == 1 || color_plane == 2;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > return color_plane == 1 || color_plane == 3;
> > default:
> > @@ -2458,6 +2465,7 @@ static unsigned int
> intel_fb_modifier_to_tiling(u64 fb_modifier)
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return I915_TILING_Y;
> > default:
> > return I915_TILING_NONE;
> > @@ -2511,6 +2519,25 @@ static const struct drm_format_info
> gen12_ccs_formats[] = {
> > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true }, };
> >
> > +/*
> > + * Gen-12 compression uses 4 bits of CCS data for each cache line
> > +pair in the
> > + * main surface. And each 64B CCS cache line represents an area of
> > +4x1 Y-tiles
> > + * in the main surface. With 4 byte pixels and each Y-tile having
> > +dimensions of
> > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x
> > +32 pixels in
> > + * the main surface. Additional surface is used to pass the Clear
> > +Color
> > + * structure for the driver to program the DE.
> > + */
>
> Rather than duplicating the previous comment's text I'd just say
>
> "Same as gen12_ccs_formats[] above, but with an additional surface used to
> pass..."
Sure will update that in the next rev.
>
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > + { .format =
Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
On Fri, Oct 04, 2019 at 05:17:07PM -0700, Dhinakaran Pandiyan wrote:
> On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote:
> > On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > > Render Decompression is supported with Y-Tiled main surface. The CCS is
> > > linear and has 4 bits of data for each main surface cache line pair, a
> > > ratio of 1:256. Additional Clear Color information is passed from the
> > > user-space through an offset in the GEM BO. Add a new modifier to identify
> > > and parse new Clear Color information and extend Gen12 render
> > > decompression
> > > functionality to the newly added modifier.
> > >
> > > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> > > plane config(Matt). Fix Lookup error.
> > > v3: Fix the panic while running kms_cube
> > >
> > > Cc: Dhinakaran Pandiyan
> > > Cc: Ville Syrjala
> > > Cc: Shashank Sharma
> > > Cc: Rafael Antognolli
> > > Cc: Matt Roper
> > > Cc: Nanley G Chery
> > > Signed-off-by: Radhakrishna Sripada
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 52 +++
> > > .../drm/i915/display/intel_display_types.h| 3 ++
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> > > drivers/gpu/drm/i915/i915_reg.h | 12 +
> > > 4 files changed, 77 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 4971c296f951..822237e98f00 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct
> > > drm_framebuffer *fb, int color_plane)
> > > if (color_plane == 1)
> > > return 64;
> > > /* fall through */
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > + if (color_plane == 1 || color_plane == 2)
> > > + return 64;
> > > + /* fall through */
> > > case I915_FORMAT_MOD_Y_TILED:
> > > if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> > > return 128;
> > > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const
> > > struct drm_framebuffer *fb,
> > > return 256 * 1024;
> > > return 0;
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return 16 * 1024;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
> > > color_plane)
> > > return true;
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > return color_plane == 1;
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > + return color_plane == 1 || color_plane == 2;
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > return color_plane == 1 || color_plane == 3;
> > > default:
> > > @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> > > fb_modifier)
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return I915_TILING_Y;
> > > default:
> > > return I915_TILING_NONE;
> > > @@ -2511,6 +2519,25 @@ static const struct drm_format_info
> > > gen12_ccs_formats[] = {
> > > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> > > };
> > >
> > > +/*
> > > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair
> > > in the
> > > + * main surface. And each 64B CCS cache line represents an area of 4x1
> > > Y-tiles
> > > + * in the main surface. With 4 byte pixels and each Y-tile having
> > > dimensions of
> > > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> > > pixels in
> > > + * the main surface. Additional surface is used to pass the Clear Color
> > > + * structure for the driver to program the DE.
> > > + */
> >
> > Rather than duplicating the previous comment's text I'd just say
> >
> > "Same as gen12_ccs_formats[] above, but with an additional surface used
> > to pass..."
> >
> > > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > > + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
> > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > > + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
> > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > > + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
> > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > > + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
> > > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > > +};
> > > +
> > >
Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
On Fri, 2019-10-04 at 16:52 -0700, Matt Roper wrote:
> On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> > Render Decompression is supported with Y-Tiled main surface. The CCS is
> > linear and has 4 bits of data for each main surface cache line pair, a
> > ratio of 1:256. Additional Clear Color information is passed from the
> > user-space through an offset in the GEM BO. Add a new modifier to identify
> > and parse new Clear Color information and extend Gen12 render decompression
> > functionality to the newly added modifier.
> >
> > v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> > plane config(Matt). Fix Lookup error.
> > v3: Fix the panic while running kms_cube
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Ville Syrjala
> > Cc: Shashank Sharma
> > Cc: Rafael Antognolli
> > Cc: Matt Roper
> > Cc: Nanley G Chery
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 52 +++
> > .../drm/i915/display/intel_display_types.h| 3 ++
> > drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> > drivers/gpu/drm/i915/i915_reg.h | 12 +
> > 4 files changed, 77 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4971c296f951..822237e98f00 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer
> > *fb, int color_plane)
> > if (color_plane == 1)
> > return 64;
> > /* fall through */
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + if (color_plane == 1 || color_plane == 2)
> > + return 64;
> > + /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> > return 128;
> > @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct
> > drm_framebuffer *fb,
> > return 256 * 1024;
> > return 0;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return 16 * 1024;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
> > color_plane)
> > return true;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > return color_plane == 1;
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > + return color_plane == 1 || color_plane == 2;
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > return color_plane == 1 || color_plane == 3;
> > default:
> > @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> > fb_modifier)
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return I915_TILING_Y;
> > default:
> > return I915_TILING_NONE;
> > @@ -2511,6 +2519,25 @@ static const struct drm_format_info
> > gen12_ccs_formats[] = {
> > .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> > };
> >
> > +/*
> > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in
> > the
> > + * main surface. And each 64B CCS cache line represents an area of 4x1
> > Y-tiles
> > + * in the main surface. With 4 byte pixels and each Y-tile having
> > dimensions of
> > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> > pixels in
> > + * the main surface. Additional surface is used to pass the Clear Color
> > + * structure for the driver to program the DE.
> > + */
>
> Rather than duplicating the previous comment's text I'd just say
>
> "Same as gen12_ccs_formats[] above, but with an additional surface used
> to pass..."
>
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> > + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
> > + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> > +};
> > +
> > static const struct drm_format_info *
> > lookup_format_info(const struct drm_format_info formats[],
> >int num_formats, u32 format)
> > @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct
Re: [Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
On Fri, Sep 27, 2019 at 03:28:37PM -0700, Radhakrishna Sripada wrote:
> Render Decompression is supported with Y-Tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Additional Clear Color information is passed from the
> user-space through an offset in the GEM BO. Add a new modifier to identify
> and parse new Clear Color information and extend Gen12 render decompression
> functionality to the newly added modifier.
>
> v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
> plane config(Matt). Fix Lookup error.
> v3: Fix the panic while running kms_cube
>
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjala
> Cc: Shashank Sharma
> Cc: Rafael Antognolli
> Cc: Matt Roper
> Cc: Nanley G Chery
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 52 +++
> .../drm/i915/display/intel_display_types.h| 3 ++
> drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
> drivers/gpu/drm/i915/i915_reg.h | 12 +
> 4 files changed, 77 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4971c296f951..822237e98f00 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer
> *fb, int color_plane)
> if (color_plane == 1)
> return 64;
> /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + if (color_plane == 1 || color_plane == 2)
> + return 64;
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> @@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> return 256 * 1024;
> return 0;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return 16 * 1024;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
> color_plane)
> return true;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return color_plane == 1;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + return color_plane == 1 || color_plane == 2;
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return color_plane == 1 || color_plane == 3;
> default:
> @@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> fb_modifier)
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return I915_TILING_Y;
> default:
> return I915_TILING_NONE;
> @@ -2511,6 +2519,25 @@ static const struct drm_format_info
> gen12_ccs_formats[] = {
> .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
> };
>
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1
> Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having dimensions
> of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32
> pixels in
> + * the main surface. Additional surface is used to pass the Clear Color
> + * structure for the driver to program the DE.
> + */
Rather than duplicating the previous comment's text I'd just say
"Same as gen12_ccs_formats[] above, but with an additional surface used
to pass..."
> +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
> + .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +};
> +
> static const struct drm_format_info *
> lookup_format_info(const struct drm_format_info formats[],
> int num_formats, u32 format)
> @@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2
> *cmd)
> return lookup_format_info(gen12_ccs_formats,
> ARRAY_SIZE(gen12_ccs_formats),
>
[Intel-gfx] [PATCH v3 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjala
Cc: Shashank Sharma
Cc: Rafael Antognolli
Cc: Matt Roper
Cc: Nanley G Chery
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++
.../drm/i915/display/intel_display_types.h| 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4971c296f951..822237e98f00 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1919,6 +1919,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2060,6 +2064,7 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2265,6 +2270,8 @@ static bool is_surface_linear(u64 modifier, int
color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2458,6 +2465,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2511,6 +2519,25 @@ static const struct drm_format_info gen12_ccs_formats[]
= {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels
in
+ * the main surface. Additional surface is used to pass the Clear Color
+ * structure for the driver to program the DE.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2538,6 +2565,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
