Re: [Intel-gfx] [PATCH v3 11/14] drm/i915/gt: Add MCR-specific workaround initializers

2022-10-17 Thread Balasubramani Vivekanandan 
On 14.10.2022 16:02, Matt Roper wrote:
> Let's be more explicit about which of our workarounds are updating MCR
> registers.
> 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 433 +++---
>  .../gpu/drm/i915/gt/intel_workarounds_types.h |   4 +-
>  2 files changed, 263 insertions(+), 174 deletions(-)

Reviewed-by: Balasubramani Vivekanandan 

Regards,
Bala
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 96b9f02a2284..7671994d5b7a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -166,12 +166,33 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t 
> reg,
>   _wa_add(wal, );
>  }
>  
> +static void wa_mcr_add(struct i915_wa_list *wal, i915_reg_t reg,
> +u32 clear, u32 set, u32 read_mask, bool masked_reg)
> +{
> + struct i915_wa wa = {
> + .reg  = reg,
> + .clr  = clear,
> + .set  = set,
> + .read = read_mask,
> + .masked_reg = masked_reg,
> + .is_mcr = 1,
> + };
> +
> + _wa_add(wal, );
> +}
> +
>  static void
>  wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 
> set)
>  {
>   wa_add(wal, reg, clear, set, clear, false);
>  }
>  
> +static void
> +wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, 
> u32 set)
> +{
> + wa_mcr_add(wal, reg, clear, set, clear, false);
> +}
> +
>  static void
>  wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
>  {
> @@ -184,12 +205,24 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, 
> u32 set)
>   wa_write_clr_set(wal, reg, set, set);
>  }
>  
> +static void
> +wa_mcr_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
> +{
> + wa_mcr_write_clr_set(wal, reg, set, set);
> +}
> +
>  static void
>  wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
>  {
>   wa_write_clr_set(wal, reg, clr, 0);
>  }
>  
> +static void
> +wa_mcr_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
> +{
> + wa_mcr_write_clr_set(wal, reg, clr, 0);
> +}
> +
>  /*
>   * WA operations on "masked register". A masked register has the upper 16 
> bits
>   * documented as "masked" in b-spec. Its purpose is to allow writing to just 
> a
> @@ -207,12 +240,24 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, 
> u32 val)
>   wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
>  }
>  
> +static void
> +wa_mcr_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> +{
> + wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
> +}
> +
>  static void
>  wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>  {
>   wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
>  }
>  
> +static void
> +wa_mcr_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> +{
> + wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
> +}
> +
>  static void
>  wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
>   u32 mask, u32 val)
> @@ -220,6 +265,13 @@ wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t 
> reg,
>   wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
>  }
>  
> +static void
> +wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
> + u32 mask, u32 val)
> +{
> + wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
> +}
> +
>  static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
>  {
> @@ -241,8 +293,8 @@ static void gen8_ctx_workarounds_init(struct 
> intel_engine_cs *engine,
>   wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), 
> ASYNC_FLIP_PERF_DISABLE);
>  
>   /* WaDisablePartialInstShootdown:bdw,chv */
> - wa_masked_en(wal, GEN8_ROW_CHICKEN,
> -  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
> + wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
> +  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>  
>   /* Use Force Non-Coherent whenever executing a 3D context. This is a
>* workaround for a possible hang in the unlikely event a TLB
> @@ -288,18 +340,18 @@ static void bdw_ctx_workarounds_init(struct 
> intel_engine_cs *engine,
>   gen8_ctx_workarounds_init(engine, wal);
>  
>   /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
> - wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
> + wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
>  
>   /* WaDisableDopClockGating:bdw
>*
>* Also see the related UCGTCL1 write in bdw_init_clock_gating()
>* to disable EUTC clock gating.
>*/
> - wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> -  DOP_CLOCK_GATING_DISABLE);
> + wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> +

[Intel-gfx] [PATCH v3 11/14] drm/i915/gt: Add MCR-specific workaround initializers

2022-10-14 Thread Matt Roper 
Let's be more explicit about which of our workarounds are updating MCR
registers.

Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 433 +++---
 .../gpu/drm/i915/gt/intel_workarounds_types.h |   4 +-
 2 files changed, 263 insertions(+), 174 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 96b9f02a2284..7671994d5b7a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -166,12 +166,33 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t 
reg,
_wa_add(wal, );
 }
 
+static void wa_mcr_add(struct i915_wa_list *wal, i915_reg_t reg,
+  u32 clear, u32 set, u32 read_mask, bool masked_reg)
+{
+   struct i915_wa wa = {
+   .reg  = reg,
+   .clr  = clear,
+   .set  = set,
+   .read = read_mask,
+   .masked_reg = masked_reg,
+   .is_mcr = 1,
+   };
+
+   _wa_add(wal, );
+}
+
 static void
 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
 {
wa_add(wal, reg, clear, set, clear, false);
 }
 
+static void
+wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 
set)
+{
+   wa_mcr_add(wal, reg, clear, set, clear, false);
+}
+
 static void
 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 {
@@ -184,12 +205,24 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 
set)
wa_write_clr_set(wal, reg, set, set);
 }
 
+static void
+wa_mcr_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
+{
+   wa_mcr_write_clr_set(wal, reg, set, set);
+}
+
 static void
 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
 {
wa_write_clr_set(wal, reg, clr, 0);
 }
 
+static void
+wa_mcr_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
+{
+   wa_mcr_write_clr_set(wal, reg, clr, 0);
+}
+
 /*
  * WA operations on "masked register". A masked register has the upper 16 bits
  * documented as "masked" in b-spec. Its purpose is to allow writing to just a
@@ -207,12 +240,24 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, 
u32 val)
wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
 }
 
+static void
+wa_mcr_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+   wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
+}
+
 static void
 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
 }
 
+static void
+wa_mcr_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+   wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
+}
+
 static void
 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
u32 mask, u32 val)
@@ -220,6 +265,13 @@ wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t 
reg,
wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
 }
 
+static void
+wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
+   u32 mask, u32 val)
+{
+   wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
+}
+
 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
  struct i915_wa_list *wal)
 {
@@ -241,8 +293,8 @@ static void gen8_ctx_workarounds_init(struct 
intel_engine_cs *engine,
wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), 
ASYNC_FLIP_PERF_DISABLE);
 
/* WaDisablePartialInstShootdown:bdw,chv */
-   wa_masked_en(wal, GEN8_ROW_CHICKEN,
-PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+   wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
+PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
/* Use Force Non-Coherent whenever executing a 3D context. This is a
 * workaround for a possible hang in the unlikely event a TLB
@@ -288,18 +340,18 @@ static void bdw_ctx_workarounds_init(struct 
intel_engine_cs *engine,
gen8_ctx_workarounds_init(engine, wal);
 
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
-   wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
+   wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 
/* WaDisableDopClockGating:bdw
 *
 * Also see the related UCGTCL1 write in bdw_init_clock_gating()
 * to disable EUTC clock gating.
 */
-   wa_masked_en(wal, GEN8_ROW_CHICKEN2,
-DOP_CLOCK_GATING_DISABLE);
+   wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
+DOP_CLOCK_GATING_DISABLE);
 
-   wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
-GEN8_SAMPLER_POWER_BYPASS_DIS);
+   wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
+GEN8_SAMPLER_POWER_BYPASS_DIS);
 
wa_masked_en(wal, HDC_CHICKEN0,