Re: [Intel-gfx] [PATCH v3 18/21] drm/i915: Don't try to place HWS in non-existing mappable region

2019-10-04 Thread Chris Wilson
Quoting Matthew Auld (2019-10-04 18:04:49)
> From: Michal Wajdeczko 
> 
> HWS placement restrictions can't just rely on HAS_LLC flag.
> 
> Signed-off-by: Michal Wajdeczko 
> Signed-off-by: Matthew Auld 
> Cc: Daniele Ceraolo Spurio 
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 80fd072ac719..f6799ef9915a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -513,7 +513,8 @@ static int pin_ggtt_status_page(struct intel_engine_cs 
> *engine,
> unsigned int flags;
>  
> flags = PIN_GLOBAL;
> -   if (!HAS_LLC(engine->i915))
> +   if (!HAS_LLC(engine->i915) &&
> +   i915_ggtt_has_aperture(>i915->ggtt))

engine->gt->ggtt is the preferred abstracted route.
-Chris
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[Intel-gfx] [PATCH v3 18/21] drm/i915: Don't try to place HWS in non-existing mappable region

2019-10-04 Thread Matthew Auld
From: Michal Wajdeczko 

HWS placement restrictions can't just rely on HAS_LLC flag.

Signed-off-by: Michal Wajdeczko 
Signed-off-by: Matthew Auld 
Cc: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 80fd072ac719..f6799ef9915a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -513,7 +513,8 @@ static int pin_ggtt_status_page(struct intel_engine_cs 
*engine,
unsigned int flags;
 
flags = PIN_GLOBAL;
-   if (!HAS_LLC(engine->i915))
+   if (!HAS_LLC(engine->i915) &&
+   i915_ggtt_has_aperture(>i915->ggtt))
/*
 * On g33, we cannot place HWS above 256MiB, so
 * restrict its pinning to the low mappable arena.
-- 
2.20.1

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