Re: [Intel-gfx] [PATCH v3 5/5] drm/i915: Setup static bias for GPU

2015-03-30 Thread Ville Syrjälä 
On Sat, Mar 28, 2015 at 03:23:38PM +0530, deepa...@linux.intel.com wrote:
 From: Deepak S deepa...@linux.intel.com
 
 Based on the spec, Setting up static BIAS for GPU to improve the
 rps performace.

My understanding is that this would only improve the GPU performance
under TDP constrained use cases, at the cost of CPU performance. So
it's not some magic bullet that makes things just faster (tm).

 
 Signed-off-by: Deepak S deepa...@linux.intel.com
 ---
  drivers/gpu/drm/i915/i915_reg.h |  5 +
  drivers/gpu/drm/i915/intel_pm.c | 12 
  2 files changed, 17 insertions(+)
 
 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
 index b522eb6..ea708ba 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -670,6 +670,11 @@ enum skl_disp_power_wells {
  #define   FB_FMAX_VMIN_FREQ_LO_SHIFT 27
  #define   FB_FMAX_VMIN_FREQ_LO_MASK  0xf800
  
 +#define VLV_IOSFB_RPS_OVERRIDE   0x04
 +#define VLV_OVERRIDE_RPS_MASK1
 +#define VLV_ENABLE_BIAS_SHARE(1  1)
 +#define VLV_BIAS_VAL (6  2)

Can we use better names for these (from configdb, say)?

 +
  #define VLV_CZ_CLOCK_TO_MILLI_SEC10
  #define VLV_RP_UP_EI_THRESHOLD   90
  #define VLV_RP_DOWN_EI_THRESHOLD 70
 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
 index 88e71a3..673612b 100644
 --- a/drivers/gpu/drm/i915/intel_pm.c
 +++ b/drivers/gpu/drm/i915/intel_pm.c
 @@ -5015,6 +5015,12 @@ static void cherryview_enable_rps(struct drm_device 
 *dev)
  GEN6_RP_UP_BUSY_AVG |
  GEN6_RP_DOWN_IDLE_AVG);
  
 + /* Setting Fixed Bias */
 + val = VLV_OVERRIDE_RPS_MASK |
 +   VLV_ENABLE_BIAS_SHARE |
 +   VLV_BIAS_VAL;
 + vlv_punit_write(dev_priv, VLV_IOSFB_RPS_OVERRIDE, val);
 +
   val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
  
   /* RPS code assumes GPLL is used */
 @@ -5099,6 +5105,12 @@ static void valleyview_enable_rps(struct drm_device 
 *dev)
  
   I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
  
 + /* Setting Fixed Bias */
 + val = VLV_OVERRIDE_RPS_MASK |
 +   VLV_ENABLE_BIAS_SHARE |
 +   VLV_BIAS_VAL;
 + vlv_punit_write(dev_priv, VLV_IOSFB_RPS_OVERRIDE, val);
 +
   val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
  
   /* RPS code assumes GPLL is used */
 -- 
 1.9.1

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH v3 5/5] drm/i915: Setup static bias for GPU

2015-03-28 Thread shuang . he 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 6085
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV -1  270/270  269/270
ILK  303/303  303/303
SNB  304/304  304/304
IVB  337/337  337/337
BYT  287/287  287/287
HSW  361/361  361/361
BDW  309/309  309/309
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*PNV  igt@gem_tiled_pread_pwrite  PASS(2)  FAIL(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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[Intel-gfx] [PATCH v3 5/5] drm/i915: Setup static bias for GPU

2015-03-28 Thread deepak . s 
From: Deepak S deepa...@linux.intel.com

Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.

Signed-off-by: Deepak S deepa...@linux.intel.com
---
 drivers/gpu/drm/i915/i915_reg.h |  5 +
 drivers/gpu/drm/i915/intel_pm.c | 12 
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b522eb6..ea708ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -670,6 +670,11 @@ enum skl_disp_power_wells {
 #define   FB_FMAX_VMIN_FREQ_LO_SHIFT   27
 #define   FB_FMAX_VMIN_FREQ_LO_MASK0xf800
 
+#define VLV_IOSFB_RPS_OVERRIDE 0x04
+#define VLV_OVERRIDE_RPS_MASK  1
+#define VLV_ENABLE_BIAS_SHARE  (1  1)
+#define VLV_BIAS_VAL   (6  2)
+
 #define VLV_CZ_CLOCK_TO_MILLI_SEC  10
 #define VLV_RP_UP_EI_THRESHOLD 90
 #define VLV_RP_DOWN_EI_THRESHOLD   70
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e71a3..673612b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5015,6 +5015,12 @@ static void cherryview_enable_rps(struct drm_device *dev)
   GEN6_RP_UP_BUSY_AVG |
   GEN6_RP_DOWN_IDLE_AVG);
 
+   /* Setting Fixed Bias */
+   val = VLV_OVERRIDE_RPS_MASK |
+ VLV_ENABLE_BIAS_SHARE |
+ VLV_BIAS_VAL;
+   vlv_punit_write(dev_priv, VLV_IOSFB_RPS_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 
/* RPS code assumes GPLL is used */
@@ -5099,6 +5105,12 @@ static void valleyview_enable_rps(struct drm_device *dev)
 
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
+   /* Setting Fixed Bias */
+   val = VLV_OVERRIDE_RPS_MASK |
+ VLV_ENABLE_BIAS_SHARE |
+ VLV_BIAS_VAL;
+   vlv_punit_write(dev_priv, VLV_IOSFB_RPS_OVERRIDE, val);
+
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 
/* RPS code assumes GPLL is used */
-- 
1.9.1

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