Re: [Intel-gfx] [PATCH v4] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-28 Thread Jani Nikula 
On Thu, 16 Apr 2015, deepa...@linux.intel.com wrote:
 From: Deepak S deepa...@linux.intel.com

 This WA is avoid problem between shadow vs wake FIFO unload
 problem during CPD/RC6 transactions on CHV.

 v2: Define individual bits GTFIFOCTL (Ville)

 v3: move WA to uncore_early_sanitize (ville)

 Signed-off-by: Deepak S deepa...@linux.intel.com
 Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com

Pushed to drm-intel-fixes, thanks for the patch and review.

BR,
Jani.


 ---
  drivers/gpu/drm/i915/i915_reg.h | 2 ++
  drivers/gpu/drm/i915/intel_uncore.c | 8 
  2 files changed, 10 insertions(+)

 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
 index 9c97842..a642a58 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
  #define  GTFIFOCTL   0x120008
  #defineGT_FIFO_FREE_ENTRIES_MASK 0x7f
  #defineGT_FIFO_NUM_RESERVED_ENTRIES  20
 +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1  12)
 +#define GT_FIFO_CTL_RC6_POLICY_STALL (1  11)
  
  #define  HSW_IDICR   0x9008
  #defineIDIHASHMSK(x) (((x)  0x3f)  16)
 diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
 b/drivers/gpu/drm/i915/intel_uncore.c
 index d96d15f..d7cfd0c 100644
 --- a/drivers/gpu/drm/i915/intel_uncore.c
 +++ b/drivers/gpu/drm/i915/intel_uncore.c
 @@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct 
 drm_device *dev,
   __raw_i915_write32(dev_priv, GTFIFODBG,
  __raw_i915_read32(dev_priv, GTFIFODBG));
  
 + /* WaDisableShadowRegForCpd:chv */
 + if (IS_CHERRYVIEW(dev)) {
 + __raw_i915_write32(dev_priv, GTFIFOCTL,
 + __raw_i915_read32(dev_priv, GTFIFOCTL) |
 + 
 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 + GT_FIFO_CTL_RC6_POLICY_STALL);
 + }
 +
   intel_uncore_forcewake_reset(dev, restore_forcewake);
  }
  
 -- 
 1.9.1

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Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH v4] drm/i915/chv: Implement WaDisableShadowRegForCpd

2015-04-15 Thread deepak . s 
From: Deepak S deepa...@linux.intel.com

This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by: Deepak S deepa...@linux.intel.com
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_uncore.c | 8 
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..a642a58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL 0x120008
 #defineGT_FIFO_FREE_ENTRIES_MASK   0x7f
 #defineGT_FIFO_NUM_RESERVED_ENTRIES20
+#define   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1  12)
+#define   GT_FIFO_CTL_RC6_POLICY_STALL (1  11)
 
 #define  HSW_IDICR 0x9008
 #defineIDIHASHMSK(x)   (((x)  0x3f)  16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index d96d15f..d7cfd0c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct 
drm_device *dev,
__raw_i915_write32(dev_priv, GTFIFODBG,
   __raw_i915_read32(dev_priv, GTFIFODBG));
 
+   /* WaDisableShadowRegForCpd:chv */
+   if (IS_CHERRYVIEW(dev)) {
+   __raw_i915_write32(dev_priv, GTFIFOCTL,
+   __raw_i915_read32(dev_priv, GTFIFOCTL) |
+   
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+   GT_FIFO_CTL_RC6_POLICY_STALL);
+   }
+
intel_uncore_forcewake_reset(dev, restore_forcewake);
 }
 
-- 
1.9.1

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