Re: [Intel-gfx] [PATCH v5 2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext'
On Wed, 2014-05-28 at 15:27 +0530, sourab gupta wrote:
On Mon, 2014-04-14 at 09:45 +, Gupta, Sourab wrote:
From: Akash Goel akash.g...@intel.com
This workaround is needed on VLV for the HW context feature.
It is used after adding the mi_set_context command in ring buffer
for Hw context switch. As per the spec
The software must send a pipe_control with a CS stall and a post sync
operation and then a dummy DRAW after every MI_SET_CONTEXT and after any
PIPELINE_SELECT that is enabling 3D mode.
Tested only for vlv.
v2: Modified the WA comment. (Ville)
v3: Added the vlv identifier with the WA name
v4: Check removed for scratch page initialization. (Chris/Daniel)
v5: Refactored based on latest codebase. Also WA added for full Gen7.
Signed-off-by: Sourab Gupta sourab.gu...@intel.com
Signed-off-by: Akash Goel akash.g...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 55
+++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
4 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f77b4c1..b6d2a67 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -545,6 +545,47 @@ i915_gem_context_get(struct drm_i915_file_private
*file_priv, u32 id)
return ctx;
}
+static inline void
+mi_set_context_dummy3d_prim_wa(struct intel_ring_buffer *ring)
+{
+ u32 scratch_addr;
+ u32 flags = 0;
+
+ /* Actual scratch location is at 128 bytes offset */
+ scratch_addr = intel_get_pipe_control_scratch_addr(ring) + 128;
+
+ /*
+* WaSendDummy3dPrimitveAfterSetContext:ivb,vlv
+* Software must send a pipe_control with a CS stall
+* and a post sync operation and then a dummy DRAW after
+* every MI_SET_CONTEXT and after any PIPELINE_SELECT that
+* is enabling 3D mode. A dummy draw is a 3DPRIMITIVE command
+* with Indirect Parameter Enable set to 0, UAV Coherency
+* Required set to 0, Predicate Enable set to 0,
+* End Offset Enable set to 0, and Vertex Count Per Instance
+* set to 0, All other parameters are a don't care.
+*/
+
+ /*
+* Add a pipe control with CS Stall and postsync op
+* before dummy 3D_PRIMITIVE
+*/
+ flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
+ intel_ring_emit(ring, flags);
+ intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(ring, 0);
+
+ /* Add a dummy 3D_PRIMITVE */
+ intel_ring_emit(ring, GFX_OP_3DPRIMITIVE);
+ intel_ring_emit(ring, 4); /* PrimTopoType*/
+ intel_ring_emit(ring, 0); /* VertexCountPerInstance */
+ intel_ring_emit(ring, 0); /* StartVertexLocation */
+ intel_ring_emit(ring, 0); /* InstanceCount */
+ intel_ring_emit(ring, 0); /* StartInstanceLocation */
+ intel_ring_emit(ring, 0); /* BaseVertexLocation */
+}
+
static inline int
mi_set_context(struct intel_ring_buffer *ring,
struct i915_hw_context *new_context,
@@ -563,7 +604,10 @@ mi_set_context(struct intel_ring_buffer *ring,
return ret;
}
- ret = intel_ring_begin(ring, 6);
+ if (INTEL_INFO(ring-dev)-gen == 7)
+ ret = intel_ring_begin(ring, 6+4+8);
+ else
+ ret = intel_ring_begin(ring, 6);
if (ret)
return ret;
@@ -586,8 +630,15 @@ mi_set_context(struct intel_ring_buffer *ring,
*/
intel_ring_emit(ring, MI_NOOP);
+ /* WaSendDummy3dPrimitveAfterSetContext:ivb,vlv */
if (INTEL_INFO(ring-dev)-gen = 7)
- intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+ if (INTEL_INFO(ring-dev)-gen == 7) {
+ mi_set_context_dummy3d_prim_wa(ring);
+ intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+ intel_ring_emit(ring, MI_NOOP);
+ } else
+ intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+
else
intel_ring_emit(ring, MI_NOOP);
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index 8f84555..1128527 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -355,6 +355,7 @@
#define PIPE_CONTROL_STALL_AT_SCOREBOARD (11)
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (10)
#define PIPE_CONTROL_GLOBAL_GTT (12) /* in addr dword */
+#define GFX_OP_3DPRIMITIVE ((0x329)|(0x327)|(0x324)|(7-2))
/*
* Commands used only by the command parser
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index eb3dd26..834411b
[Intel-gfx] [PATCH v5 2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext'
From: Akash Goel akash.g...@intel.com
This workaround is needed on VLV for the HW context feature.
It is used after adding the mi_set_context command in ring buffer
for Hw context switch. As per the spec
The software must send a pipe_control with a CS stall and a post sync
operation and then a dummy DRAW after every MI_SET_CONTEXT and after any
PIPELINE_SELECT that is enabling 3D mode.
Tested only for vlv.
v2: Modified the WA comment. (Ville)
v3: Added the vlv identifier with the WA name
v4: Check removed for scratch page initialization. (Chris/Daniel)
v5: Refactored based on latest codebase. Also WA added for full Gen7.
Signed-off-by: Sourab Gupta sourab.gu...@intel.com
Signed-off-by: Akash Goel akash.g...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 55 +++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
4 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f77b4c1..b6d2a67 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -545,6 +545,47 @@ i915_gem_context_get(struct drm_i915_file_private
*file_priv, u32 id)
return ctx;
}
+static inline void
+mi_set_context_dummy3d_prim_wa(struct intel_ring_buffer *ring)
+{
+ u32 scratch_addr;
+ u32 flags = 0;
+
+ /* Actual scratch location is at 128 bytes offset */
+ scratch_addr = intel_get_pipe_control_scratch_addr(ring) + 128;
+
+ /*
+* WaSendDummy3dPrimitveAfterSetContext:ivb,vlv
+* Software must send a pipe_control with a CS stall
+* and a post sync operation and then a dummy DRAW after
+* every MI_SET_CONTEXT and after any PIPELINE_SELECT that
+* is enabling 3D mode. A dummy draw is a 3DPRIMITIVE command
+* with Indirect Parameter Enable set to 0, UAV Coherency
+* Required set to 0, Predicate Enable set to 0,
+* End Offset Enable set to 0, and Vertex Count Per Instance
+* set to 0, All other parameters are a don't care.
+*/
+
+ /*
+* Add a pipe control with CS Stall and postsync op
+* before dummy 3D_PRIMITIVE
+*/
+ flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
+ intel_ring_emit(ring, flags);
+ intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(ring, 0);
+
+ /* Add a dummy 3D_PRIMITVE */
+ intel_ring_emit(ring, GFX_OP_3DPRIMITIVE);
+ intel_ring_emit(ring, 4); /* PrimTopoType*/
+ intel_ring_emit(ring, 0); /* VertexCountPerInstance */
+ intel_ring_emit(ring, 0); /* StartVertexLocation */
+ intel_ring_emit(ring, 0); /* InstanceCount */
+ intel_ring_emit(ring, 0); /* StartInstanceLocation */
+ intel_ring_emit(ring, 0); /* BaseVertexLocation */
+}
+
static inline int
mi_set_context(struct intel_ring_buffer *ring,
struct i915_hw_context *new_context,
@@ -563,7 +604,10 @@ mi_set_context(struct intel_ring_buffer *ring,
return ret;
}
- ret = intel_ring_begin(ring, 6);
+ if (INTEL_INFO(ring-dev)-gen == 7)
+ ret = intel_ring_begin(ring, 6+4+8);
+ else
+ ret = intel_ring_begin(ring, 6);
if (ret)
return ret;
@@ -586,8 +630,15 @@ mi_set_context(struct intel_ring_buffer *ring,
*/
intel_ring_emit(ring, MI_NOOP);
+ /* WaSendDummy3dPrimitveAfterSetContext:ivb,vlv */
if (INTEL_INFO(ring-dev)-gen = 7)
- intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+ if (INTEL_INFO(ring-dev)-gen == 7) {
+ mi_set_context_dummy3d_prim_wa(ring);
+ intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+ intel_ring_emit(ring, MI_NOOP);
+ } else
+ intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+
else
intel_ring_emit(ring, MI_NOOP);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f84555..1128527 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -355,6 +355,7 @@
#define PIPE_CONTROL_STALL_AT_SCOREBOARD (11)
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (10)
#define PIPE_CONTROL_GLOBAL_GTT (12) /* in addr dword */
+#define GFX_OP_3DPRIMITIVE ((0x329)|(0x327)|(0x324)|(7-2))
/*
* Commands used only by the command parser
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index eb3dd26..834411b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -585,6 +585,15 @@ err:
return
