Re: [Intel-gfx] [PATCH v5 4/8] drm/i915/pxp: Add GSC-CS backend to send GSC fw messages

2023-02-15 Thread Teres Alexis, Alan Previn
On Tue, 2023-02-14 at 13:38 -0800, Teres Alexis, Alan Previn wrote:
alan:snip
> +static int gsccs_send_message(struct intel_pxp *pxp,
> +   void *msg_in, size_t msg_in_size,
> +   void *msg_out, size_t msg_out_size_max,
> +   size_t *msg_out_len,
> +   u64 *gsc_msg_handle_retry)
> +{
> + struct intel_gt *gt = pxp->ctrl_gt;
> + struct drm_i915_private *i915 = gt->i915;
> + struct gsccs_session_resources *exec =  >gsccs_res;
> + struct intel_gsc_mtl_header *header = exec->pkt_vaddr;
> + struct intel_gsc_heci_non_priv_pkt pkt;
> + bool null_pkt = !msg_in && !msg_out;
> + size_t max_msg_size;
> + u32 reply_size;
> + int ret;
> +
> + if (!exec->ce)
> + return -ENODEV;
> +
> + max_msg_size = PXP43_MAX_HECI_IN_SIZE - sizeof(*header);
> +
> + if (msg_in_size > max_msg_size || msg_out_size_max > max_msg_size)
> + return -ENOSPC;
> +
> + mutex_lock(>tee_mutex);
> +
> + if (!exec->pkt_vma || !exec->bb_vma)
> + return -ENOENT;
> +
alan: nack - i need to move the tee_mutex to after this pkt_vma / bb_bma checks


[Intel-gfx] [PATCH v5 4/8] drm/i915/pxp: Add GSC-CS backend to send GSC fw messages

2023-02-14 Thread Alan Previn
Add GSC engine based method for sending PXP firmware packets
to the GSC firmware for MTL (and future) products.

Use the newly added helpers to populate the GSC-CS memory
header and send the message packet to the FW by dispatching
the GSC_HECI_CMD_PKT instruction on the GSC engine.

We use non-priveleged batches for submission to GSC engine
and require two buffers for the request:
 - a buffer for the HECI packet that contains PXP FW commands
 - a batch-buffer that contains the engine instruction for
   sending the HECI packet to the GSC firmware.

Thus, add the allocation and freeing of these buffers in gsccs
init and fini.

Signed-off-by: Alan Previn 
---
 .../drm/i915/pxp/intel_pxp_cmd_interface_43.h |   4 +
 drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c| 224 +-
 drivers/gpu/drm/i915/pxp/intel_pxp_types.h|   6 +
 3 files changed, 232 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h 
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
index ad67e3f49c20..b2523d6918c7 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h
@@ -12,6 +12,10 @@
 /* PXP-Cmd-Op definitions */
 #define PXP43_CMDID_START_HUC_AUTH 0x003A
 
+/* PXP-Packet sizes for MTL's GSCCS-HECI instruction */
+#define PXP43_MAX_HECI_IN_SIZE (SZ_32K)
+#define PXP43_MAX_HECI_OUT_SIZE (SZ_32K)
+
 /* PXP-Input-Packet: HUC-Authentication */
 struct pxp43_start_huc_auth_in {
struct pxp_cmd_header header;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c 
b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
index 13693e78b57e..3cd28db830c1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
@@ -6,19 +6,211 @@
 #include "gem/i915_gem_internal.h"
 
 #include "gt/intel_context.h"
+#include "gt/uc/intel_gsc_uc_heci_cmd_submit.h"
 
 #include "i915_drv.h"
 #include "intel_pxp_cmd_interface_43.h"
 #include "intel_pxp_gsccs.h"
 #include "intel_pxp_types.h"
 
+static int gsccs_send_message(struct intel_pxp *pxp,
+ void *msg_in, size_t msg_in_size,
+ void *msg_out, size_t msg_out_size_max,
+ size_t *msg_out_len,
+ u64 *gsc_msg_handle_retry)
+{
+   struct intel_gt *gt = pxp->ctrl_gt;
+   struct drm_i915_private *i915 = gt->i915;
+   struct gsccs_session_resources *exec =  >gsccs_res;
+   struct intel_gsc_mtl_header *header = exec->pkt_vaddr;
+   struct intel_gsc_heci_non_priv_pkt pkt;
+   bool null_pkt = !msg_in && !msg_out;
+   size_t max_msg_size;
+   u32 reply_size;
+   int ret;
+
+   if (!exec->ce)
+   return -ENODEV;
+
+   max_msg_size = PXP43_MAX_HECI_IN_SIZE - sizeof(*header);
+
+   if (msg_in_size > max_msg_size || msg_out_size_max > max_msg_size)
+   return -ENOSPC;
+
+   mutex_lock(>tee_mutex);
+
+   if (!exec->pkt_vma || !exec->bb_vma)
+   return -ENOENT;
+
+   memset(header, 0, sizeof(*header));
+   intel_gsc_uc_heci_cmd_emit_mtl_header(header, GSC_HECI_MEADDRESS_PXP,
+ msg_in_size + sizeof(*header),
+ exec->host_session_handle);
+
+   /* check if this is a host-session-handle cleanup call */
+   if (null_pkt)
+   header->flags |= GSC_HECI_FLAG_MSG_CLEANUP;
+
+   /* copy caller provided gsc message handle if this is polling for a 
prior msg completion */
+   header->gsc_message_handle = *gsc_msg_handle_retry;
+
+   /* NOTE: zero size packets are used for session-cleanups */
+   if (msg_in && msg_in_size)
+   memcpy(exec->pkt_vaddr + sizeof(*header), msg_in, msg_in_size);
+
+   pkt.addr_in = i915_vma_offset(exec->pkt_vma);
+   pkt.size_in = header->message_size;
+   pkt.addr_out = pkt.addr_in + PXP43_MAX_HECI_IN_SIZE;
+   pkt.size_out = msg_out_size_max + sizeof(*header);
+   pkt.heci_pkt_vma = exec->pkt_vma;
+   pkt.bb_vma = exec->bb_vma;
+
+   ret = intel_gsc_uc_heci_cmd_submit_nonpriv(>uc.gsc,
+  exec->ce, , 
exec->bb_vaddr, 500);
+   if (ret) {
+   drm_err(>drm, "failed to send gsc PXP msg (%d)\n", ret);
+   goto unlock;
+   }
+
+   /* we keep separate location for reply, so get the response header loc 
first */
+   header = exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE;
+
+   /* Response validity marker, status and busyness */
+   if (header->validity_marker != GSC_HECI_VALIDITY_MARKER) {
+   drm_err(>drm, "gsc PXP reply with invalid validity 
marker\n");
+   ret = -EINVAL;
+   goto unlock;
+   }
+   if (header->status != 0) {
+   drm_dbg(>drm, "gsc PXP reply status has error = 0x%08x\n",
+