Re: [Intel-gfx] [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control

2023-07-21 Thread Andi Shyti 
Hi Andrzej,

> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
> > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 7566c89d9def3..9d050b9a19194 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -218,6 +218,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 
> > mode)
> > bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
> > +   /*
> > +* When required, in MTL+ platforms we need to
> > +* set the CCS_FLUSH bit in the pipe control
> > +*/
> > +   if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
> > +   bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
> > +
> 
> 
> Btw, not for this patch, but related: rcs and ccs have slightly different
> set of flushes according to bspec but this functions is the same for both.
> Is it sth we should address, or just safe simplification.

I guess this is not only used for ccs aux invalidation. I think
the BSPEC is specifying the minimum set of bits that need to be
set in the pipe control. So that I left it as it is and just
added this bit for MTL+.

Thanks,
Andi

Re: [Intel-gfx] [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control

2023-07-21 Thread Andrzej Hajda 

On 20.07.2023 23:07, Andi Shyti wrote:

Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti 
Cc: Jonathan Cavitt 
Cc: Nirmoy Das 
Cc:  # v5.8+
---
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++
  drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
  2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 7566c89d9def3..9d050b9a19194 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -218,6 +218,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
  
  		bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
  
+		/*

+* When required, in MTL+ platforms we need to
+* set the CCS_FLUSH bit in the pipe control
+*/
+   if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
+   bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
+



Btw, not for this patch, but related: rcs and ccs have slightly 
different set of flushes according to bspec but this functions is the 
same for both. Is it sth we should address, or just safe simplification.


Regards
Andrzej



bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 5d143e2a8db03..5df7cce23197c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -299,6 +299,7 @@
  #define   PIPE_CONTROL_QW_WRITE   (1<<14)
  #define   PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
  #define   PIPE_CONTROL_DEPTH_STALL(1<<13)
+#define   PIPE_CONTROL_CCS_FLUSH   (1<<13) /* MTL+ */
  #define   PIPE_CONTROL_WRITE_FLUSH(1<<12)
  #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH  (1<<12) /* gen6+ */
  #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE   (1<<11) /* MBZ on ILK */

Re: [Intel-gfx] [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control

2023-07-21 Thread Andi Shyti 
Hi Nirmoy,

On Fri, Jul 21, 2023 at 12:05:10PM +0200, Andrzej Hajda wrote:
> On 20.07.2023 23:07, Andi Shyti wrote:
> > Enable the CCS_FLUSH bit 13 in the control pipe for render and
> > compute engines in platforms starting from Meteor Lake (BSPEC
> > 43904 and 47112).
> > 
> > Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all 
> > engines")
> > Signed-off-by: Andi Shyti 
> > Cc: Jonathan Cavitt 
> > Cc: Nirmoy Das 
> > Cc:  # v5.8+
> > ---
> >   drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++
> >   drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> >   2 files changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
> > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 7566c89d9def3..9d050b9a19194 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -218,6 +218,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 
> > mode)
> > bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
> > +   /*
> > +* When required, in MTL+ platforms we need to
> > +* set the CCS_FLUSH bit in the pipe control
> > +*/
> > +   if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
> > +   bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
> 
> BSpec 43904 mentions also other platforms. Why only MTL+?

This is the process of quiescing the engine and that is done in
the pipe control sequence.

In the pipe control sequence each engine has its own sequence,
even though render and compute overlap on some bits, while the
others overlap on other bits.

Besides that MTL+ need this extra bit to be set in the pipe
control and that is bit 13 defined as PIPE_CONTROL_CCS_FLUSH.

Thanks,
Andi

Re: [Intel-gfx] [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control

2023-07-21 Thread Andrzej Hajda 

On 20.07.2023 23:07, Andi Shyti wrote:

Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti 
Cc: Jonathan Cavitt 
Cc: Nirmoy Das 
Cc:  # v5.8+
---
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++
  drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
  2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 7566c89d9def3..9d050b9a19194 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -218,6 +218,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
  
  		bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
  
+		/*

+* When required, in MTL+ platforms we need to
+* set the CCS_FLUSH bit in the pipe control
+*/
+   if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
+   bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;



BSpec 43904 mentions also other platforms. Why only MTL+?


Regards
Andrzej



+
bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 5d143e2a8db03..5df7cce23197c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -299,6 +299,7 @@
  #define   PIPE_CONTROL_QW_WRITE   (1<<14)
  #define   PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
  #define   PIPE_CONTROL_DEPTH_STALL(1<<13)
+#define   PIPE_CONTROL_CCS_FLUSH   (1<<13) /* MTL+ */
  #define   PIPE_CONTROL_WRITE_FLUSH(1<<12)
  #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH  (1<<12) /* gen6+ */
  #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE   (1<<11) /* MBZ on ILK */

[Intel-gfx] [PATCH v7 5/9] drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control

2023-07-20 Thread Andi Shyti 
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).

Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti 
Cc: Jonathan Cavitt 
Cc: Nirmoy Das 
Cc:  # v5.8+
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 7566c89d9def3..9d050b9a19194 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -218,6 +218,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 
bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
 
+   /*
+* When required, in MTL+ platforms we need to
+* set the CCS_FLUSH bit in the pipe control
+*/
+   if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
+   bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
+
bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 5d143e2a8db03..5df7cce23197c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -299,6 +299,7 @@
 #define   PIPE_CONTROL_QW_WRITE(1<<14)
 #define   PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
 #define   PIPE_CONTROL_DEPTH_STALL (1<<13)
+#define   PIPE_CONTROL_CCS_FLUSH   (1<<13) /* MTL+ */
 #define   PIPE_CONTROL_WRITE_FLUSH (1<<12)
 #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH   (1<<12) /* gen6+ */
 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE(1<<11) /* MBZ on ILK */
-- 
2.40.1