Re: [Intel-gfx] [PATCH v8 3/7] drm/i915/skl: Rework MOCS tables to keep common part in a define

2019-01-23 Thread Lis, Tomasz 



On 2019-01-22 06:12, Lucas De Marchi wrote:

From: Tomasz Lis 

The MOCS tables are going to be very similar across platforms.

To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.

v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
 to MOCS_ENTRIES. (Joonas)
v3 (Lucas):
   - Fix indentation
   - Rebase on rework done by additional patch
   - Remove define for or-ing flags as it made the table more complex by
 requiring zeroed values to be passed
   - Do not embed comma in the macro, so to treat that just as another
 item and please source code formatting tools

Signed-off-by: Tomasz Lis 
Suggested-by: Lucas De Marchi 
Signed-off-by: Lucas De Marchi 

Acked-by: Tomasz Lis 
-Tomasz

---
  drivers/gpu/drm/i915/intel_mocs.c | 57 ++-
  1 file changed, 25 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
b/drivers/gpu/drm/i915/intel_mocs.c
index 4ea80bb7dcc8..c7a2a8d81d90 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -93,46 +93,39 @@ struct drm_i915_mocs_table {
   *   may only be updated incrementally by adding entries at the
   *   end.
   */
+
+#define GEN9_MOCS_ENTRIES \
+   [I915_MOCS_UNCACHED] = { \
+   /* 0x0009 */ \
+   .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, \
+   /* 0x0010 */ \
+   .l3cc_value = L3_1_UC, \
+   }, \
+   [I915_MOCS_PTE] = { \
+   /* 0x0038 */ \
+   .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | 
LE_LRUM(3), \
+   /* 0x0030 */ \
+   .l3cc_value = L3_3_WB, \
+   }
+
  static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
-   [I915_MOCS_UNCACHED] = {
- /* 0x0009 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
- /* 0x0010 */
- .l3cc_value =L3_1_UC,
-   },
-   [I915_MOCS_PTE] = {
- /* 0x0038 */
- .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value =L3_3_WB,
-   },
+   GEN9_MOCS_ENTRIES,
[I915_MOCS_CACHED] = {
- /* 0x003b */
- .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value =   L3_3_WB,
+   /* 0x003b */
+   .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+   /* 0x0030 */
+   .l3cc_value =   L3_3_WB,
},
  };
  
  /* NOTE: the LE_TGT_CACHE is not used on Broxton */

  static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
-   [I915_MOCS_UNCACHED] = {
- /* 0x0009 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
- /* 0x0010 */
- .l3cc_value = L3_1_UC,
-   },
-   [I915_MOCS_PTE] = {
- /* 0x0038 */
- .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value = L3_3_WB,
-   },
+   GEN9_MOCS_ENTRIES,
[I915_MOCS_CACHED] = {
- /* 0x0039 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value = L3_3_WB,
+   /* 0x0039 */
+   .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+   /* 0x0030 */
+   .l3cc_value = L3_3_WB,
},
  };
  


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Re: [Intel-gfx] [PATCH v8 3/7] drm/i915/skl: Rework MOCS tables to keep common part in a define

2019-01-22 Thread Chris Wilson 
Quoting Lucas De Marchi (2019-01-22 05:12:23)
> From: Tomasz Lis 
> 
> The MOCS tables are going to be very similar across platforms.
> 
> To reduce the amount of copied code, this patch rips the common part and
> puts it into a definition valid for all gen9 platforms.
> 
> v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
> to MOCS_ENTRIES. (Joonas)
> v3 (Lucas):
>   - Fix indentation
>   - Rebase on rework done by additional patch
>   - Remove define for or-ing flags as it made the table more complex by
> requiring zeroed values to be passed
>   - Do not embed comma in the macro, so to treat that just as another
> item and please source code formatting tools
> 
> Signed-off-by: Tomasz Lis 
> Suggested-by: Lucas De Marchi 
> Signed-off-by: Lucas De Marchi 
> ---
>  drivers/gpu/drm/i915/intel_mocs.c | 57 ++-
>  1 file changed, 25 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
> b/drivers/gpu/drm/i915/intel_mocs.c
> index 4ea80bb7dcc8..c7a2a8d81d90 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -93,46 +93,39 @@ struct drm_i915_mocs_table {
>   *   may only be updated incrementally by adding entries at the
>   *   end.
>   */
> +
> +#define GEN9_MOCS_ENTRIES \
> +   [I915_MOCS_UNCACHED] = { \
> +   /* 0x0009 */ \
> +   .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, \
> +   /* 0x0010 */ \
> +   .l3cc_value = L3_1_UC, \
> +   }, \
> +   [I915_MOCS_PTE] = { \
> +   /* 0x0038 */ \
> +   .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | 
> LE_LRUM(3), \
> +   /* 0x0030 */ \
> +   .l3cc_value = L3_3_WB, \
> +   }
> +
>  static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
> -   [I915_MOCS_UNCACHED] = {
> - /* 0x0009 */
> - .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
> - /* 0x0010 */
> - .l3cc_value =L3_1_UC,
> -   },
> -   [I915_MOCS_PTE] = {
> - /* 0x0038 */
> - .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
> - /* 0x0030 */
> - .l3cc_value =L3_3_WB,
> -   },
> +   GEN9_MOCS_ENTRIES,
> [I915_MOCS_CACHED] = {
> - /* 0x003b */
> - .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
> - /* 0x0030 */
> - .l3cc_value =   L3_3_WB,
> +   /* 0x003b */

You scared me with the indentation change at the same time.

Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] [PATCH v8 3/7] drm/i915/skl: Rework MOCS tables to keep common part in a define

2019-01-21 Thread Lucas De Marchi 
From: Tomasz Lis 

The MOCS tables are going to be very similar across platforms.

To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.

v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
to MOCS_ENTRIES. (Joonas)
v3 (Lucas):
  - Fix indentation
  - Rebase on rework done by additional patch
  - Remove define for or-ing flags as it made the table more complex by
requiring zeroed values to be passed
  - Do not embed comma in the macro, so to treat that just as another
item and please source code formatting tools

Signed-off-by: Tomasz Lis 
Suggested-by: Lucas De Marchi 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/intel_mocs.c | 57 ++-
 1 file changed, 25 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
b/drivers/gpu/drm/i915/intel_mocs.c
index 4ea80bb7dcc8..c7a2a8d81d90 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -93,46 +93,39 @@ struct drm_i915_mocs_table {
  *   may only be updated incrementally by adding entries at the
  *   end.
  */
+
+#define GEN9_MOCS_ENTRIES \
+   [I915_MOCS_UNCACHED] = { \
+   /* 0x0009 */ \
+   .control_value = LE_1_UC | LE_TC_2_LLC_ELLC, \
+   /* 0x0010 */ \
+   .l3cc_value = L3_1_UC, \
+   }, \
+   [I915_MOCS_PTE] = { \
+   /* 0x0038 */ \
+   .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | 
LE_LRUM(3), \
+   /* 0x0030 */ \
+   .l3cc_value = L3_3_WB, \
+   }
+
 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
-   [I915_MOCS_UNCACHED] = {
- /* 0x0009 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
- /* 0x0010 */
- .l3cc_value =L3_1_UC,
-   },
-   [I915_MOCS_PTE] = {
- /* 0x0038 */
- .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value =L3_3_WB,
-   },
+   GEN9_MOCS_ENTRIES,
[I915_MOCS_CACHED] = {
- /* 0x003b */
- .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value =   L3_3_WB,
+   /* 0x003b */
+   .control_value = LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+   /* 0x0030 */
+   .l3cc_value =   L3_3_WB,
},
 };
 
 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
-   [I915_MOCS_UNCACHED] = {
- /* 0x0009 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC,
- /* 0x0010 */
- .l3cc_value = L3_1_UC,
-   },
-   [I915_MOCS_PTE] = {
- /* 0x0038 */
- .control_value = LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value = L3_3_WB,
-   },
+   GEN9_MOCS_ENTRIES,
[I915_MOCS_CACHED] = {
- /* 0x0039 */
- .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
- /* 0x0030 */
- .l3cc_value = L3_3_WB,
+   /* 0x0039 */
+   .control_value = LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+   /* 0x0030 */
+   .l3cc_value = L3_3_WB,
},
 };
 
-- 
2.20.0

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