Re: [Intel-gfx] [RFC 5/8] drm/i915/gen11+: Prefer gen over platform codename.
On Thu, 18 Oct 2018, Rodrigo Vivi wrote:
> Also let's always consider next platform follows
> the most recent one. Like we have done for transitioning
> gen9 to gen10 and gent10 to gen11.
>
> Let's use same approach for gen11+ and only introduce
> changes later as needed.
Same worry as with Geminilake. The gen is essentially the gem gen, not
display gen.
BR,
Jani.
>
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
> drivers/gpu/drm/i915/intel_ddi.c| 18 +-
> drivers/gpu/drm/i915/intel_display.c| 8
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_mocs.c | 3 +--
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> 8 files changed, 24 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index b315b70fd49c..915e2c93412b 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2572,7 +2572,7 @@ static int intel_compute_max_dotclk(struct
> drm_i915_private *dev_priv)
> */
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> {
> - if (IS_ICELAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> if (dev_priv->cdclk.hw.ref == 24000)
> dev_priv->max_cdclk_freq = 648000;
> else
> @@ -2801,12 +2801,12 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
> dev_priv->display.set_cdclk = cnl_set_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> cnl_modeset_calc_cdclk;
> - } else if (IS_ICELAKE(dev_priv)) {
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.set_cdclk = icl_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> }
>
> - if (IS_ICELAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11)
> dev_priv->display.get_cdclk = icl_get_cdclk;
> else if (IS_GEN10(dev_priv))
> dev_priv->display.get_cdclk = cnl_get_cdclk;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index cd627851f2a5..10b5314f266c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -915,7 +915,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
> *dev_priv, enum port por
>
> level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> - if (IS_ICELAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> if (intel_port_is_combophy(dev_priv, port))
> icl_get_combo_buf_trans(dev_priv, port,
> INTEL_OUTPUT_HDMI, _entries);
> @@ -1745,7 +1745,7 @@ static void intel_ddi_clock_get(struct intel_encoder
> *encoder,
> bxt_ddi_clock_get(encoder, pipe_config);
> else if (IS_GEN10(dev_priv))
> cnl_ddi_clock_get(encoder, pipe_config);
> - else if (IS_ICELAKE(dev_priv))
> + else if (INTEL_GEN(dev_priv) >= 11)
> icl_ddi_clock_get(encoder, pipe_config);
> }
>
> @@ -2241,7 +2241,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder
> *encoder)
> enum port port = encoder->port;
> int n_entries;
>
> - if (IS_ICELAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> if (intel_port_is_combophy(dev_priv, port))
> icl_get_combo_buf_trans(dev_priv, port, encoder->type,
> _entries);
> @@ -2716,7 +2716,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
> struct intel_encoder *encoder = >base;
> int level = intel_ddi_dp_level(intel_dp);
>
> - if (IS_ICELAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11)
> icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
> level, encoder->type);
> else if (IS_GEN10(dev_priv))
> @@ -2833,7 +2833,7 @@ static void intel_ddi_clk_select(struct intel_encoder
> *encoder,
>
> mutex_lock(_priv->dpll_lock);
>
> - if (IS_ICELAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> if (!intel_port_is_combophy(dev_priv, port))
> I915_WRITE(DDI_CLK_SEL(port),
> icl_pll_to_ddi_pll_sel(encoder, crtc_state));
> @@ -2875,7 +2875,7 @@ static void intel_ddi_clk_disable(struct intel_encoder
> *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
>
> - if (IS_ICELAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> if (!intel_port_is_combophy(dev_priv, port))
> I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
> } else if
[Intel-gfx] [RFC 5/8] drm/i915/gen11+: Prefer gen over platform codename.
Also let's always consider next platform follows
the most recent one. Like we have done for transitioning
gen9 to gen10 and gent10 to gen11.
Let's use same approach for gen11+ and only introduce
changes later as needed.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_cdclk.c | 6 +++---
drivers/gpu/drm/i915/intel_ddi.c| 18 +-
drivers/gpu/drm/i915/intel_display.c| 8
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_mocs.c | 3 +--
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
8 files changed, 24 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index b315b70fd49c..915e2c93412b 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2572,7 +2572,7 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
*/
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (dev_priv->cdclk.hw.ref == 24000)
dev_priv->max_cdclk_freq = 648000;
else
@@ -2801,12 +2801,12 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
dev_priv->display.set_cdclk = cnl_set_cdclk;
dev_priv->display.modeset_calc_cdclk =
cnl_modeset_calc_cdclk;
- } else if (IS_ICELAKE(dev_priv)) {
+ } else if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.set_cdclk = icl_set_cdclk;
dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
}
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
dev_priv->display.get_cdclk = icl_get_cdclk;
else if (IS_GEN10(dev_priv))
dev_priv->display.get_cdclk = cnl_get_cdclk;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cd627851f2a5..10b5314f266c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -915,7 +915,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
*dev_priv, enum port por
level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port,
INTEL_OUTPUT_HDMI, _entries);
@@ -1745,7 +1745,7 @@ static void intel_ddi_clock_get(struct intel_encoder
*encoder,
bxt_ddi_clock_get(encoder, pipe_config);
else if (IS_GEN10(dev_priv))
cnl_ddi_clock_get(encoder, pipe_config);
- else if (IS_ICELAKE(dev_priv))
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_ddi_clock_get(encoder, pipe_config);
}
@@ -2241,7 +2241,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
enum port port = encoder->port;
int n_entries;
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port, encoder->type,
_entries);
@@ -2716,7 +2716,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp)
struct intel_encoder *encoder = >base;
int level = intel_ddi_dp_level(intel_dp);
- if (IS_ICELAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
level, encoder->type);
else if (IS_GEN10(dev_priv))
@@ -2833,7 +2833,7 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
mutex_lock(_priv->dpll_lock);
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (!intel_port_is_combophy(dev_priv, port))
I915_WRITE(DDI_CLK_SEL(port),
icl_pll_to_ddi_pll_sel(encoder, crtc_state));
@@ -2875,7 +2875,7 @@ static void intel_ddi_clk_disable(struct intel_encoder
*encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
if (!intel_port_is_combophy(dev_priv, port))
I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
} else if (IS_GEN10(dev_priv)) {
@@ -2917,7 +2917,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
icl_program_mg_dp_mode(intel_dp);
icl_disable_phy_clock_gating(dig_port);
- if (IS_ICELAKE(dev_priv))
+ if
