Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev5)
On Wed, 2016-04-27 at 17:39 +0300, Tomi Sarvela wrote: > Hello, > > On Wednesday 27 April 2016 16:36:13 Ander Conselvan De Oliveira wrote: > > > Subgroup suspend-read-crc-pipe-a: > > > pass -> INCOMPLETE (hsw-gt2) > > > > dmesg ends with > > > > [ 505.669959] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A > > > > Seems very unlikely this would be caused by this series. The only code that > > is run on hsw machines is setting the lane count field in crtc_state, but > > that is not used anywhere. > > > > Are there any know issues with this machine? > > There is no known issues with this hardware itself. There is one known issue > with HSW and drm-intel kernel, which has taken a while to figure out. I think > it still exists in the baseline kernel where patch is applied. > > (It's hard to replicate with IGT, but newest Mesa seems to hit it quite > regularly). Patches pushed to dinq. Thanks, Ander ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev5)
Hello, On Wednesday 27 April 2016 16:36:13 Ander Conselvan De Oliveira wrote: > > Subgroup suspend-read-crc-pipe-a: > > pass -> INCOMPLETE (hsw-gt2) > > dmesg ends with > > [ 505.669959] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A > > Seems very unlikely this would be caused by this series. The only code that > is run on hsw machines is setting the lane count field in crtc_state, but > that is not used anywhere. > > Are there any know issues with this machine? There is no known issues with this hardware itself. There is one known issue with HSW and drm-intel kernel, which has taken a while to figure out. I think it still exists in the baseline kernel where patch is applied. (It's hard to replicate with IGT, but newest Mesa seems to hit it quite regularly). Regards, Tomi > > > Ander > > > bdw-nuci7total:200 pass:188 dwarn:0 dfail:0 fail:0 skip:12 > > bdw-ultratotal:200 pass:175 dwarn:0 dfail:0 fail:0 skip:25 > > bsw-nuc-2total:199 pass:158 dwarn:0 dfail:0 fail:0 skip:41 > > byt-nuc total:199 pass:158 dwarn:0 dfail:0 fail:0 skip:41 > > hsw-brixbox total:200 pass:174 dwarn:0 dfail:0 fail:0 skip:26 > > hsw-gt2 total:199 pass:176 dwarn:0 dfail:0 fail:1 skip:21 > > ilk-hp8440p total:200 pass:139 dwarn:0 dfail:0 fail:0 skip:61 > > ivb-t430stotal:200 pass:169 dwarn:0 dfail:0 fail:0 skip:31 > > skl-i7k-2total:200 pass:173 dwarn:0 dfail:0 fail:0 skip:27 > > skl-nuci5total:200 pass:189 dwarn:0 dfail:0 fail:0 skip:11 > > snb-dellxps total:200 pass:157 dwarn:1 dfail:0 fail:0 skip:42 > > snb-x220ttotal:200 pass:158 dwarn:0 dfail:0 fail:1 skip:41 > > > > Results at /archive/results/CI_IGT_test/Patchwork_2090/ > > > > 4fa405ab5848b76c8568c7fb771d389a6695108c drm-intel-nightly: > > 2016y-04m-27d-10h -47m-35s UTC integration manifest > > 9e163c0 drm/i915: Move VLV HDMI lane reset work around logic to > > intel_dpio_phy.c > > b7b843d drm/i915: Unduplicate pre encoder enabling phy code > > 4165303 drm/i915: Unduplicate VLV phy pre pll enabling code > > 7241e40 drm/i915: Unduplicate VLV signal level code > > 1879a24 drm/i915: Unduplicate CHV encoders' post pll disable code > > 3b54e74 drm/i915: Unduplicate CHV pre-encoder enabling phy logic > > 66e88ec drm/i915: Unduplicate CHV phy-releated pre pll enabling code > > 8a2b013 drm/i915: Unduplicate chv_data_lane_soft_reset() > > 4a6d52d drm/i915: Unduplicate CHV signal level code > > 5a20188 drm/i915: Set crtc_state->lane_count for HDMI ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev5)
On Wed, 2016-04-27 at 13:23 +, Patchwork wrote: > == Series Details == > > Series: Unduplicate CHV phy code (rev5) > URL : https://patchwork.freedesktop.org/series/5463/ > State : failure > > == Summary == > > Series 5463v5 Unduplicate CHV phy code > http://patchwork.freedesktop.org/api/1.0/series/5463/revisions/5/mbox/ > > Test drv_module_reload_basic: > dmesg-warn -> PASS (snb-x220t) > Test gem_exec_suspend: > Subgroup basic-s3: > fail -> PASS (snb-x220t) > Test kms_pipe_crc_basic: > Subgroup hang-read-crc-pipe-a: > pass -> DMESG-WARN (snb-dellxps) [ 303.915830] [ cut here ] [ 303.915859] WARNING: CPU: 5 PID: 6657 at drivers/gpu/drm/i915/intel_display.c:13529 intel_atomic_commit+0x1271/0x1400 [i915] [ 303.915861] pipe A vblank wait timed out https://bugs.freedesktop.org/show_bug.cgi?id=95125 > Subgroup suspend-read-crc-pipe-a: > pass -> INCOMPLETE (hsw-gt2) dmesg ends with [ 505.669959] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A Seems very unlikely this would be caused by this series. The only code that is run on hsw machines is setting the lane count field in crtc_state, but that is not used anywhere. Are there any know issues with this machine? Ander > > bdw-nuci7total:200 pass:188 dwarn:0 dfail:0 fail:0 skip:12 > bdw-ultratotal:200 pass:175 dwarn:0 dfail:0 fail:0 skip:25 > bsw-nuc-2total:199 pass:158 dwarn:0 dfail:0 fail:0 skip:41 > byt-nuc total:199 pass:158 dwarn:0 dfail:0 fail:0 skip:41 > hsw-brixbox total:200 pass:174 dwarn:0 dfail:0 fail:0 skip:26 > hsw-gt2 total:199 pass:176 dwarn:0 dfail:0 fail:1 skip:21 > ilk-hp8440p total:200 pass:139 dwarn:0 dfail:0 fail:0 skip:61 > ivb-t430stotal:200 pass:169 dwarn:0 dfail:0 fail:0 skip:31 > skl-i7k-2total:200 pass:173 dwarn:0 dfail:0 fail:0 skip:27 > skl-nuci5total:200 pass:189 dwarn:0 dfail:0 fail:0 skip:11 > snb-dellxps total:200 pass:157 dwarn:1 dfail:0 fail:0 skip:42 > snb-x220ttotal:200 pass:158 dwarn:0 dfail:0 fail:1 skip:41 > > Results at /archive/results/CI_IGT_test/Patchwork_2090/ > > 4fa405ab5848b76c8568c7fb771d389a6695108c drm-intel-nightly: 2016y-04m-27d-10h > -47m-35s UTC integration manifest > 9e163c0 drm/i915: Move VLV HDMI lane reset work around logic to > intel_dpio_phy.c > b7b843d drm/i915: Unduplicate pre encoder enabling phy code > 4165303 drm/i915: Unduplicate VLV phy pre pll enabling code > 7241e40 drm/i915: Unduplicate VLV signal level code > 1879a24 drm/i915: Unduplicate CHV encoders' post pll disable code > 3b54e74 drm/i915: Unduplicate CHV pre-encoder enabling phy logic > 66e88ec drm/i915: Unduplicate CHV phy-releated pre pll enabling code > 8a2b013 drm/i915: Unduplicate chv_data_lane_soft_reset() > 4a6d52d drm/i915: Unduplicate CHV signal level code > 5a20188 drm/i915: Set crtc_state->lane_count for HDMI > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev5)
== Series Details == Series: Unduplicate CHV phy code (rev5) URL : https://patchwork.freedesktop.org/series/5463/ State : failure == Summary == Series 5463v5 Unduplicate CHV phy code http://patchwork.freedesktop.org/api/1.0/series/5463/revisions/5/mbox/ Test drv_module_reload_basic: dmesg-warn -> PASS (snb-x220t) Test gem_exec_suspend: Subgroup basic-s3: fail -> PASS (snb-x220t) Test kms_pipe_crc_basic: Subgroup hang-read-crc-pipe-a: pass -> DMESG-WARN (snb-dellxps) Subgroup suspend-read-crc-pipe-a: pass -> INCOMPLETE (hsw-gt2) bdw-nuci7total:200 pass:188 dwarn:0 dfail:0 fail:0 skip:12 bdw-ultratotal:200 pass:175 dwarn:0 dfail:0 fail:0 skip:25 bsw-nuc-2total:199 pass:158 dwarn:0 dfail:0 fail:0 skip:41 byt-nuc total:199 pass:158 dwarn:0 dfail:0 fail:0 skip:41 hsw-brixbox total:200 pass:174 dwarn:0 dfail:0 fail:0 skip:26 hsw-gt2 total:199 pass:176 dwarn:0 dfail:0 fail:1 skip:21 ilk-hp8440p total:200 pass:139 dwarn:0 dfail:0 fail:0 skip:61 ivb-t430stotal:200 pass:169 dwarn:0 dfail:0 fail:0 skip:31 skl-i7k-2total:200 pass:173 dwarn:0 dfail:0 fail:0 skip:27 skl-nuci5total:200 pass:189 dwarn:0 dfail:0 fail:0 skip:11 snb-dellxps total:200 pass:157 dwarn:1 dfail:0 fail:0 skip:42 snb-x220ttotal:200 pass:158 dwarn:0 dfail:0 fail:1 skip:41 Results at /archive/results/CI_IGT_test/Patchwork_2090/ 4fa405ab5848b76c8568c7fb771d389a6695108c drm-intel-nightly: 2016y-04m-27d-10h-47m-35s UTC integration manifest 9e163c0 drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.c b7b843d drm/i915: Unduplicate pre encoder enabling phy code 4165303 drm/i915: Unduplicate VLV phy pre pll enabling code 7241e40 drm/i915: Unduplicate VLV signal level code 1879a24 drm/i915: Unduplicate CHV encoders' post pll disable code 3b54e74 drm/i915: Unduplicate CHV pre-encoder enabling phy logic 66e88ec drm/i915: Unduplicate CHV phy-releated pre pll enabling code 8a2b013 drm/i915: Unduplicate chv_data_lane_soft_reset() 4a6d52d drm/i915: Unduplicate CHV signal level code 5a20188 drm/i915: Set crtc_state->lane_count for HDMI ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
