[PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS

2024-02-20 Thread Andi Shyti 
The hardware should not dynamically balance the load between CCS
engines. Wa_16016805146 recommends disabling it across all
platforms.

Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Matt Roper 
Cc:  # v6.2+
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 50962cfd1353..cf709f6c05ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1478,6 +1478,7 @@
 
 #define GEN12_RCU_MODE _MMIO(0x14800)
 #define   GEN12_RCU_MODE_CCS_ENABLEREG_BIT(0)
+#define   XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE   REG_BIT(1)
 
 #define CHV_FUSE_GT_MMIO(VLV_GUNIT_BASE + 0x2168)
 #define   CHV_FGT_DISABLE_SS0  (1 << 10)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d67d44611c28..7f42c8015f71 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs 
*engine, struct i915_wa_li
wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
}
+
+   /*
+* Wa_16016805146: disable the CCS load balancing
+* indiscriminately for all the platforms
+*/
+   wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
 }
 
 static void
-- 
2.43.0

Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS

2024-02-19 Thread Andi Shyti 
On Mon, Feb 19, 2024 at 11:17:33AM +0100, Andi Shyti wrote:
> On Thu, Feb 15, 2024 at 08:55:41AM -0800, Matt Roper wrote:
> > On Thu, Feb 15, 2024 at 02:59:23PM +0100, Andi Shyti wrote:
> > > The hardware should not dynamically balance the load between CCS
> > > engines. Wa_16016805146 recommends disabling it across all
> > 
> > Is this the right workaround number?  When I check the database, this
> > workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even
> > have an entry for DG2-G12.
> > 
> > There are other workarounds that sound somewhat related to load
> > balancing (e.g., part 3 of Wa_14019159160), but what's asked there is
> > more involved than just setting one register bit and conflicts a bit
> > with the second patch of this series.
> 
> thanks for checking it. Indeed the WA I mentioned is limited to
> a specific platform. This recommendation comes in different WA,
> e.g. this one: Wa_14019186972 (3rd point). Will start using that
> as a reference.

actually you are right, I checked with Joonas and I will use
Wa_14019159160.

Thanks,
Andi

Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS

2024-02-19 Thread Andi Shyti 
Hi Matt,

On Thu, Feb 15, 2024 at 08:55:41AM -0800, Matt Roper wrote:
> On Thu, Feb 15, 2024 at 02:59:23PM +0100, Andi Shyti wrote:
> > The hardware should not dynamically balance the load between CCS
> > engines. Wa_16016805146 recommends disabling it across all
> 
> Is this the right workaround number?  When I check the database, this
> workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even
> have an entry for DG2-G12.
> 
> There are other workarounds that sound somewhat related to load
> balancing (e.g., part 3 of Wa_14019159160), but what's asked there is
> more involved than just setting one register bit and conflicts a bit
> with the second patch of this series.

thanks for checking it. Indeed the WA I mentioned is limited to
a specific platform. This recommendation comes in different WA,
e.g. this one: Wa_14019186972 (3rd point). Will start using that
as a reference.

Thank you.
Andi

> 
> 
> Matt
> 
> > platforms.
> > 
> > Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> > Signed-off-by: Andi Shyti 
> > Cc: Chris Wilson 
> > Cc: Joonas Lahtinen 
> > Cc: Matt Roper 
> > Cc:  # v6.2+
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
> >  2 files changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 50962cfd1353..cf709f6c05ae 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1478,6 +1478,7 @@
> >  
> >  #define GEN12_RCU_MODE _MMIO(0x14800)
> >  #define   GEN12_RCU_MODE_CCS_ENABLEREG_BIT(0)
> > +#define   XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE   REG_BIT(1)
> >  
> >  #define CHV_FUSE_GT_MMIO(VLV_GUNIT_BASE + 
> > 0x2168)
> >  #define   CHV_FGT_DISABLE_SS0  (1 << 10)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index d67d44611c28..7f42c8015f71 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct 
> > intel_engine_cs *engine, struct i915_wa_li
> > wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> >  GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> > }
> > +
> > +   /*
> > +* Wa_16016805146: disable the CCS load balancing
> > +* indiscriminately for all the platforms
> > +*/
> > +   wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
> >  }
> >  
> >  static void
> > -- 
> > 2.43.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS

2024-02-15 Thread Matt Roper 
On Thu, Feb 15, 2024 at 02:59:23PM +0100, Andi Shyti wrote:
> The hardware should not dynamically balance the load between CCS
> engines. Wa_16016805146 recommends disabling it across all

Is this the right workaround number?  When I check the database, this
workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even
have an entry for DG2-G12.

There are other workarounds that sound somewhat related to load
balancing (e.g., part 3 of Wa_14019159160), but what's asked there is
more involved than just setting one register bit and conflicts a bit
with the second patch of this series.


Matt

> platforms.
> 
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti 
> Cc: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Matt Roper 
> Cc:  # v6.2+
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 50962cfd1353..cf709f6c05ae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1478,6 +1478,7 @@
>  
>  #define GEN12_RCU_MODE   _MMIO(0x14800)
>  #define   GEN12_RCU_MODE_CCS_ENABLE  REG_BIT(0)
> +#define   XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
>  
>  #define CHV_FUSE_GT  _MMIO(VLV_GUNIT_BASE + 0x2168)
>  #define   CHV_FGT_DISABLE_SS0(1 << 10)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d67d44611c28..7f42c8015f71 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs 
> *engine, struct i915_wa_li
>   wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
>GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>   }
> +
> + /*
> +  * Wa_16016805146: disable the CCS load balancing
> +  * indiscriminately for all the platforms
> +  */
> + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
>  }
>  
>  static void
> -- 
> 2.43.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS

2024-02-15 Thread Andi Shyti 
The hardware should not dynamically balance the load between CCS
engines. Wa_16016805146 recommends disabling it across all
platforms.

Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti 
Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Matt Roper 
Cc:  # v6.2+
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 50962cfd1353..cf709f6c05ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1478,6 +1478,7 @@
 
 #define GEN12_RCU_MODE _MMIO(0x14800)
 #define   GEN12_RCU_MODE_CCS_ENABLEREG_BIT(0)
+#define   XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE   REG_BIT(1)
 
 #define CHV_FUSE_GT_MMIO(VLV_GUNIT_BASE + 0x2168)
 #define   CHV_FGT_DISABLE_SS0  (1 << 10)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d67d44611c28..7f42c8015f71 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs 
*engine, struct i915_wa_li
wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
}
+
+   /*
+* Wa_16016805146: disable the CCS load balancing
+* indiscriminately for all the platforms
+*/
+   wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
 }
 
 static void
-- 
2.43.0