RE: [PATCH 2/3] drm/i915/mtl: Remove misleading "clock" field from C20 pll_state
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Friday, December 8, 2023 12:10 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sripada, Radhakrishna ; Taylor, Clinton A
> ; Kahola, Mika
>
> Subject: [PATCH 2/3] drm/i915/mtl: Remove misleading "clock" field from C20
> pll_state
>
> The field link_bit_rate serves as the actual clock value for the C20
> pll_state structure. Remove the misleading clock field. The
> subsequent patch would rename the link_bit_rate as the clock field.
>
> Cc: Clint Taylor
> Cc: Mika Kahola
Reviewed-by: Mika Kahola
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 --
> .../gpu/drm/i915/display/intel_display_types.h | 3 +--
> 2 files changed, 1 insertion(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 7d412be996ea..d518b55d5150 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -746,7 +746,6 @@ static const struct intel_c10pll_state * const
> mtl_c10_edp_tables[] = {
> /* C20 basic DP 1.4 tables */
> static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> .link_bit_rate = 162000,
> - .clock = 162000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x5800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -772,7 +771,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = {
>
> static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> .link_bit_rate = 27,
> - .clock = 27,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -798,7 +796,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
>
> static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> .link_bit_rate = 54,
> - .clock = 54,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -824,7 +821,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
>
> static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> .link_bit_rate = 81,
> - .clock = 81,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -851,7 +847,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> /* C20 basic DP 2.0 tables */
> static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> .link_bit_rate = 100, /* 10 Gbps */
> - .clock = 312500,
> .tx = { 0xbe21, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -876,7 +871,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10
> = {
>
> static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> .link_bit_rate = 135, /* 13.5 Gbps */
> - .clock = 421875,
> .tx = { 0xbea0, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -902,7 +896,6 @@ static const struct intel_c20pll_state
> mtl_c20_dp_uhbr13_5 = {
>
> static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> .link_bit_rate = 200, /* 20 Gbps */
> - .clock = 625000,
> .tx = { 0xbe20, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -1522,7 +1515,6 @@ static const struct intel_c10pll_state * const
> mtl_c10_hdmi_tables[] = {
>
> static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> .link_bit_rate = 25175,
> - .clock = 25175,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -1548,7 +1540,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_25_175 = {
>
> static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> .link_bit_rate = 27000,
> - .clock = 27000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -1574,7 +1565,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_27_0 = {
>
> static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> .link_bit_rate = 74250,
> - .clock = 74250,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -1600,7 +1590,6 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_74_25 = {
>
> static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> .link_bit_rate =
[PATCH 2/3] drm/i915/mtl: Remove misleading "clock" field from C20 pll_state
The field link_bit_rate serves as the actual clock value for the C20
pll_state structure. Remove the misleading clock field. The subsequent
patch would rename the link_bit_rate as the clock field.
Cc: Clint Taylor
Cc: Mika Kahola
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 --
.../gpu/drm/i915/display/intel_display_types.h | 3 +--
2 files changed, 1 insertion(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 7d412be996ea..d518b55d5150 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -746,7 +746,6 @@ static const struct intel_c10pll_state * const
mtl_c10_edp_tables[] = {
/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = {
.link_bit_rate = 162000,
- .clock = 162000,
.tx = { 0xbe88, /* tx cfg0 */
0x5800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -772,7 +771,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = {
static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
.link_bit_rate = 27,
- .clock = 27,
.tx = { 0xbe88, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -798,7 +796,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
.link_bit_rate = 54,
- .clock = 54,
.tx = { 0xbe88, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -824,7 +821,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
.link_bit_rate = 81,
- .clock = 81,
.tx = { 0xbe88, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -851,7 +847,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
/* C20 basic DP 2.0 tables */
static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
.link_bit_rate = 100, /* 10 Gbps */
- .clock = 312500,
.tx = { 0xbe21, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -876,7 +871,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
.link_bit_rate = 135, /* 13.5 Gbps */
- .clock = 421875,
.tx = { 0xbea0, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -902,7 +896,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5
= {
static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
.link_bit_rate = 200, /* 20 Gbps */
- .clock = 625000,
.tx = { 0xbe20, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -1522,7 +1515,6 @@ static const struct intel_c10pll_state * const
mtl_c10_hdmi_tables[] = {
static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
.link_bit_rate = 25175,
- .clock = 25175,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -1548,7 +1540,6 @@ static const struct intel_c20pll_state
mtl_c20_hdmi_25_175 = {
static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
.link_bit_rate = 27000,
- .clock = 27000,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -1574,7 +1565,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_27_0
= {
static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
.link_bit_rate = 74250,
- .clock = 74250,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -1600,7 +1590,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_74_25
= {
static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
.link_bit_rate = 148500,
- .clock = 148500,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -1626,7 +1615,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_148_5
= {
static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
.link_bit_rate = 594000,
- .clock = 594000,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -1652,7 +1640,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 =
{
static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
.link_bit_rate = 300,
- .clock = 166670,
.tx = { 0xbe98, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x, /* tx cfg2 */
@@ -1678,7
