Re: [PATCH v2] drm/i915/mtl: Add fake PCH for Meteor Lake

2023-12-21 Thread Kalvala, Haridhar 



On 12/21/2023 3:41 AM, Matt Roper wrote:

On Wed, Dec 20, 2023 at 12:22:33AM +0530, Haridhar Kalvala wrote:

Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.

On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC die in this case), unlike many past
platforms where the SDE was on a separate PCH die. The code is (badly)
structured today in a way that assumes the SDE is always on the PCH for
modern platforms, so on platforms where we don't actually need to identify
the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as
MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows
us to avoid restructuring a bunch of the code.we've been assigning a
"fake PCH" as a quick hack that allows us to avoid restructuring a bunch
of the code.

Removed unused macros of LNL amd MTL as well.

v2: Reorder PCH_MTL conditional check (Matt Roper)
 Reverting to PCH_MTL for PICA interrupt(Matt Roper)

Signed-off-by: Haridhar Kalvala 

Reviewed-by: Matt Roper 

Thank you Matt.

---
  drivers/gpu/drm/i915/display/intel_backlight.c   |  2 +-
  drivers/gpu/drm/i915/display/intel_bios.c|  3 +--
  drivers/gpu/drm/i915/display/intel_cdclk.c   |  6 +++---
  drivers/gpu/drm/i915/display/intel_display_irq.c |  2 +-
  drivers/gpu/drm/i915/display/intel_gmbus.c   |  5 +
  drivers/gpu/drm/i915/display/intel_hotplug_irq.c |  6 ++
  drivers/gpu/drm/i915/display/intel_pps.c |  2 +-
  drivers/gpu/drm/i915/soc/intel_pch.c | 16 
  drivers/gpu/drm/i915/soc/intel_pch.h |  6 +-
  9 files changed, 19 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c 
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 612d4cd9dacb..696ae59874a9 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct 
drm_i915_private *i915, int
  
  	if (controller == 1 &&

INTEL_PCH_TYPE(i915) >= PCH_ICP &&
-   INTEL_PCH_TYPE(i915) < PCH_MTP)
+   INTEL_PCH_TYPE(i915) <= PCH_ADP)
return intel_de_read(i915, SOUTH_CHICKEN1) & 
ICP_SECOND_PPS_IO_SELECT;
  
  	return true;

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index aa169b0055e9..0e61e424802e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2204,8 +2204,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 
vbt_pin)
if (IS_DGFX(i915))
return vbt_pin;
  
-	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||

-   IS_ALDERLAKE_P(i915)) {
+   if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c985ebb6831a..b251a71092dd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3467,15 +3467,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
  {
u32 freq;
  
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)

-   freq = dg1_rawclk(dev_priv);
-   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
+   if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
/*
 * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
 * "RAWCLK_FREQ defaults to the values for 38.4 and does
 * not need to be programmed."
 */
freq = 38400;
+   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+   freq = dg1_rawclk(dev_priv);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a7d8f3fc98de..6964f4b95865 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -986,7 +986,7 @@ static void gen8_read_and_ack_pch_irqs(struct 
drm_i915_private *i915, u32 *pch_i
 * their flags both in the PICA and SDE IIR.
 */
if (*pch_iir & SDE_PICAINTERRUPT) {
-   drm_WARN_ON(>drm, INTEL_PCH_TYPE(i915) < PCH_MTP);
+   drm_WARN_ON(>drm, INTEL_PCH_TYPE(i915) < PCH_MTL);
  
  		pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0);

*pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c 
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 40d7b6f3f489..854566ba5414 100644
---

Re: [PATCH v2] drm/i915/mtl: Add fake PCH for Meteor Lake

2023-12-20 Thread Matt Roper 
On Wed, Dec 20, 2023 at 12:22:33AM +0530, Haridhar Kalvala wrote:
> Correct the implementation trying to detect MTL PCH with
> the MTL fake PCH id.
> 
> On MTL, both the North Display (NDE) and South Display (SDE) functionality
> reside on the same die (the SoC die in this case), unlike many past
> platforms where the SDE was on a separate PCH die. The code is (badly)
> structured today in a way that assumes the SDE is always on the PCH for
> modern platforms, so on platforms where we don't actually need to identify
> the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as
> MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows
> us to avoid restructuring a bunch of the code.we've been assigning a
> "fake PCH" as a quick hack that allows us to avoid restructuring a bunch
> of the code.
> 
> Removed unused macros of LNL amd MTL as well.
> 
> v2: Reorder PCH_MTL conditional check (Matt Roper)
> Reverting to PCH_MTL for PICA interrupt(Matt Roper)
> 
> Signed-off-by: Haridhar Kalvala 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/display/intel_backlight.c   |  2 +-
>  drivers/gpu/drm/i915/display/intel_bios.c|  3 +--
>  drivers/gpu/drm/i915/display/intel_cdclk.c   |  6 +++---
>  drivers/gpu/drm/i915/display/intel_display_irq.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_gmbus.c   |  5 +
>  drivers/gpu/drm/i915/display/intel_hotplug_irq.c |  6 ++
>  drivers/gpu/drm/i915/display/intel_pps.c |  2 +-
>  drivers/gpu/drm/i915/soc/intel_pch.c | 16 
>  drivers/gpu/drm/i915/soc/intel_pch.h |  6 +-
>  9 files changed, 19 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c 
> b/drivers/gpu/drm/i915/display/intel_backlight.c
> index 612d4cd9dacb..696ae59874a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct 
> drm_i915_private *i915, int
>  
>   if (controller == 1 &&
>   INTEL_PCH_TYPE(i915) >= PCH_ICP &&
> - INTEL_PCH_TYPE(i915) < PCH_MTP)
> + INTEL_PCH_TYPE(i915) <= PCH_ADP)
>   return intel_de_read(i915, SOUTH_CHICKEN1) & 
> ICP_SECOND_PPS_IO_SELECT;
>  
>   return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index aa169b0055e9..0e61e424802e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2204,8 +2204,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 
> vbt_pin)
>   if (IS_DGFX(i915))
>   return vbt_pin;
>  
> - if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
> - IS_ALDERLAKE_P(i915)) {
> + if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
>   ddc_pin_map = adlp_ddc_pin_map;
>   n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
>   } else if (IS_ALDERLAKE_S(i915)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c985ebb6831a..b251a71092dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3467,15 +3467,15 @@ u32 intel_read_rawclk(struct drm_i915_private 
> *dev_priv)
>  {
>   u32 freq;
>  
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> - freq = dg1_rawclk(dev_priv);
> - else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
>   /*
>* MTL always uses a 38.4 MHz rawclk.  The bspec tells us
>* "RAWCLK_FREQ defaults to the values for 38.4 and does
>* not need to be programmed."
>*/
>   freq = 38400;
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> + freq = dg1_rawclk(dev_priv);
>   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
>   freq = cnp_rawclk(dev_priv);
>   else if (HAS_PCH_SPLIT(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index a7d8f3fc98de..6964f4b95865 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -986,7 +986,7 @@ static void gen8_read_and_ack_pch_irqs(struct 
> drm_i915_private *i915, u32 *pch_i
>* their flags both in the PICA and SDE IIR.
>*/
>   if (*pch_iir & SDE_PICAINTERRUPT) {
> - drm_WARN_ON(>drm, INTEL_PCH_TYPE(i915) < PCH_MTP);
> + drm_WARN_ON(>drm, INTEL_PCH_TYPE(i915) < PCH_MTL);
>  
>   pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0);
>   *pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR);
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c 
>

[PATCH v2] drm/i915/mtl: Add fake PCH for Meteor Lake

2023-12-19 Thread Haridhar Kalvala 
Correct the implementation trying to detect MTL PCH with
the MTL fake PCH id.

On MTL, both the North Display (NDE) and South Display (SDE) functionality
reside on the same die (the SoC die in this case), unlike many past
platforms where the SDE was on a separate PCH die. The code is (badly)
structured today in a way that assumes the SDE is always on the PCH for
modern platforms, so on platforms where we don't actually need to identify
the PCH to figure out how the SDE behaves (i.e., all DG1/2 GPUs as well as
MTL and LNL),we've been assigning a "fake PCH" as a quickhack that allows
us to avoid restructuring a bunch of the code.we've been assigning a
"fake PCH" as a quick hack that allows us to avoid restructuring a bunch
of the code.

Removed unused macros of LNL amd MTL as well.

v2: Reorder PCH_MTL conditional check (Matt Roper)
Reverting to PCH_MTL for PICA interrupt(Matt Roper)

Signed-off-by: Haridhar Kalvala 
---
 drivers/gpu/drm/i915/display/intel_backlight.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_bios.c|  3 +--
 drivers/gpu/drm/i915/display/intel_cdclk.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_display_irq.c |  2 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c   |  5 +
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c |  6 ++
 drivers/gpu/drm/i915/display/intel_pps.c |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c | 16 
 drivers/gpu/drm/i915/soc/intel_pch.h |  6 +-
 9 files changed, 19 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c 
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 612d4cd9dacb..696ae59874a9 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct 
drm_i915_private *i915, int
 
if (controller == 1 &&
INTEL_PCH_TYPE(i915) >= PCH_ICP &&
-   INTEL_PCH_TYPE(i915) < PCH_MTP)
+   INTEL_PCH_TYPE(i915) <= PCH_ADP)
return intel_de_read(i915, SOUTH_CHICKEN1) & 
ICP_SECOND_PPS_IO_SELECT;
 
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index aa169b0055e9..0e61e424802e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2204,8 +2204,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 
vbt_pin)
if (IS_DGFX(i915))
return vbt_pin;
 
-   if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
-   IS_ALDERLAKE_P(i915)) {
+   if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c985ebb6831a..b251a71092dd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3467,15 +3467,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 {
u32 freq;
 
-   if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
-   freq = dg1_rawclk(dev_priv);
-   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
+   if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
/*
 * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
 * "RAWCLK_FREQ defaults to the values for 38.4 and does
 * not need to be programmed."
 */
freq = 38400;
+   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+   freq = dg1_rawclk(dev_priv);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a7d8f3fc98de..6964f4b95865 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -986,7 +986,7 @@ static void gen8_read_and_ack_pch_irqs(struct 
drm_i915_private *i915, u32 *pch_i
 * their flags both in the PICA and SDE IIR.
 */
if (*pch_iir & SDE_PICAINTERRUPT) {
-   drm_WARN_ON(>drm, INTEL_PCH_TYPE(i915) < PCH_MTP);
+   drm_WARN_ON(>drm, INTEL_PCH_TYPE(i915) < PCH_MTL);
 
pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0);
*pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c 
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 40d7b6f3f489..854566ba5414 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -155,7 +155,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct