RE: [PATCH 3/3] drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_state
Hi.
> -Original Message-
> From: Intel-gfx On Behalf Of
> Sripada,
> Radhakrishna
> Sent: Friday, December 8, 2023 9:30 PM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 3/3] drm/i915/mtl: Rename the link_bit_rate to clock in
> C20
> pll_state
>
> Thank you for the review. With clean CI pushed the patches upstream.
It seems these patches are causing some issues on certain MTL system and need
to be re-thought?
Mika, Imre?
Should we revert or fix?
>
> Regards,
> Radhakrishna Sripada
>
> > -Original Message-
> > From: Kahola, Mika
> > Sent: Friday, December 8, 2023 4:01 AM
> > To: Sripada, Radhakrishna ; intel-
> > g...@lists.freedesktop.org
> > Cc: Taylor, Clinton A
> > Subject: RE: [PATCH 3/3] drm/i915/mtl: Rename the link_bit_rate to
> > clock in C20 pll_state
> >
> > > -Original Message-
> > > From: Sripada, Radhakrishna
> > > Sent: Friday, December 8, 2023 12:10 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Sripada, Radhakrishna ; Taylor,
> > > Clinton A
> > ; Kahola, Mika
> > >
> > > Subject: [PATCH 3/3] drm/i915/mtl: Rename the link_bit_rate to clock
> > > in C20
> > pll_state
> > >
> > > With the cleanup of the misleading clock value to avoid extra
> > > calculations to
> > convert between link_bit_rate and clock, use one
> > > standard "clock" field for the c20 pll which works with
> > > crtc_state->port_clock
> > field.
> > >
> > > Cc: Clint Taylor
> > > Cc: Mika Kahola
> >
> > Reviewed-by: Mika Kahola
> >
> > > Signed-off-by: Radhakrishna Sripada
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 42 +--
> > > .../drm/i915/display/intel_display_types.h| 2 +-
> > > 2 files changed, 22 insertions(+), 22 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > index d518b55d5150..4e6ea71ff629 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > @@ -745,7 +745,7 @@ static const struct intel_c10pll_state * const
> > mtl_c10_edp_tables[] = {
> > >
> > > /* C20 basic DP 1.4 tables */
> > > static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> > > - .link_bit_rate = 162000,
> > > + .clock = 162000,
> > > .tx = { 0xbe88, /* tx cfg0 */
> > > 0x5800, /* tx cfg1 */
> > > 0x, /* tx cfg2 */
> > > @@ -770,7 +770,7 @@ static const struct intel_c20pll_state
> > > mtl_c20_dp_rbr =
> > { };
> > >
> > > static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> > > - .link_bit_rate = 27,
> > > + .clock = 27,
> > > .tx = { 0xbe88, /* tx cfg0 */
> > > 0x4800, /* tx cfg1 */
> > > 0x, /* tx cfg2 */
> > > @@ -795,7 +795,7 @@ static const struct intel_c20pll_state
> > > mtl_c20_dp_hbr1
> > = { };
> > >
> > > static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> > > - .link_bit_rate = 54,
> > > + .clock = 54,
> > > .tx = { 0xbe88, /* tx cfg0 */
> > > 0x4800, /* tx cfg1 */
> > > 0x, /* tx cfg2 */
> > > @@ -820,7 +820,7 @@ static const struct intel_c20pll_state
> > > mtl_c20_dp_hbr2
> > = { };
> > >
> > > static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> > > - .link_bit_rate = 81,
> > > + .clock = 81,
> > > .tx = { 0xbe88, /* tx cfg0 */
> > > 0x4800, /* tx cfg1 */
> > > 0x, /* tx cfg2 */
> > > @@ -846,7 +846,7 @@ static const struct intel_c20pll_state
> > > mtl_c20_dp_hbr3
> > = {
> > >
> > > /* C20 basic DP 2.0 tables */
> > > static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> > > - .link_bit_rate = 100, /* 10 Gbps */
> > > + .clock = 100, /* 10 Gbps */
> > > .tx = { 0xbe21, /* tx cfg0 */
> > > 0x4800, /* tx cfg1 */
> > > 0x, /* tx cfg2 */
> > > @@ -870,7 +870,7 @@ static const struct intel_c20pll_state
> > mtl_c20_dp_uhbr10 = { };
> > >
> > > static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> > > - .link_bit_rate = 135, /* 13.5 Gbps */
> > > + .clock = 135, /* 13.5 Gbps */
> > > .tx = { 0xbea0, /* tx cfg0 */
> > > 0x4800, /* tx cfg1 */
> > > 0x, /* tx cfg2 */
> > > @@ -895,7 +895,7 @@ static const struct intel_c20pll_state
> > mtl_c20_dp_uhbr13_5 = { };
> > >
> > > static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> > > - .link_bit_rate = 200, /* 20 Gbps */
> > > + .clock = 200, /* 20 Gbps */
> > > .tx = { 0xbe20, /* tx cfg0 */
> > > 0x4800, /* tx cfg1 */
> > > 0x, /* tx cfg2 */
> > > @@ -1514,7 +1514,7 @@ static const struct intel_c10pll_state * const
> > mtl_c10_hdmi_tables[] = { };
> > >
> > > static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> > > - .link_bit_rate = 25175,
> > > + .clock = 25175,
> > > .tx = { 0xbe88, /* tx cfg0 */
> > > 0x9800, /* tx cfg1 */
> > > 0x, /* tx cfg2 */
> > > @@ -1539,7
RE: [PATCH 3/3] drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_state
Thank you for the review. With clean CI pushed the patches upstream.
Regards,
Radhakrishna Sripada
> -Original Message-
> From: Kahola, Mika
> Sent: Friday, December 8, 2023 4:01 AM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Cc: Taylor, Clinton A
> Subject: RE: [PATCH 3/3] drm/i915/mtl: Rename the link_bit_rate to clock in
> C20
> pll_state
>
> > -Original Message-
> > From: Sripada, Radhakrishna
> > Sent: Friday, December 8, 2023 12:10 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Sripada, Radhakrishna ; Taylor, Clinton
> > A
> ; Kahola, Mika
> >
> > Subject: [PATCH 3/3] drm/i915/mtl: Rename the link_bit_rate to clock in C20
> pll_state
> >
> > With the cleanup of the misleading clock value to avoid extra calculations
> > to
> convert between link_bit_rate and clock, use one
> > standard "clock" field for the c20 pll which works with
> > crtc_state->port_clock
> field.
> >
> > Cc: Clint Taylor
> > Cc: Mika Kahola
>
> Reviewed-by: Mika Kahola
>
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 42 +--
> > .../drm/i915/display/intel_display_types.h| 2 +-
> > 2 files changed, 22 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index d518b55d5150..4e6ea71ff629 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -745,7 +745,7 @@ static const struct intel_c10pll_state * const
> mtl_c10_edp_tables[] = {
> >
> > /* C20 basic DP 1.4 tables */
> > static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> > - .link_bit_rate = 162000,
> > + .clock = 162000,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x5800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> > @@ -770,7 +770,7 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr =
> { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> > - .link_bit_rate = 27,
> > + .clock = 27,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> > @@ -795,7 +795,7 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1
> = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> > - .link_bit_rate = 54,
> > + .clock = 54,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> > @@ -820,7 +820,7 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2
> = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> > - .link_bit_rate = 81,
> > + .clock = 81,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> > @@ -846,7 +846,7 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3
> = {
> >
> > /* C20 basic DP 2.0 tables */
> > static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> > - .link_bit_rate = 100, /* 10 Gbps */
> > + .clock = 100, /* 10 Gbps */
> > .tx = { 0xbe21, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> > @@ -870,7 +870,7 @@ static const struct intel_c20pll_state
> mtl_c20_dp_uhbr10 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> > - .link_bit_rate = 135, /* 13.5 Gbps */
> > + .clock = 135, /* 13.5 Gbps */
> > .tx = { 0xbea0, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> > @@ -895,7 +895,7 @@ static const struct intel_c20pll_state
> mtl_c20_dp_uhbr13_5 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> > - .link_bit_rate = 200, /* 20 Gbps */
> > + .clock = 200, /* 20 Gbps */
> > .tx = { 0xbe20, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> > @@ -1514,7 +1514,7 @@ static const struct intel_c10pll_state * const
> mtl_c10_hdmi_tables[] = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> > - .link_bit_rate = 25175,
> > + .clock = 25175,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x9800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> > @@ -1539,7 +1539,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_25_175 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> > - .link_bit_rate = 27000,
> > + .clock = 27000,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x9800, /* tx cfg1 */
> > 0x, /* tx cfg2 */
> > @@ -1564,7 +1564,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_27_0 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> > - .link_bit_rate = 74250,
> > + .clock = 74250,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x9800, /* tx
RE: [PATCH 3/3] drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_state
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Friday, December 8, 2023 12:10 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sripada, Radhakrishna ; Taylor, Clinton A
> ; Kahola, Mika
>
> Subject: [PATCH 3/3] drm/i915/mtl: Rename the link_bit_rate to clock in C20
> pll_state
>
> With the cleanup of the misleading clock value to avoid extra calculations to
> convert between link_bit_rate and clock, use one
> standard "clock" field for the c20 pll which works with
> crtc_state->port_clock field.
>
> Cc: Clint Taylor
> Cc: Mika Kahola
Reviewed-by: Mika Kahola
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 42 +--
> .../drm/i915/display/intel_display_types.h| 2 +-
> 2 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index d518b55d5150..4e6ea71ff629 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -745,7 +745,7 @@ static const struct intel_c10pll_state * const
> mtl_c10_edp_tables[] = {
>
> /* C20 basic DP 1.4 tables */
> static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> - .link_bit_rate = 162000,
> + .clock = 162000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x5800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -770,7 +770,7 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> };
>
> static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> - .link_bit_rate = 27,
> + .clock = 27,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -795,7 +795,7 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 =
> { };
>
> static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> - .link_bit_rate = 54,
> + .clock = 54,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -820,7 +820,7 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 =
> { };
>
> static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> - .link_bit_rate = 81,
> + .clock = 81,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -846,7 +846,7 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
>
> /* C20 basic DP 2.0 tables */
> static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> - .link_bit_rate = 100, /* 10 Gbps */
> + .clock = 100, /* 10 Gbps */
> .tx = { 0xbe21, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -870,7 +870,7 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10
> = { };
>
> static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> - .link_bit_rate = 135, /* 13.5 Gbps */
> + .clock = 135, /* 13.5 Gbps */
> .tx = { 0xbea0, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -895,7 +895,7 @@ static const struct intel_c20pll_state
> mtl_c20_dp_uhbr13_5 = { };
>
> static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> - .link_bit_rate = 200, /* 20 Gbps */
> + .clock = 200, /* 20 Gbps */
> .tx = { 0xbe20, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -1514,7 +1514,7 @@ static const struct intel_c10pll_state * const
> mtl_c10_hdmi_tables[] = { };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> - .link_bit_rate = 25175,
> + .clock = 25175,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -1539,7 +1539,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_25_175 = { };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> - .link_bit_rate = 27000,
> + .clock = 27000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -1564,7 +1564,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_27_0 = { };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> - .link_bit_rate = 74250,
> + .clock = 74250,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -1589,7 +1589,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_74_25 = { };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> - .link_bit_rate = 148500,
> + .clock = 148500,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x, /* tx cfg2 */
> @@ -1614,7 +1614,7 @@ static const struct intel_c20pll_state
> mtl_c20_hdmi_148_5 = { };
>
> static
