Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-08 Thread Daniel Vetter
On Fri, Sep 05, 2014 at 09:54:13PM +0300, ville.syrj...@linux.intel.com wrote:
 From: Ville Syrjälä ville.syrj...@linux.intel.com
 
 830 is very unhappy of the watermark value is too low (indicating a very
 high watermark in fact, ie. memory fetch will occur with an almost full
 FIFO). Limit the watermark value to at least 8 cache lines.
 
 That also matches the burst size we use on most platforms. BSpec seems
 to indicate we should limit the watermark to 'burst size + 1'. But on
 gen4 we already use a hardcoded 8 as the watermark value (as the spec
 says we should), so just use 8 as the limit on gen2/3 as well.
 
 Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com

Queued for -next, thanks for the patch. And since this goes in through
-next the potential risk to other platforms is imo manageable. And we've
had other people complaint about serious underrun troubles on e.g.
underpowered i915gm atoms with big screens. Maybe this helps there like
for the i830m.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-08 Thread Thomas Richter

Am 08.09.2014 09:39, schrieb Daniel Vetter:

On Fri, Sep 05, 2014 at 09:54:13PM +0300, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä ville.syrj...@linux.intel.com

830 is very unhappy of the watermark value is too low (indicating a very
high watermark in fact, ie. memory fetch will occur with an almost full
FIFO). Limit the watermark value to at least 8 cache lines.

That also matches the burst size we use on most platforms. BSpec seems
to indicate we should limit the watermark to 'burst size + 1'. But on
gen4 we already use a hardcoded 8 as the watermark value (as the spec
says we should), so just use 8 as the limit on gen2/3 as well.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com


Queued for -next, thanks for the patch. And since this goes in through
-next the potential risk to other platforms is imo manageable. And we've
had other people complaint about serious underrun troubles on e.g.
underpowered i915gm atoms with big screens. Maybe this helps there like
for the i830m.


Thanks, I'll give -next a spin on my 830 and 945 based machines. I don't 
think I have a 845 here, though.


Greetings,
Thomas


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Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-06 Thread Ville Syrjälä
On Fri, Sep 05, 2014 at 09:03:11PM +0200, Thomas Richter wrote:
 On 05.09.2014 20:54, ville.syrj...@linux.intel.com wrote:
  From: Ville Syrjälä ville.syrj...@linux.intel.com
 
  830 is very unhappy of the watermark value is too low (indicating a very
  high watermark in fact, ie. memory fetch will occur with an almost full
  FIFO). Limit the watermark value to at least 8 cache lines.
 
  That also matches the burst size we use on most platforms. BSpec seems
  to indicate we should limit the watermark to 'burst size + 1'. But on
  gen4 we already use a hardcoded 8 as the watermark value (as the spec
  says we should), so just use 8 as the limit on gen2/3 as well.
 
 /* snip */
 
 That's certainly one way to fix it. Nothing against it. It might be more 
 conservative to make this fix only in the calling context of the 830 and 
 845 specific functions as I don't know whether the other chipsets have 
 similar issues. I.e. one level up in the call-chain.
 
 This being said, I can certainly confirm that the suggested modification 
 works on i830.
 
 One way or another, it seems to me that drm-intel-nightly which I pulled 
 had a couple of more serious issues. I didn't even get X running, and 
 monitor detection did not seem to work reliable, too. I had the same 
 kind of instability on the external monitor for the console Ville's 
 patches fixed so nicely, so it seems to me that there is something else 
 that is missing. The new DVO code was definitely there, I checked that.

The DVO 2x clock fix was missing. I posted a new version. But I think
that should only affect the DVO output and not the VGA output. Anyway on
my 830 nightly with those two patches is pretty damn good. I'm going to
assume this is the first time in history when 830 works properly in linux
(well, excluding all the features we still haven't even implemented in
the driver). Only took 14 years or so to get there :P

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-06 Thread Thomas Richter

On 06.09.2014 19:33, Ville Syrjälä wrote:


The DVO 2x clock fix was missing. I posted a new version. But I think
that should only affect the DVO output and not the VGA output. Anyway on
my 830 nightly with those two patches is pretty damn good. I'm going to
assume this is the first time in history when 830 works properly in linux
(well, excluding all the features we still haven't even implemented in
the driver). Only took 14 years or so to get there :P


Many thanks for all that, it's really appreciated. (-: Still, what I did 
last week is to clone drm-intel-nightly and tested what I got this way. 
Is this not the recommended way to test whether the patches are in?


Greetings and have a nice weekend,

Thomas




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Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-05 Thread Thomas Richter

On 05.09.2014 20:54, ville.syrj...@linux.intel.com wrote:

From: Ville Syrjälä ville.syrj...@linux.intel.com

830 is very unhappy of the watermark value is too low (indicating a very
high watermark in fact, ie. memory fetch will occur with an almost full
FIFO). Limit the watermark value to at least 8 cache lines.

That also matches the burst size we use on most platforms. BSpec seems
to indicate we should limit the watermark to 'burst size + 1'. But on
gen4 we already use a hardcoded 8 as the watermark value (as the spec
says we should), so just use 8 as the limit on gen2/3 as well.


/* snip */

That's certainly one way to fix it. Nothing against it. It might be more 
conservative to make this fix only in the calling context of the 830 and 
845 specific functions as I don't know whether the other chipsets have 
similar issues. I.e. one level up in the call-chain.


This being said, I can certainly confirm that the suggested modification 
works on i830.


One way or another, it seems to me that drm-intel-nightly which I pulled 
had a couple of more serious issues. I didn't even get X running, and 
monitor detection did not seem to work reliable, too. I had the same 
kind of instability on the external monitor for the console Ville's 
patches fixed so nicely, so it seems to me that there is something else 
that is missing. The new DVO code was definitely there, I checked that.


Thanks,
Thomas


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