Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: reorder dpll_info members

2018-03-27 Thread Rodrigo Vivi 
On Fri, Mar 23, 2018 at 06:25:52PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 20, 2018 at 03:06:37PM -0700, Lucas De Marchi wrote:
> > Remove 4-bytes hole in this struct an reorder tables accordingly. This
> > also changes the last element of the tables to be more future-proof.
> > 
> > Signed-off-by: Lucas De Marchi 
> > ---
> >  drivers/gpu/drm/i915/intel_dpll_mgr.c | 48 
> > +--
> >  drivers/gpu/drm/i915/intel_dpll_mgr.h | 13 ++
> >  2 files changed, 32 insertions(+), 29 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index bda69e1ccd76..d5e114e9660b 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -1908,9 +1908,9 @@ struct intel_dpll_mgr {
> >  };
> >  
> >  static const struct dpll_info pch_plls[] = {
> > -   { "PCH DPLL A", DPLL_ID_PCH_PLL_A, _pch_dpll_funcs, 0 },
> > -   { "PCH DPLL B", DPLL_ID_PCH_PLL_B, _pch_dpll_funcs, 0 },
> > -   { NULL, -1, NULL, 0 },
> > +   { "PCH DPLL A", _pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
> > +   { "PCH DPLL B", _pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
> 
> I usually prefer named initializer to be used pretty much everywhere.
> 
> Patches 6-7 are
> Reviewed-by: Ville Syrjälä 
> regardless.

pushed to dinq. Thanks for patches and reviews.

> 
> > +   { },
> >  };
> >  
> >  static const struct intel_dpll_mgr pch_pll_mgr = {
> > @@ -1920,13 +1920,13 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
> >  };
> >  
> >  static const struct dpll_info hsw_plls[] = {
> > -   { "WRPLL 1",DPLL_ID_WRPLL1, _ddi_wrpll_funcs, 0 },
> > -   { "WRPLL 2",DPLL_ID_WRPLL2, _ddi_wrpll_funcs, 0 },
> > -   { "SPLL",   DPLL_ID_SPLL,   _ddi_spll_funcs,  0 },
> > -   { "LCPLL 810",  DPLL_ID_LCPLL_810,  _ddi_lcpll_funcs, 
> > INTEL_DPLL_ALWAYS_ON },
> > -   { "LCPLL 1350", DPLL_ID_LCPLL_1350, _ddi_lcpll_funcs, 
> > INTEL_DPLL_ALWAYS_ON },
> > -   { "LCPLL 2700", DPLL_ID_LCPLL_2700, _ddi_lcpll_funcs, 
> > INTEL_DPLL_ALWAYS_ON },
> > -   { NULL, -1, NULL, },
> > +   { "WRPLL 1",_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 },
> > +   { "WRPLL 2",_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 },
> > +   { "SPLL",   _ddi_spll_funcs,  DPLL_ID_SPLL,   0 },
> > +   { "LCPLL 810",  _ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  
> > INTEL_DPLL_ALWAYS_ON },
> > +   { "LCPLL 1350", _ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, 
> > INTEL_DPLL_ALWAYS_ON },
> > +   { "LCPLL 2700", _ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, 
> > INTEL_DPLL_ALWAYS_ON },
> > +   { },
> >  };
> >  
> >  static const struct intel_dpll_mgr hsw_pll_mgr = {
> > @@ -1936,11 +1936,11 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
> >  };
> >  
> >  static const struct dpll_info skl_plls[] = {
> > -   { "DPLL 0", DPLL_ID_SKL_DPLL0, _ddi_dpll0_funcs, 
> > INTEL_DPLL_ALWAYS_ON },
> > -   { "DPLL 1", DPLL_ID_SKL_DPLL1, _ddi_pll_funcs,   0 },
> > -   { "DPLL 2", DPLL_ID_SKL_DPLL2, _ddi_pll_funcs,   0 },
> > -   { "DPLL 3", DPLL_ID_SKL_DPLL3, _ddi_pll_funcs,   0 },
> > -   { NULL, -1, NULL, },
> > +   { "DPLL 0", _ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, 
> > INTEL_DPLL_ALWAYS_ON },
> > +   { "DPLL 1", _ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },
> > +   { "DPLL 2", _ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },
> > +   { "DPLL 3", _ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },
> > +   { },
> >  };
> >  
> >  static const struct intel_dpll_mgr skl_pll_mgr = {
> > @@ -1950,10 +1950,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
> >  };
> >  
> >  static const struct dpll_info bxt_plls[] = {
> > -   { "PORT PLL A", DPLL_ID_SKL_DPLL0, _ddi_pll_funcs, 0 },
> > -   { "PORT PLL B", DPLL_ID_SKL_DPLL1, _ddi_pll_funcs, 0 },
> > -   { "PORT PLL C", DPLL_ID_SKL_DPLL2, _ddi_pll_funcs, 0 },
> > -   { NULL, -1, NULL, },
> > +   { "PORT PLL A", _ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> > +   { "PORT PLL B", _ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> > +   { "PORT PLL C", _ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> > +   { },
> >  };
> >  
> >  static const struct intel_dpll_mgr bxt_pll_mgr = {
> > @@ -2387,10 +2387,10 @@ static const struct intel_shared_dpll_funcs 
> > cnl_ddi_pll_funcs = {
> >  };
> >  
> >  static const struct dpll_info cnl_plls[] = {
> > -   { "DPLL 0", DPLL_ID_SKL_DPLL0, _ddi_pll_funcs, 0 },
> > -   { "DPLL 1", DPLL_ID_SKL_DPLL1, _ddi_pll_funcs, 0 },
> > -   { "DPLL 2", DPLL_ID_SKL_DPLL2, _ddi_pll_funcs, 0 },
> > -   { NULL, -1, NULL, },
> > +   { "DPLL 0", _ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> > +   { "DPLL 1", _ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> > +   { "DPLL 2", _ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> > +   { },
> >  };
> >  
> >  static const struct intel_dpll_mgr cnl_pll_mgr = {
> > @@ -2430,7 +2430,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> >  
> > dpll_info = dpll_mgr->dpll_info;
> >  
> > -   for (i = 0; dpll_info[i].id >= 0; i++) {
> > +   for (i = 0;

Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: reorder dpll_info members

2018-03-23 Thread Ville Syrjälä 
On Tue, Mar 20, 2018 at 03:06:37PM -0700, Lucas De Marchi wrote:
> Remove 4-bytes hole in this struct an reorder tables accordingly. This
> also changes the last element of the tables to be more future-proof.
> 
> Signed-off-by: Lucas De Marchi 
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 48 
> +--
>  drivers/gpu/drm/i915/intel_dpll_mgr.h | 13 ++
>  2 files changed, 32 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index bda69e1ccd76..d5e114e9660b 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1908,9 +1908,9 @@ struct intel_dpll_mgr {
>  };
>  
>  static const struct dpll_info pch_plls[] = {
> - { "PCH DPLL A", DPLL_ID_PCH_PLL_A, _pch_dpll_funcs, 0 },
> - { "PCH DPLL B", DPLL_ID_PCH_PLL_B, _pch_dpll_funcs, 0 },
> - { NULL, -1, NULL, 0 },
> + { "PCH DPLL A", _pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
> + { "PCH DPLL B", _pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },

I usually prefer named initializer to be used pretty much everywhere.

Patches 6-7 are
Reviewed-by: Ville Syrjälä 
regardless.

> + { },
>  };
>  
>  static const struct intel_dpll_mgr pch_pll_mgr = {
> @@ -1920,13 +1920,13 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
>  };
>  
>  static const struct dpll_info hsw_plls[] = {
> - { "WRPLL 1",DPLL_ID_WRPLL1, _ddi_wrpll_funcs, 0 },
> - { "WRPLL 2",DPLL_ID_WRPLL2, _ddi_wrpll_funcs, 0 },
> - { "SPLL",   DPLL_ID_SPLL,   _ddi_spll_funcs,  0 },
> - { "LCPLL 810",  DPLL_ID_LCPLL_810,  _ddi_lcpll_funcs, 
> INTEL_DPLL_ALWAYS_ON },
> - { "LCPLL 1350", DPLL_ID_LCPLL_1350, _ddi_lcpll_funcs, 
> INTEL_DPLL_ALWAYS_ON },
> - { "LCPLL 2700", DPLL_ID_LCPLL_2700, _ddi_lcpll_funcs, 
> INTEL_DPLL_ALWAYS_ON },
> - { NULL, -1, NULL, },
> + { "WRPLL 1",_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 },
> + { "WRPLL 2",_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 },
> + { "SPLL",   _ddi_spll_funcs,  DPLL_ID_SPLL,   0 },
> + { "LCPLL 810",  _ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  
> INTEL_DPLL_ALWAYS_ON },
> + { "LCPLL 1350", _ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, 
> INTEL_DPLL_ALWAYS_ON },
> + { "LCPLL 2700", _ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, 
> INTEL_DPLL_ALWAYS_ON },
> + { },
>  };
>  
>  static const struct intel_dpll_mgr hsw_pll_mgr = {
> @@ -1936,11 +1936,11 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
>  };
>  
>  static const struct dpll_info skl_plls[] = {
> - { "DPLL 0", DPLL_ID_SKL_DPLL0, _ddi_dpll0_funcs, 
> INTEL_DPLL_ALWAYS_ON },
> - { "DPLL 1", DPLL_ID_SKL_DPLL1, _ddi_pll_funcs,   0 },
> - { "DPLL 2", DPLL_ID_SKL_DPLL2, _ddi_pll_funcs,   0 },
> - { "DPLL 3", DPLL_ID_SKL_DPLL3, _ddi_pll_funcs,   0 },
> - { NULL, -1, NULL, },
> + { "DPLL 0", _ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, 
> INTEL_DPLL_ALWAYS_ON },
> + { "DPLL 1", _ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },
> + { "DPLL 2", _ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },
> + { "DPLL 3", _ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },
> + { },
>  };
>  
>  static const struct intel_dpll_mgr skl_pll_mgr = {
> @@ -1950,10 +1950,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
>  };
>  
>  static const struct dpll_info bxt_plls[] = {
> - { "PORT PLL A", DPLL_ID_SKL_DPLL0, _ddi_pll_funcs, 0 },
> - { "PORT PLL B", DPLL_ID_SKL_DPLL1, _ddi_pll_funcs, 0 },
> - { "PORT PLL C", DPLL_ID_SKL_DPLL2, _ddi_pll_funcs, 0 },
> - { NULL, -1, NULL, },
> + { "PORT PLL A", _ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> + { "PORT PLL B", _ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> + { "PORT PLL C", _ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> + { },
>  };
>  
>  static const struct intel_dpll_mgr bxt_pll_mgr = {
> @@ -2387,10 +2387,10 @@ static const struct intel_shared_dpll_funcs 
> cnl_ddi_pll_funcs = {
>  };
>  
>  static const struct dpll_info cnl_plls[] = {
> - { "DPLL 0", DPLL_ID_SKL_DPLL0, _ddi_pll_funcs, 0 },
> - { "DPLL 1", DPLL_ID_SKL_DPLL1, _ddi_pll_funcs, 0 },
> - { "DPLL 2", DPLL_ID_SKL_DPLL2, _ddi_pll_funcs, 0 },
> - { NULL, -1, NULL, },
> + { "DPLL 0", _ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> + { "DPLL 1", _ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> + { "DPLL 2", _ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> + { },
>  };
>  
>  static const struct intel_dpll_mgr cnl_pll_mgr = {
> @@ -2430,7 +2430,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>  
>   dpll_info = dpll_mgr->dpll_info;
>  
> - for (i = 0; dpll_info[i].id >= 0; i++) {
> + for (i = 0; dpll_info[i].name; i++) {
>   WARN_ON(i != dpll_info[i].id);
>   dev_priv->shared_dplls[i].info = _info[i];
>   }
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h 
> b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index