[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use (rev3)
== Series Details == Series: drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use (rev3) URL : https://patchwork.freedesktop.org/series/66551/ State : warning == Summary == $ dim checkpatch origin/drm-tip 966019d69514 drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use -:120: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #120: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:441: + struct mutex pin_mutex; total: 0 errors, 0 warnings, 1 checks, 97 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 02/23] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Quoting Lucas De Marchi (2019-08-23 09:20:34)
> From: Michel Thierry
>
> HCP/MFX power gating is disabled by default, turn it on for the vd units
> available. User space will also issue a MI_FORCE_WAKEUP properly to
> wake up proper subwell.
>
> During driver load, init_clock_gating happens after device_info_init_mmio
> read the vdbox disable fuse register, so only present vd units will have
> these enabled.
>
> BSpec: 14214
> HSDES: 1209977827
> Signed-off-by: Michel Thierry
> Reviewed-by: Lucas De Marchi
> Signed-off-by: Lucas De Marchi
> Reviewed-by: Tony Ye
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4
> drivers/gpu/drm/i915/intel_pm.c | 18 +-
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a092b34c269d..02e1ef10c47e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8615,6 +8615,10 @@ enum {
> #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
> #define GEN9_PWRGT_RENDER_STATUS_MASK(1 << 1)
>
> +#define POWERGATE_ENABLE _MMIO(0xa210)
> +#defineVDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3)
> +#defineVDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4)
> +
> #define GTFIFODBG _MMIO(0x12)
> #defineGT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
> #defineGT_FIFO_FREE_ENTRIES_CHV(0x7f << 13)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 75ee027abb80..d3ea193cd093 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9078,6 +9078,22 @@ static void icl_init_clock_gating(struct
> drm_i915_private *dev_priv)
>_MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
> }
>
> +static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> + u32 vd_pg_enable = 0;
> + unsigned int i;
> +
> + /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
> + for (i = 0; i < I915_MAX_VCS; i++) {
> + if (HAS_ENGINE(dev_priv, _VCS(i)))
> + vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
> + VDN_MFX_POWERGATE_ENABLE(i);
> + }
> +
> + I915_WRITE(POWERGATE_ENABLE,
> + I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
Is this display related at all?
-Chris
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for Fix i915_interrupt_info debugfs with display off on VLV
== Series Details == Series: Fix i915_interrupt_info debugfs with display off on VLV URL : https://patchwork.freedesktop.org/series/66604/ State : success == Summary == CI Bug Log - changes from CI_DRM_6882_full -> Patchwork_14381_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14381_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@reset-stress: - shard-iclb: [PASS][1] -> [FAIL][2] ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb5/igt@gem_...@reset-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-iclb2/igt@gem_...@reset-stress.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +9 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb3/igt@gem_exec_sched...@preemptive-hang-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-sliding: - shard-apl: [PASS][7] -> [FAIL][8] ([fdo#103232]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-apl6/igt@kms_cursor_...@pipe-a-cursor-128x128-sliding.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-128x128-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#103232]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-skl9/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#110741]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-skl10/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@all-pipes-single-move: - shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-apl3/igt@kms_cursor_leg...@all-pipes-single-move.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-apl1/igt@kms_cursor_leg...@all-pipes-single-move.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-hsw: [PASS][15] -> [FAIL][16] ([fdo#102670]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-hsw2/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-hsw4/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#105363]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-skl2/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([fdo#107713]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb2/igt@kms_f...@plain-flip-ts-check-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-iclb7/igt@kms_f...@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +7 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-skl4/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14381/shard-skl4/igt@kms_pipe_cr
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use (rev3)
== Series Details ==
Series: drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use (rev3)
URL : https://patchwork.freedesktop.org/series/66551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6885 -> Patchwork_14393
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14393:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-tgl-u/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_14393 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] /
[fdo#108569])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
- fi-bsw-kefka: [PASS][7] -> [INCOMPLETE][8] ([fdo#105876])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u2}:[DMESG-WARN][9] ([fdo#111600]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- {fi-tgl-u}: [INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-tgl-u/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][13] ([fdo#08]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@prime_v...@basic-busy-default.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14393/fi-icl-u3/igt@prime_v...@basic-busy-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (55 -> 47)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-sq
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/tgl: Introduce gen12 forcewake ranges
== Series Details == Series: series starting with [1/3] drm/i915/tgl: Introduce gen12 forcewake ranges URL : https://patchwork.freedesktop.org/series/66630/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/tgl: Introduce gen12 forcewake ranges +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block Commit: drm/i915/tgl: s/ss/eu fuse reading support Okay! Commit: drm/i915/tgl: Re-enable rc6 Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Only unwedge if we can reset first
Quoting Janusz Krzysztofik (2019-09-10 08:39:51) > Hi Chris, > > On Tuesday, September 10, 2019 12:55:36 AM CEST Chris Wilson wrote: > > @@ -854,7 +855,11 @@ static bool __intel_gt_unset_wedged(struct intel_gt > *gt) > > } > > spin_unlock_irqrestore(&timelines->lock, flags); > > > > - intel_gt_sanitize(gt, false); > > + ok = false; > > + if (!reset_clobbers_display(gt->i915)) > > + ok = __intel_gt_reset(gt, ALL_ENGINES) == 0; > > + if (!ok) > > + return false; > > Before your change, that code was executed inside intel_gt_sanitize(gt, > false) > which unfortunately didn't return any result. The same outcome could be > achieved by redefining intel_gt_sanitize() to return that result and saying: > > if (!intel_gt_sanitize(gt, false) > return false; > > Is there any specific reason for intel_gt_sanitize() returning void? The intent is that sanitize scrubs the leftover BIOS state, failure is not an option. The biggest change with respect to intel_gt_sanitize() is the game we play with reset_clobbers_display -- we need the reset, whereas in sanitize, the reset is good to have (but realistically we do not expect there to be any contexts to scrub and so can take the risk). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/tgl: Introduce gen12 forcewake ranges
== Series Details ==
Series: series starting with [1/3] drm/i915/tgl: Introduce gen12 forcewake
ranges
URL : https://patchwork.freedesktop.org/series/66630/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6885 -> Patchwork_14394
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/
Known issues
Here are the changes found in Patchwork_14394 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_render_linear_blits@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
* igt@i915_selftest@live_reset:
- fi-icl-u3: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@i915_selftest@live_reset.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-icl-u3/igt@i915_selftest@live_reset.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@debugfs_test@read_all_entries:
- {fi-tgl-u2}:[DMESG-WARN][9] ([fdo#111600]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u2}:[INCOMPLETE][11] ([fdo#111593]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-tgl-u2/igt@gem_exec_gttf...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-tgl-u2/igt@gem_exec_gttf...@basic.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][13] ([fdo#08]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/fi-icl-u3/igt@prime_v...@basic-busy-default.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14394/fi-icl-u3/igt@prime_v...@basic-busy-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Participating hosts (55 -> 47)
--
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
[Intel-gfx] [PATCH] drm/i915/gt: Only unwedge if we can reset first
Unwedging the GPU requires a successful GPU reset before we restore the
default submission, or else we may see residual context switch events
that we were not expecting.
v2: Pull in the special-case reset_clobbers_display, and explain why it
should be safe in the context of unwedging.
Reported-by: Janusz Krzysztofik
Signed-off-by: Chris Wilson
Cc: Janusz Krzysztofik
Cc: Daniele Ceraolo Spurio
Cc: Ville Syrjälä
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_reset.c | 30 ++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index ee52947eb31d..d3b1cdafd4c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -7,6 +7,7 @@
#include
#include
+#include "display/intel_display.h"
#include "display/intel_display_types.h"
#include "display/intel_overlay.h"
@@ -729,6 +730,28 @@ static void nop_submit_request(struct i915_request
*request)
intel_engine_queue_breadcrumbs(engine);
}
+static bool reset_clobbers_display(struct drm_i915_private *i915)
+{
+ struct intel_crtc *crtc;
+
+ if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
+ return false;
+
+ /*
+* While this appears racy, we should only be inspecting the display
+* state at runtime from inside a GPU reset, which will be serialized
+* with modesets on affected machines. For a full device reset,
+* we should already have cleared the active CRTC state in
+* intel_prepare_reset().
+*/
+ for_each_intel_crtc(&i915->drm, crtc) {
+ if (crtc->active)
+ return true;
+ }
+
+ return false;
+}
+
static void __intel_gt_set_wedged(struct intel_gt *gt)
{
struct intel_engine_cs *engine;
@@ -793,6 +816,7 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
struct intel_gt_timelines *timelines = >->timelines;
struct intel_timeline *tl;
unsigned long flags;
+ bool ok;
if (!test_bit(I915_WEDGED, >->reset.flags))
return true;
@@ -838,7 +862,11 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
}
spin_unlock_irqrestore(&timelines->lock, flags);
- intel_gt_sanitize(gt, false);
+ ok = false;
+ if (!reset_clobbers_display(gt->i915))
+ ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
+ if (!ok)
+ return false;
/*
* Undo nop_submit_request. We prevent all new i915 requests from
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/tgl: s/ss/eu fuse reading support
From: Daniele Ceraolo Spurio
Gen12 has dual-subslices (DSS), which compared to gen11 subslices have
some duplicated resources/paths. Although DSS behave similarly to 2
subslices, instead of splitting this and presenting userspace with bits
not directly representative of hardware resources, present userspace
with a subslice_mask made up of DSS bits instead.
v2: GEM_BUG_ON on mask size (Lionel)
Bspec: 29547
Bspec: 12247
Cc: Kelvin Gardiner
Cc: Tvrtko Ursulin
Cc: Lionel Landwerlin
CC: Radhakrishna Sripada
Cc: Michel Thierry #v1
Cc: Daniele Ceraolo Spurio
Cc: José Roberto de Souza
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: James Ausmus
Signed-off-by: Oscar Mateo
Signed-off-by: Sudeep Dutt
Signed-off-by: Stuart Summers
Signed-off-by: Mika Kuoppala
Acked-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +--
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.c | 83 ++--
include/uapi/drm/i915_drm.h | 6 +-
5 files changed, 72 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4070f6ff1db6..d1d225204f09 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -18,12 +18,13 @@ struct drm_i915_private;
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
-#define GEN_MAX_EUS(10) /* HSW upper bound */
+#define GEN_MAX_EUS(16) /* TGL upper bound */
#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
struct sseu_dev_info {
u8 slice_mask;
u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
+ u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -40,12 +41,6 @@ struct sseu_dev_info {
u8 ss_stride;
u8 eu_stride;
-
- /* We don't have more than 8 eus per subslice at the moment and as we
-* store eus enabled using bits, no need to multiply by eus per
-* subslice.
-*/
- u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
};
/*
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 43db50095257..b5b449a88cf1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3823,7 +3823,8 @@ static void gen10_sseu_device_status(struct
drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+ if (info->sseu.has_subslice_pg &&
+ !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
/* skip disabled subslice */
continue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..47847135a11f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2956,6 +2956,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 50b05a5de53b..b91a960b037f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -182,13 +182,69 @@ static u16 compute_eu_total(const struct sseu_dev_info
*sseu)
return total;
}
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
+ u8 s_en, u32 ss_en, u16 eu_en)
+{
+ int s, ss;
+
+ /* ss_en represents entire subslice mask across all slices */
+ GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
+ sizeof(ss_en) * BITS_PER_BYTE);
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ if ((s_en & BIT(s)) == 0)
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+
+ intel_sseu_set_subslices(sseu, s, ss_en);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
+ sseu_set_eus(sseu, s, ss, eu_en);
+ }
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void gen12_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+
[Intel-gfx] [PATCH 1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
From: Michel Thierry
The media ranges extend beyond what gen11 gives so we can't piggypack
on gen11 ranges, even on read side.
Introduce a table for gen12 and accessors for it.
v2: correctly implement gen12_fwtable_write/read (Daniele)
v3: update with ranges from bspec.
v4: avoid GEN11_NEEDS_FORCEWAKE on read size (Mika)
BSpec: 18331.
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 75 ++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 9e583f13a9e4..18e8314641a8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -910,6 +910,9 @@ static const struct intel_forcewake_range __vlv_fw_ranges[]
= {
__fwd; \
})
+#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
+ find_fw_domain(uncore, offset)
+
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const i915_reg_t gen8_shadowed_regs[] = {
RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
@@ -935,6 +938,20 @@ static const i915_reg_t gen11_shadowed_regs[] = {
/* TODO: Other registers are not yet used */
};
+static const i915_reg_t gen12_shadowed_regs[] = {
+ RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
+ GEN6_RPNSWREQ, /* 0xA008 */
+ GEN6_RC_VIDEO_FREQ, /* 0xA00C */
+ RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
+ RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C (base) */
+ RING_TAIL(GEN11_BSD2_RING_BASE),/* 0x1C4000 (base) */
+ RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
+ RING_TAIL(GEN11_BSD3_RING_BASE),/* 0x1D (base) */
+ RING_TAIL(GEN11_BSD4_RING_BASE),/* 0x1D4000 (base) */
+ RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
+ /* TODO: Other registers are not yet used */
+};
+
static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
{
u32 offset = i915_mmio_reg_offset(*reg);
@@ -957,6 +974,7 @@ static bool is_gen##x##_shadowed(u32 offset) \
__is_genX_shadowed(8)
__is_genX_shadowed(11)
+__is_genX_shadowed(12)
static enum forcewake_domains
gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
@@ -1010,6 +1028,15 @@ static const struct intel_forcewake_range
__chv_fw_ranges[] = {
__fwd; \
})
+#define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (!is_gen12_shadowed(__offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
+
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
@@ -1080,6 +1107,46 @@ static const struct intel_forcewake_range
__gen11_fw_ranges[] = {
GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
};
+/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __gen12_fw_ranges[] = {
+ GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
+ GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x24800, 0x3, FORCEWAKE_BLITTER),
+ GEN_FW_RAN
[Intel-gfx] ✓ Fi.CI.IGT: success for Revert "drm/i915/userptr: Acquire the page lock around set_page_dirty()"
== Series Details == Series: Revert "drm/i915/userptr: Acquire the page lock around set_page_dirty()" URL : https://patchwork.freedesktop.org/series/66605/ State : success == Summary == CI Bug Log - changes from CI_DRM_6882_full -> Patchwork_14382_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14382_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_switch@legacy-render: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] / [fdo#111381]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-apl6/igt@gem_ctx_swi...@legacy-render.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-apl8/igt@gem_ctx_swi...@legacy-render.html * igt@gem_eio@unwedge-stress: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-apl4/igt@gem_...@unwedge-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-apl7/igt@gem_...@unwedge-stress.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb7/igt@gem_exec_as...@concurrent-writes-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110854]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb4/igt@gem_exec_balan...@smoke.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@i915_pm_rpm@legacy-planes: - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713] / [fdo#108840] / [fdo#109960]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb3/igt@i915_pm_...@legacy-planes.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-iclb5/igt@i915_pm_...@legacy-planes.html * igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb5/igt@kms_cursor_edge_w...@pipe-c-128x128-top-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-iclb7/igt@kms_cursor_edge_w...@pipe-c-128x128-top-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#102670]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-skl10/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-skl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-hsw5/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-hsw2/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([fdo#106978] / [fdo#107713]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb2/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-iclb8/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-blt.html * igt@kms_plane@pixel-format-pipe-b-planes: - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713] / [fdo#110036 ]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6882/shard-iclb7/igt@kms_pl...@pixel-format-pipe-b-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14382/shard-iclb1/igt@kms_pl...@pixel-format-pipe-b-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-iclb: [PASS][23] -> [INCOMPLETE][24] ([fdo#107713] / [fdo#110042]) [23]: https://intel-gfx-ci.01.org/tree/dr
[Intel-gfx] [PATCH v8 0/7] DC3CO Support for TGL
v8 revision is a rework of series, which has fixed the review comments provided by Imre and Animesh. Anshuman Gupta (7): drm/i915/tgl: Add DC3CO required register and bits drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask drm/i915/tgl: Enable DC3CO state in "DC Off" power well drm/i915/tgl: Do modeset to enable and configure DC3CO exitline. drm/i915/tgl: DC3CO PSR2 helper drm/i915/tgl: switch between dc3co and dc5 based on display idleness drm/i915/tgl: Add DC3CO counter in i915_dmc_info drivers/gpu/drm/i915/display/intel_display.c | 5 + .../drm/i915/display/intel_display_power.c| 332 +- .../drm/i915/display/intel_display_power.h| 13 + .../drm/i915/display/intel_display_types.h| 1 + .../gpu/drm/i915/display/intel_frontbuffer.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 52 +++ drivers/gpu/drm/i915/display/intel_psr.h | 2 + drivers/gpu/drm/i915/i915_debugfs.c | 6 + drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_params.c| 3 +- drivers/gpu/drm/i915/i915_reg.h | 10 + drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_pm.h | 2 + 13 files changed, 415 insertions(+), 17 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well
Add target_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
v6: Fixed minor unwanted change.
v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
v8: Uniform checks by using only target_dc_state instead of allowed_dc_mask
in "DC off" power well callback. [Imre]
Adding "DC off" power well id to older platforms. [Imre]
Removed psr2_deep_sleep flag from tgl_set_target_dc_state. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 102 --
.../drm/i915/display/intel_display_power.h| 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 96 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 24cd9320ad4c..7965e07257a0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -772,6 +772,36 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+static void
+allowed_dc_mask_to_target_dc_state(struct drm_i915_private *dev_priv)
+{
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
+ dev_priv->csr.target_dc_state = DC_STATE_EN_UPTO_DC6;
+ else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
+ dev_priv->csr.target_dc_state = DC_STATE_EN_UPTO_DC5;
+}
+
+static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
+{
+ DRM_DEBUG_KMS("Enabling DC3CO\n");
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ DRM_DEBUG_KMS("Disabling DC3CO\n");
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+* Delay of 200us DC3CO Exit time B.Spec 49196
+*/
+ udelay(200);
+}
+
static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -939,7 +969,8 @@ static void bxt_verify_ddi_phy_power_wells(struct
drm_i915_private *dev_priv)
static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
+ return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
@@ -955,6 +986,11 @@ static void gen9_disable_dc_states(struct drm_i915_private
*dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
+ if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
+ tgl_disable_dc3co(dev_priv);
+ return;
+ }
+
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
@@ -987,12 +1023,59 @@ static void gen9_dc_off_power_well_disable(struct
drm_i915_private *dev_priv,
if (!dev_priv->csr.dmc_payload)
return;
- if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
+ if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO)
+ tgl_enable_dc3co(dev_priv);
+ else if (dev_priv->csr.target_dc_state == DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(dev_priv);
- else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
+ else if (dev_priv->csr.target_dc_state == DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(dev_priv);
}
+void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state)
+{
+ struct i915_power_well *power_well;
+ bool dc_off_enabled;
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+
+ mutex_lock(&power_domains->lock);
+ power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
+
+ if (!power_well)
+ goto unlock;
+
+ if (state == dev_priv->csr.target_dc_state)
+ goto unlock;
+
+ /*
+
[Intel-gfx] [PATCH v8 6/7] drm/i915/tgl: switch between dc3co and dc5 based on display idleness
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
B.Specs:49196 has a restriction to enable DC3CO only for Video Playback.
It will be worthy to enable DC3CO after completion of each pageflip
and switch back to DC5 when display is idle because driver doesn't
differentiate between video playback and a normal pageflip.
We will use Frontbuffer flush call tgl_dc3co_flush() to enable DC3CO
state only for ORIGIN_FLIP flush call, because DC3CO state has primarily
targeted for VPB use case. We are not interested here for frontbuffer
invalidates calls because that triggers PSR2 exit, which will
explicitly disable DC3CO.
DC5 and DC6 saves more power, but can't be entered during video
playback because there are not enough idle frames in a row to meet
most PSR2 panel deep sleep entry requirement typically 4 frames.
As PSR2 existing implementation is using minimum 6 idle frames for
deep sleep, it is safer to enable DC5/6 after 6 idle frames
(By scheduling a delayed work of 6 idle frames, once DC3CO has been
enabled after a pageflip).
After manually waiting for 6 idle frames DC5/6 will be enabled and
PSR2 deep sleep idle frames will be restored to 6 idle frames, at this
point DMC will triggers DC5/6 once PSR2 enters to deep sleep after
6 idle frames.
In future when we will enable S/W PSR2 tracking, we can change the
PSR2 required deep sleep idle frames to 1 so DMC can trigger the
DC5/6 immediately after S/W manual waiting of 6 idle frames get
complete.
v2: calculated s/w state to switch over dc3co when there is an
update. [Imre]
Used cancel_delayed_work_sync() in order to avoid any race
with already scheduled delayed work. [Imre]
v3: Cancel_delayed_work_sync() may blocked the commit work.
hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
v4: Used frontbuffer flush mechanism. [Imre]
v5: Used psr.pipe to extract frontbuffer busy bits. [Imre]
Used cancel_delayed_work_sync() in encoder disable path. [Imre]
Used mod_delayed_work() instead of cancelling and scheduling a
delayed work. [Imre]
Used psr.lock in tgl_dc5_idle_thread() to enable psr2 deep
sleep. [Imre]
Removed DC5_REQ_IDLE_FRAMES macro. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 97 +++
.../drm/i915/display/intel_display_power.h| 4 +
.../gpu/drm/i915/display/intel_frontbuffer.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
5 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 42eabcdecf00..a605047cb28a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -20,6 +20,7 @@
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_pm.h"
+#include "intel_psr.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -773,6 +774,27 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
+{
+ u32 pixel_rate, crtc_htotal, crtc_vtotal;
+ u32 frametime_us;
+
+ if (!cstate || !cstate->base.active)
+ return 0;
+
+ pixel_rate = cstate->pixel_rate;
+
+ if (WARN_ON(pixel_rate == 0))
+ return 0;
+
+ crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
+ crtc_vtotal = cstate->base.adjusted_mode.crtc_vtotal;
+ frametime_us = DIV_ROUND_UP(crtc_htotal * crtc_vtotal * 1000ULL,
+ pixel_rate);
+
+ return frametime_us;
+}
+
void tgl_disable_psr2_transcoder_exitline(const struct intel_crtc_state
*cstate)
{
struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
@@ -784,6 +806,9 @@ void tgl_disable_psr2_transcoder_exitline(const struct
intel_crtc_state *cstate)
val = I915_READ(EXITLINE(cstate->cpu_transcoder));
val &= ~EXITLINE_ENABLE;
I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+
+ /* As psr2 encoder has disabled, cancel the dc5 idle delayed work */
+ cancel_delayed_work_sync(&dev_priv->csr.idle_work);
}
void tgl_enable_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
@@ -817,6 +842,60 @@ void tgl_enable_psr2_transcoder_exitline(const struct
intel_crtc_state *cstate)
I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
}
+/*
+ * When we will enable manual PSR2 S/W tracking in fu
[Intel-gfx] [PATCH v8 5/7] drm/i915/tgl: DC3CO PSR2 helper
Add dc3co helper functions to enable/disable psr2 deep sleep.
Adhere B.Specs by disallow DC3CO state before PSR2 exit.
Enable PSR2 exitline event and program the desired scanlines
to exit DC3CO in intel_psr_enable function at modeset path.
Disable the DC3CO exitline in order to maintian consistent
pipe config state in encoder disable path.
v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to
intel_psr_enable(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 51
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index b3c7eef53bf3..11d37f96ce71 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -534,6 +534,48 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv,
enum transcoder trans)
return trans == TRANSCODER_EDP;
}
+static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
+u32 idle_frames)
+{
+ u32 val;
+
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
+}
+
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
+{
+ int idle_frames = 0;
+
+ psr2_program_idle_frames(dev_priv, idle_frames);
+}
+
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
+{
+ int idle_frames;
+
+ /*
+* Let's use 6 as the minimum to cover all known cases including the
+* off-by-one issue that HW has in some cases.
+*/
+ idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+ idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+ psr2_program_idle_frames(dev_priv, idle_frames);
+}
+
+static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+{
+ if (!IS_TIGERLAKE(dev_priv))
+ return;
+
+ cancel_delayed_work(&dev_priv->csr.idle_work);
+ /* Before PSR2 exit disallow dc3co*/
+ tgl_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+}
+
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
@@ -799,6 +841,10 @@ void intel_psr_enable(struct intel_dp *intel_dp,
WARN_ON(dev_priv->drrs.dp);
+ /* Enable PSR2 transcoder exit line */
+ if (crtc_state->has_psr2)
+ tgl_enable_psr2_transcoder_exitline(crtc_state);
+
mutex_lock(&dev_priv->psr.lock);
if (!psr_global_enabled(dev_priv->psr.debug)) {
@@ -829,6 +875,7 @@ static void intel_psr_exit(struct drm_i915_private
*dev_priv)
}
if (dev_priv->psr.psr2_enabled) {
+ tgl_disallow_dc3co_on_psr2_exit(dev_priv);
val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
WARN_ON(!(val & EDP_PSR2_ENABLE));
val &= ~EDP_PSR2_ENABLE;
@@ -895,6 +942,10 @@ void intel_psr_disable(struct intel_dp *intel_dp,
if (WARN_ON(!CAN_PSR(dev_priv)))
return;
+ /* Disable PSR2 transcoder exit line */
+ if (old_crtc_state->has_psr2)
+ tgl_disable_psr2_transcoder_exitline(old_crtc_state);
+
mutex_lock(&dev_priv->psr.lock);
intel_psr_disable_locked(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index 46e4de8b8cd5..75a9862f36fd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -35,5 +35,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value);
bool intel_psr_enabled(struct intel_dp *intel_dp);
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PSR_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 68fb732c24c8..4521b9381db3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -494,6 +494,7 @@ struct i915_psr {
bool link_standby;
bool colorimetry_support;
bool psr2_enabled;
+ bool psr2_deep_slp_disabled;
u8 sink_sync_latency;
ktime_t last_entry_attempt;
ktime_t last_exit;
--
2.21.0
___
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[Intel-gfx] [PATCH v8 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e5835337f022..5bb0a299b520 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2404,6 +2404,12 @@ static int i915_dmc_info(struct seq_file *m, void
*unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
+ /*
+* TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter.
+*/
+ if (IS_TIGERLAKE(dev_priv))
+ seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
if (INTEL_GEN(dev_priv) >= 12) {
dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6bfebab9a441..3ad75d0fb71a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7255,6 +7255,8 @@ enum {
#define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
#define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
+#define DMC_DEBUG3 _MMIO(0x101090)
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE(1 << 29)
--
2.21.0
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[Intel-gfx] [PATCH v8 1/7] drm/i915/tgl: Add DC3CO required register and bits
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
v1: Use of REG_BIT and using extra space for EXITLINE_ macro
definition. [Animesh]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..6bfebab9a441 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4138,6 +4138,7 @@ enum {
#define _VTOTAL_A 0x6000c
#define _VBLANK_A 0x60010
#define _VSYNC_A 0x60014
+#define _EXITLINE_A0x60018
#define _PIPEASRC 0x6001c
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
@@ -4184,11 +4185,16 @@ enum {
#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans)_MMIO_TRANS2(trans, _EXITLINE_A)
#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
+#define EXITLINE_ENABLE REG_BIT(31)
+#define EXITLINE_MASKREG_GENMASK(12, 0)
+#define EXITLINE_SHIFT 0
+
/*
* HSW+ eDP PSR registers
*
@@ -10118,6 +10124,8 @@ enum skl_power_gate {
/* GEN9 DC */
#define DC_STATE_EN_MMIO(0x45504)
#define DC_STATE_DISABLE 0
+#define DC_STATE_EN_DC3CO REG_BIT(30)
+#define DC_STATE_DC3CO_STATUS REG_BIT(29)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
--
2.21.0
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[Intel-gfx] [PATCH v8 2/7] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently. [Animesh]
v2: Using a switch statement for cleaner code. [Animesh]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce88a27229ef..24cd9320ad4c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -698,7 +698,11 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
- if (INTEL_GEN(dev_priv) >= 11)
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+ | DC_STATE_EN_DC9;
+ else if (IS_GEN(dev_priv, 11))
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
@@ -3927,14 +3931,17 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
- if (INTEL_GEN(dev_priv) >= 11) {
- max_dc = 2;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
* suspend/resume, so allow it unconditionally.
*/
mask = DC_STATE_EN_DC9;
+ } else if (IS_GEN(dev_priv, 11)) {
+ max_dc = 2;
+ mask = DC_STATE_EN_DC9;
} else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
max_dc = 2;
mask = 0;
@@ -3953,7 +3960,7 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
requested_dc = enable_dc;
} else if (enable_dc == -1) {
requested_dc = max_dc;
- } else if (enable_dc > max_dc && enable_dc <= 2) {
+ } else if (enable_dc > max_dc && enable_dc <= 4) {
DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
enable_dc, max_dc);
requested_dc = max_dc;
@@ -3962,10 +3969,20 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
requested_dc = max_dc;
}
- if (requested_dc > 1)
+ switch (requested_dc) {
+ case 4:
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+ break;
+ case 3:
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+ break;
+ case 2:
mask |= DC_STATE_EN_UPTO_DC6;
- if (requested_dc > 0)
+ break;
+ case 1:
mask |= DC_STATE_EN_UPTO_DC5;
+ break;
+ }
DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..4f1806f65040 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
- "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+ "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+ "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
i915_param_named_unsafe(enable_fbc, int, 0600,
"Enable frame buffer compression for power savings "
--
2.21.0
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[Intel-gfx] [PATCH v8 4/7] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline.
DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset to enable and configure
DC3CO exitline.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915/display/intel_display_power.c| 104 ++
.../drm/i915/display/intel_display_power.h| 7 ++
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_pm.h | 2 +
6 files changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a19f8c73f2e0..6b7b8d2112a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7409,6 +7409,8 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
const struct drm_display_mode *adjusted_mode =
&pipe_config->base.adjusted_mode;
int clock_limit = dev_priv->max_dotclk_freq;
+ tgl_dc3co_crtc_compute_config(dev_priv, pipe_config);
+
if (INTEL_GEN(dev_priv) < 4) {
clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
@@ -10474,6 +10476,8 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
pipe_config->pixel_multiplier = 1;
}
+ tgl_dc3co_crtc_get_config(pipe_config);
+
out:
for_each_power_domain(power_domain, power_domain_mask)
intel_display_power_put(dev_priv,
@@ -12739,6 +12743,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(output_format);
+ PIPE_CONF_CHECK_BOOL(has_dc3co_exitline);
PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7965e07257a0..42eabcdecf00 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,7 @@
#include "intel_hotplug.h"
#include "intel_sideband.h"
#include "intel_tc.h"
+#include "intel_pm.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -772,6 +773,109 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+void tgl_disable_psr2_transcoder_exitline(const struct intel_crtc_state
*cstate)
+{
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ u32 val;
+
+ if (!cstate->has_dc3co_exitline)
+ return;
+
+ val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+ val &= ~EXITLINE_ENABLE;
+ I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+void tgl_enable_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
+{
+ u32 linetime_us, val, exit_scanlines;
+ u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+ if (!cstate->has_dc3co_exitline)
+ return;
+
+ linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
+ if (WARN_ON(!linetime_us))
+ return;
+ /*
+* DC3CO Exit time 200us B.Spec 49196
+* PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+* Exit line event need to program above calculated scan lines before
+* next VBLANK.
+*/
+ exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
+ if (WARN_ON(exit_scanlines > crtc_vdisplay))
+ return;
+
+ exit_scanlines = crtc_vdisplay - exit_scanlines;
+ exit_scanlines <<= EXITLINE_SHIFT;
+ val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+ val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+ val |= exit_scanlines;
+ val |= EXITLINE_ENABLE;
+ I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static bool tgl_dc3co_is_edp_connected(struct intel_crtc_state *crtc_state)
+{
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_connector *connector;
+ struct drm_connector_state *connector_state;
+ int i;
+
+ for_each_new_connector_in_state(state, connector, connector_state, i) {
+ if (connector->status == connect
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Only unwedge if we can reset first
== Series Details ==
Series: drm/i915/gt: Only unwedge if we can reset first
URL : https://patchwork.freedesktop.org/series/66637/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6887 -> Patchwork_14395
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14395 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14395, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14395:
### IGT changes ###
Possible regressions
* igt@i915_module_load@reload-with-fault-injection:
- fi-blb-e6850: NOTRUN -> [DMESG-WARN][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-blb-e6850/igt@i915_module_l...@reload-with-fault-injection.html
- fi-bwr-2160:[PASS][2] -> [DMESG-WARN][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-bwr-2160/igt@i915_module_l...@reload-with-fault-injection.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-bwr-2160/igt@i915_module_l...@reload-with-fault-injection.html
- fi-pnv-d510:[PASS][4] -> [DMESG-WARN][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-pnv-d510/igt@i915_module_l...@reload-with-fault-injection.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-pnv-d510/igt@i915_module_l...@reload-with-fault-injection.html
- fi-gdg-551: [PASS][6] -> [DMESG-WARN][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-gdg-551/igt@i915_module_l...@reload-with-fault-injection.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-gdg-551/igt@i915_module_l...@reload-with-fault-injection.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-pnv-d510/igt@run...@aborted.html
- fi-gdg-551: NOTRUN -> [FAIL][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-gdg-551/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u2}:[PASS][10] -> [INCOMPLETE][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][12]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][13]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-tgl-u/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_14395 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_reset:
- fi-icl-u2: [PASS][14] -> [INCOMPLETE][15] ([fdo#107713])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-icl-u2/igt@i915_selftest@live_reset.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-icl-u2/igt@i915_selftest@live_reset.html
* igt@i915_selftest@live_workarounds:
- fi-bsw-kefka: [PASS][16] -> [DMESG-WARN][17] ([fdo#111373])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-bsw-kefka/igt@i915_selftest@live_workarounds.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-bsw-kefka/igt@i915_selftest@live_workarounds.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][18] -> [FAIL][19] ([fdo#111407])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_busy@basic-before-default:
- fi-icl-u3: [PASS][20] -> [DMESG-WARN][21] ([fdo#107724])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-icl-u3/igt@prime_b...@basic-before-default.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-icl-u3/igt@prime_b...@basic-before-default.html
Possible fixes
* igt@gem_close_race@basic-process:
- fi-icl-u3: [DMESG-WARN][22] ([fdo#107724]) -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-icl-u3/igt@gem_close_r...@basic-process.html
[23]:
Re: [Intel-gfx] [PATCH v3 00/37] Introduce memory region concept (including device local memory)
On Thu, 12 Sep 2019 at 23:33, Joonas Lahtinen wrote: > > Quoting Dave Airlie (2019-08-13 22:20:52) > > On Sat, 10 Aug 2019 at 08:26, Matthew Auld wrote: > > > > > > In preparation for upcoming devices with device local memory, introduce > > > the > > > concept of different memory regions, and a simple buddy allocator to > > > manage > > > them in i915. > > > > > > One of the concerns raised from v1 was around not using enough of TTM, > > > which is > > > a fair criticism, so trying to get better alignment here is something we > > > are > > > investigating, though currently that is still WIP so in the meantime v3 > > > still > > > continues to push more of the low-level details forward, but not yet the > > > TTM > > > interactions. > > > > Can we bump the TTM work up the ladder here, as is I'm not willing to > > accept any of this code upstream without some serious analysis, this > > isn't a case of me making a nice suggestion and you having the option > > to ignore it. Don't make me shout. > > Thanks for a reminder. TTM analysis was ongoing on the background > and we now reserved enough time to conclude on how to best align > with TTM in short-term and long-term. > > We decided to bite the bullet and apply dma_resv as the outer-most > locking in i915 codepaths to align with the TTM locking. As a > conclusion to those discussions we documented guidelines how to > align with TTM locking: > > https://patchwork.freedesktop.org/patch/328266/ > > As refactoring of locking fundamentals of the driver is a massive > undergoing with many opens along the path, we'd like to propose a > staged approach to avoid stalling the upstream work while it's > being done. > > Our first suggested step would be merging the i915 local memory > related internal code reworks to unblock the display work. This > step should not cause any conflicts with TTM. > > Following step would be to merge proposed memory allocation/ > management uAPIs with TTM related functionality behind them for > early debug. They would be protected by DRM_I915_DEBUG_EARLY_API > kernel config flag (depending on EXPERT & STAGING & BROKEN). > > This would allow us to keep debugging these new IOCTLs with Mesa > etc. while we rework the locking. The protection still leaving us > a possibility to correcting the uAPIs if/when there is need after > reworking the locking around dma_resv progresses. Draft of such > proposal here: > > https://patchwork.freedesktop.org/patch/327908/ > > The final step (a rather long one) would be then to complete the > locking rework in the driver and lift the DEBUG_EARLY_API > protection once the locking has been sorted. > > If you could confirm the above plan sounds reasonable to you, we > may then proceed with it. Just travelling, but this sounds like a good way foward to me. Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: introduce INTEL_DISPLAY_ENABLED()
Prepare for making a distinction between not having display and having
disabled display. Add INTEL_DISPLAY_ENABLED() and use it where
HAS_DISPLAY() is used after intel_device_info_runtime_init(). This is
initially duplication, as disabling display still leads to ->pipe_mask =
0 and HAS_DISPLAY() being false.
Note that ever since i915.display_disable was introduced, it has not
affected PCH detection even if it uses HAS_DISPLAY(), as display disable
happens after that.
Since INTEL_DISPLAY_ENABLED() will not make sense unless HAS_DISPLAY()
is true, include a warning for catching misuses making decisions on
INTEL_DISPLAY_ENABLED() when HAS_DISPLAY() is false.
v2: Remove INTEL_DISPLAY_ENABLED() check from intel_detect_pch() (Chris)
Cc: Chris Wilson
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Reviewed-by: José Roberto de Souza
Acked-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c| 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 8
drivers/gpu/drm/i915/i915_drv.h | 3 +++
6 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index efb39f350b19..1def550c68c8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1833,7 +1833,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
const struct bdb_header *bdb;
u8 __iomem *bios = NULL;
- if (!HAS_DISPLAY(dev_priv)) {
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) {
DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a19f8c73f2e0..2c0cb32235c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15366,7 +15366,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_pps_init(dev_priv);
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return;
if (INTEL_GEN(dev_priv) >= 12) {
@@ -17273,7 +17273,7 @@ intel_display_capture_error_state(struct
drm_i915_private *dev_priv)
BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return NULL;
error = kzalloc(sizeof(*error), GFP_ATOMIC);
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index d59eee5c5d9c..68338669f054 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -444,7 +444,7 @@ int intel_fbdev_init(struct drm_device *dev)
struct intel_fbdev *ifbdev;
int ret;
- if (WARN_ON(!HAS_DISPLAY(dev_priv)))
+ if (WARN_ON(!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)))
return -ENODEV;
ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index d6775a005726..3d4d19ac1d14 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -836,7 +836,7 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
unsigned int pin;
int ret;
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return 0;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0dfcb40f3162..9904f762f4bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -338,7 +338,7 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
- if (HAS_DISPLAY(dev_priv)) {
+ if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
ret = drm_vblank_init(&dev_priv->drm,
INTEL_NUM_PIPES(dev_priv));
if (ret)
@@ -389,7 +389,7 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
intel_overlay_setup(dev_priv);
- if (!HAS_DISPLAY(dev_priv))
+ if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return 0;
ret = intel_fbdev_init(dev);
@@ -1378,7 +1378,7 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
} else
DRM_ERR
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Only unwedge if we can reset first
Quoting Patchwork (2019-09-13 10:35:06) > == Series Details == > > Series: drm/i915/gt: Only unwedge if we can reset first > URL : https://patchwork.freedesktop.org/series/66637/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_6887 -> Patchwork_14395 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_14395 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_14395, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/ > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_14395: > > ### IGT changes ### > > Possible regressions > > * igt@i915_module_load@reload-with-fault-injection: > - fi-blb-e6850: NOTRUN -> [DMESG-WARN][1] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-blb-e6850/igt@i915_module_l...@reload-with-fault-injection.html > - fi-bwr-2160:[PASS][2] -> [DMESG-WARN][3] >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-bwr-2160/igt@i915_module_l...@reload-with-fault-injection.html >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-bwr-2160/igt@i915_module_l...@reload-with-fault-injection.html > - fi-pnv-d510:[PASS][4] -> [DMESG-WARN][5] >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-pnv-d510/igt@i915_module_l...@reload-with-fault-injection.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-pnv-d510/igt@i915_module_l...@reload-with-fault-injection.html > - fi-gdg-551: [PASS][6] -> [DMESG-WARN][7] >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6887/fi-gdg-551/igt@i915_module_l...@reload-with-fault-injection.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14395/fi-gdg-551/igt@i915_module_l...@reload-with-fault-injection.html How to ruin the party! -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
== Series Details == Series: series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges URL : https://patchwork.freedesktop.org/series/66638/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/tgl: Introduce gen12 forcewake ranges +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block Commit: drm/i915/tgl: s/ss/eu fuse reading support Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake ranges
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: Introduce gen12 forcewake
ranges
URL : https://patchwork.freedesktop.org/series/66638/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6888 -> Patchwork_14396
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14396:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_close_race@basic-threads:
- {fi-tgl-u}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-tgl-u/igt@gem_close_r...@basic-threads.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-tgl-u/igt@gem_close_r...@basic-threads.html
Known issues
Here are the changes found in Patchwork_14396 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@gem_flink_ba...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-icl-u3/igt@gem_flink_ba...@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724] /
[fdo#111214])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-icl-u3/igt@i915_module_l...@reload.html
Possible fixes
* igt@gem_ctx_create@basic:
- fi-bxt-dsi: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-bxt-dsi/igt@gem_ctx_cre...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-bxt-dsi/igt@gem_ctx_cre...@basic.html
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u2}:[INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][15] ([fdo#102614]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111096]) -> [FAIL][18] ([fdo#111407])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14396/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6888 -> Patchwork_14396
CI-20190529: 20190529
CI_DRM_6888: 52e9cd0877ee673ba1bb80c7c7be2e53c0821084 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5179: 337
[Intel-gfx] [PATCH] drm/i915/tgl: Limit ourselves to just rcs0
More pruning away of features until we have a stable system and a basis
for debugging what's missing.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9236fccb3a83..ee9a7959204c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -799,6 +799,7 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.has_rc6 = false, /* XXX disabled for debugging */
.has_logical_ring_preemption = false, /* XXX disabled for debugging */
+ .engine_mask = BIT(RCS0), /* XXX reduced for debugging */
};
#undef GEN
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/9] drm/print: add drm_debug_enabled()
Add helper to check if a drm debug category is enabled. Convert drm core
to use it. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_atomic_uapi.c | 2 +-
drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++---
drivers/gpu/drm/drm_edid.c| 2 +-
drivers/gpu/drm/drm_edid_load.c | 2 +-
drivers/gpu/drm/drm_mipi_dbi.c| 4 ++--
drivers/gpu/drm/drm_print.c | 4 ++--
drivers/gpu/drm/drm_vblank.c | 6 +++---
include/drm/drm_print.h | 5 +
8 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 5a5b42db6f2a..6576cd997cbd 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -1406,7 +1406,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
} else if (arg->flags & DRM_MODE_ATOMIC_NONBLOCK) {
ret = drm_atomic_nonblocking_commit(state);
} else {
- if (unlikely(drm_debug & DRM_UT_STATE))
+ if (unlikely(drm_debug_enabled(DRM_UT_STATE)))
drm_atomic_print_state(state);
ret = drm_atomic_commit(state);
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 97216099a718..f47c5b6b51f7 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -1180,7 +1180,7 @@ static int drm_dp_mst_wait_tx_reply(struct
drm_dp_mst_branch *mstb,
}
}
out:
- if (unlikely(ret == -EIO && drm_debug & DRM_UT_DP)) {
+ if (unlikely(ret == -EIO && drm_debug_enabled(DRM_UT_DP))) {
struct drm_printer p = drm_debug_printer(DBG_PREFIX);
drm_dp_mst_dump_sideband_msg_tx(&p, txmsg);
@@ -2321,7 +2321,7 @@ static int process_single_tx_qlock(struct
drm_dp_mst_topology_mgr *mgr,
idx += tosend + 1;
ret = drm_dp_send_sideband_msg(mgr, up, chunk, idx);
- if (unlikely(ret && drm_debug & DRM_UT_DP)) {
+ if (unlikely(ret && drm_debug_enabled(DRM_UT_DP))) {
struct drm_printer p = drm_debug_printer(DBG_PREFIX);
drm_printf(&p, "sideband msg failed to send\n");
@@ -2388,7 +2388,7 @@ static void drm_dp_queue_down_tx(struct
drm_dp_mst_topology_mgr *mgr,
mutex_lock(&mgr->qlock);
list_add_tail(&txmsg->next, &mgr->tx_msg_downq);
- if (unlikely(drm_debug & DRM_UT_DP)) {
+ if (unlikely(drm_debug_enabled(DRM_UT_DP))) {
struct drm_printer p = drm_debug_printer(DBG_PREFIX);
drm_dp_mst_dump_sideband_msg_tx(&p, txmsg);
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 12c783f4d956..58dad4d24cd4 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1551,7 +1551,7 @@ static void connector_bad_edid(struct drm_connector
*connector,
{
int i;
- if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
+ if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
return;
dev_warn(connector->dev->dev,
diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c
index d38b3b255926..37d8ba3ddb46 100644
--- a/drivers/gpu/drm/drm_edid_load.c
+++ b/drivers/gpu/drm/drm_edid_load.c
@@ -175,7 +175,7 @@ static void *edid_load(struct drm_connector *connector,
const char *name,
u8 *edid;
int fwsize, builtin;
int i, valid_extensions = 0;
- bool print_bad_edid = !connector->bad_edid_counter || (drm_debug &
DRM_UT_KMS);
+ bool print_bad_edid = !connector->bad_edid_counter ||
drm_debug_enabled(DRM_UT_KMS);
builtin = match_string(generic_edid_name, GENERIC_EDIDS, name);
if (builtin >= 0) {
diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c
index f8154316a3b0..ccfb5b33c5e3 100644
--- a/drivers/gpu/drm/drm_mipi_dbi.c
+++ b/drivers/gpu/drm/drm_mipi_dbi.c
@@ -783,7 +783,7 @@ static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi,
int dc,
int i, ret;
u8 *dst;
- if (drm_debug & DRM_UT_DRIVER)
+ if (drm_debug_enabled(DRM_UT_DRIVER))
pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
__func__, dc, max_chunk);
@@ -907,7 +907,7 @@ static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int
dc,
max_chunk = dbi->tx_buf9_len;
dst16 = dbi->tx_buf9;
- if (drm_debug & DRM_UT_DRIVER)
+ if (drm_debug_enabled(DRM_UT_DRIVER))
pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
__func__, dc, max_chunk);
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index c9b57012d412..a7c89ec5ff26 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -264,7 +264,7 @@ void drm_dev_dbg(const struct device *dev, unsigned int
category,
stru
[Intel-gfx] [PATCH 8/9] drm/amdgpu: use drm_debug_enabled() to check for debug categories
Allow better abstraction of the drm_debug global variable in the
future. No functional changes.
Cc: Alex Deucher
Cc: Christian König
Cc: David (ChunMing) Zhou
Cc: amd-...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
index 4a5951036927..5f17bd4899e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
@@ -234,7 +234,7 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter
*control,
DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
(uint16_t)address, numbytes);
- if (drm_debug & DRM_UT_DRIVER) {
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
16, 1, data, numbytes, false);
}
@@ -388,7 +388,7 @@ static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter
*control,
DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
(uint16_t)address, bytes_received);
- if (drm_debug & DRM_UT_DRIVER) {
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
16, 1, data, bytes_received, false);
}
--
2.20.1
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[Intel-gfx] [PATCH 1/9] drm/print: move drm_debug variable to drm_print.[ch]
Move drm_debug variable declaration and definition to where they are
relevant and needed. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_drv.c | 17 -
drivers/gpu/drm/drm_print.c | 19 +++
include/drm/drm_drv.h | 2 --
include/drm/drm_print.h | 2 ++
4 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index c456c3d3def2..b5b3fffe2299 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -46,26 +46,9 @@
#include "drm_internal.h"
#include "drm_legacy.h"
-/*
- * drm_debug: Enable debug output.
- * Bitmask of DRM_UT_x. See include/drm/drm_print.h for details.
- */
-unsigned int drm_debug = 0;
-EXPORT_SYMBOL(drm_debug);
-
MODULE_AUTHOR("Gareth Hughes, Leif Delgass, José Fonseca, Jon Smirl");
MODULE_DESCRIPTION("DRM shared core routines");
MODULE_LICENSE("GPL and additional rights");
-MODULE_PARM_DESC(debug, "Enable debug output, where each bit enables a debug
category.\n"
-"\t\tBit 0 (0x01) will enable CORE messages (drm core code)\n"
-"\t\tBit 1 (0x02) will enable DRIVER messages (drm controller code)\n"
-"\t\tBit 2 (0x04) will enable KMS messages (modesetting code)\n"
-"\t\tBit 3 (0x08) will enable PRIME messages (prime code)\n"
-"\t\tBit 4 (0x10) will enable ATOMIC messages (atomic code)\n"
-"\t\tBit 5 (0x20) will enable VBL messages (vblank code)\n"
-"\t\tBit 7 (0x80) will enable LEASE messages (leasing code)\n"
-"\t\tBit 8 (0x100) will enable DP messages (displayport code)");
-module_param_named(debug, drm_debug, int, 0600);
static DEFINE_SPINLOCK(drm_minor_lock);
static struct idr drm_minors_idr;
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index dfa27367ebb8..c9b57012d412 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -28,6 +28,7 @@
#include
#include
+#include
#include
#include
@@ -35,6 +36,24 @@
#include
#include
+/*
+ * drm_debug: Enable debug output.
+ * Bitmask of DRM_UT_x. See include/drm/drm_print.h for details.
+ */
+unsigned int drm_debug;
+EXPORT_SYMBOL(drm_debug);
+
+MODULE_PARM_DESC(debug, "Enable debug output, where each bit enables a debug
category.\n"
+"\t\tBit 0 (0x01) will enable CORE messages (drm core code)\n"
+"\t\tBit 1 (0x02) will enable DRIVER messages (drm controller code)\n"
+"\t\tBit 2 (0x04) will enable KMS messages (modesetting code)\n"
+"\t\tBit 3 (0x08) will enable PRIME messages (prime code)\n"
+"\t\tBit 4 (0x10) will enable ATOMIC messages (atomic code)\n"
+"\t\tBit 5 (0x20) will enable VBL messages (vblank code)\n"
+"\t\tBit 7 (0x80) will enable LEASE messages (leasing code)\n"
+"\t\tBit 8 (0x100) will enable DP messages (displayport code)");
+module_param_named(debug, drm_debug, int, 0600);
+
void __drm_puts_coredump(struct drm_printer *p, const char *str)
{
struct drm_print_iterator *iterator = p->arg;
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index 8976afe48c1c..cf13470810a5 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -778,8 +778,6 @@ struct drm_driver {
int dev_priv_size;
};
-extern unsigned int drm_debug;
-
int drm_dev_init(struct drm_device *dev,
struct drm_driver *driver,
struct device *parent);
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 12d4916254b4..e5c421abce48 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -34,6 +34,8 @@
#include
+extern unsigned int drm_debug;
+
/**
* DOC: print
*
--
2.20.1
___
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[Intel-gfx] [PATCH 0/9] drm/print: add and use drm_debug_enabled()
Hi all, just a little refactoring around drm_debug access to abstract it better. There shouldn't be any functional changes. I'd appreciate acks for merging the lot via drm-misc. If there are any objections to that, we'll need to postpone the last patch until everything has been merged and converted in drm-next. BR, Jani. Cc: Alex Deucher Cc: Christian König Cc: David (ChunMing) Zhou Cc: amd-...@lists.freedesktop.org Cc: Ben Skeggs Cc: nouv...@lists.freedesktop.org Cc: Rob Clark Cc: Sean Paul Cc: linux-arm-...@vger.kernel.org Cc: freedr...@lists.freedesktop.org Cc: Francisco Jerez Cc: Lucas Stach Cc: Russell King Cc: Christian Gmeiner Cc: etna...@lists.freedesktop.org Jani Nikula (9): drm/print: move drm_debug variable to drm_print.[ch] drm/print: add drm_debug_enabled() drm/etnaviv: use drm_debug_enabled() to check for debug categories drm/i2c/sil164: use drm_debug_enabled() to check for debug categories drm/i915: use drm_debug_enabled() to check for debug categories drm/msm: use drm_debug_enabled() to check for debug categories drm/nouveau: use drm_debug_enabled() to check for debug categories drm/amdgpu: use drm_debug_enabled() to check for debug categories drm/print: rename drm_debug to __drm_debug to discourage use drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 4 ++-- drivers/gpu/drm/drm_atomic_uapi.c| 2 +- drivers/gpu/drm/drm_dp_mst_topology.c| 6 ++--- drivers/gpu/drm/drm_drv.c| 17 --- drivers/gpu/drm/drm_edid.c | 2 +- drivers/gpu/drm/drm_edid_load.c | 2 +- drivers/gpu/drm/drm_mipi_dbi.c | 4 ++-- drivers/gpu/drm/drm_print.c | 23 ++-- drivers/gpu/drm/drm_vblank.c | 6 ++--- drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 8 +++ drivers/gpu/drm/i2c/sil164_drv.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_gem.h | 2 +- drivers/gpu/drm/i915/i915_utils.c| 2 +- drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.h | 4 ++-- drivers/gpu/drm/nouveau/nouveau_drv.h| 4 ++-- include/drm/drm_drv.h| 2 -- include/drm/drm_print.h | 8 +++ 22 files changed, 60 insertions(+), 52 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 9/9] drm/print: rename drm_debug to __drm_debug to discourage use
drm_debug_enabled() is the way to check. __drm_debug is now reserved for
drm print code only. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_print.c | 8
include/drm/drm_print.h | 5 +++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index a7c89ec5ff26..ca3c56b026f0 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -37,11 +37,11 @@
#include
/*
- * drm_debug: Enable debug output.
+ * __drm_debug: Enable debug output.
* Bitmask of DRM_UT_x. See include/drm/drm_print.h for details.
*/
-unsigned int drm_debug;
-EXPORT_SYMBOL(drm_debug);
+unsigned int __drm_debug;
+EXPORT_SYMBOL(__drm_debug);
MODULE_PARM_DESC(debug, "Enable debug output, where each bit enables a debug
category.\n"
"\t\tBit 0 (0x01) will enable CORE messages (drm core code)\n"
@@ -52,7 +52,7 @@ MODULE_PARM_DESC(debug, "Enable debug output, where each bit
enables a debug cat
"\t\tBit 5 (0x20) will enable VBL messages (vblank code)\n"
"\t\tBit 7 (0x80) will enable LEASE messages (leasing code)\n"
"\t\tBit 8 (0x100) will enable DP messages (displayport code)");
-module_param_named(debug, drm_debug, int, 0600);
+module_param_named(debug, __drm_debug, int, 0600);
void __drm_puts_coredump(struct drm_printer *p, const char *str)
{
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index e13f901312a4..880bc0d1fd48 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -34,7 +34,8 @@
#include
-extern unsigned int drm_debug;
+/* Do *not* use outside of drm_print.[ch]! */
+extern unsigned int __drm_debug;
/**
* DOC: print
@@ -296,7 +297,7 @@ static inline struct drm_printer drm_err_printer(const char
*prefix)
static inline bool drm_debug_enabled(unsigned int category)
{
- return drm_debug & category;
+ return __drm_debug & category;
}
__printf(3, 4)
--
2.20.1
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[Intel-gfx] [PATCH 6/9] drm/msm: use drm_debug_enabled() to check for debug categories
Allow better abstraction of the drm_debug global variable in the
future. No functional changes.
Cc: Rob Clark
Cc: Sean Paul
Cc: linux-arm-...@vger.kernel.org
Cc: freedr...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 9e40f559c51f..00e3353f9aad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -29,7 +29,7 @@
*/
#define DPU_DEBUG(fmt, ...)\
do { \
- if (unlikely(drm_debug & DRM_UT_KMS)) \
+ if (unlikely(drm_debug_enabled(DRM_UT_KMS))) \
DRM_DEBUG(fmt, ##__VA_ARGS__); \
else \
pr_debug(fmt, ##__VA_ARGS__); \
@@ -41,7 +41,7 @@
*/
#define DPU_DEBUG_DRIVER(fmt, ...) \
do { \
- if (unlikely(drm_debug & DRM_UT_DRIVER)) \
+ if (unlikely(drm_debug_enabled(DRM_UT_DRIVER)))\
DRM_ERROR(fmt, ##__VA_ARGS__); \
else \
pr_debug(fmt, ##__VA_ARGS__); \
--
2.20.1
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[Intel-gfx] [PATCH 5/9] drm/i915: use drm_debug_enabled() to check for debug categories
Allow better abstraction of the drm_debug global variable in the
future. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.h | 2 +-
drivers/gpu/drm/i915/i915_utils.c| 2 +-
drivers/gpu/drm/i915/intel_pm.c | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a19f8c73f2e0..b0f688152bd9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11956,7 +11956,7 @@ static void
intel_dump_infoframe(struct drm_i915_private *dev_priv,
const union hdmi_infoframe *frame)
{
- if ((drm_debug & DRM_UT_KMS) == 0)
+ if (!drm_debug_enabled(DRM_UT_KMS))
return;
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
@@ -12472,7 +12472,7 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv,
const union hdmi_infoframe *b)
{
if (fastset) {
- if ((drm_debug & DRM_UT_KMS) == 0)
+ if (!drm_debug_enabled(DRM_UT_KMS))
return;
drm_dbg(DRM_UT_KMS, "fastset mismatch in %s infoframe", name);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d09133a958e1..1281d52b0670 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1685,7 +1685,7 @@ static void intel_dp_print_rates(struct intel_dp
*intel_dp)
{
char str[128]; /* FIXME: too big for stack? */
- if ((drm_debug & DRM_UT_KMS) == 0)
+ if (!drm_debug_enabled(DRM_UT_KMS))
return;
snprintf_int_array(str, sizeof(str),
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0dfcb40f3162..46ed265d5e79 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1442,7 +1442,7 @@ static void i915_driver_unregister(struct
drm_i915_private *dev_priv)
static void i915_welcome_messages(struct drm_i915_private *dev_priv)
{
- if (drm_debug & DRM_UT_DRIVER) {
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
struct drm_printer p = drm_debug_printer("i915 device info:");
drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s
(subplatform=0x%x) gen=%i\n",
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 167a7b56ed5b..a49b39e896b7 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -34,7 +34,7 @@ struct drm_i915_private;
#ifdef CONFIG_DRM_I915_DEBUG_GEM
-#define GEM_SHOW_DEBUG() (drm_debug & DRM_UT_DRIVER)
+#define GEM_SHOW_DEBUG() drm_debug_enabled(DRM_UT_DRIVER)
#define GEM_BUG_ON(condition) do { if (unlikely((condition))) {\
pr_err("%s:%d GEM_BUG_ON(%s)\n", \
diff --git a/drivers/gpu/drm/i915/i915_utils.c
b/drivers/gpu/drm/i915/i915_utils.c
index 16acdf7bdbe6..f66540e15793 100644
--- a/drivers/gpu/drm/i915/i915_utils.c
+++ b/drivers/gpu/drm/i915/i915_utils.c
@@ -23,7 +23,7 @@ __i915_printk(struct drm_i915_private *dev_priv, const char
*level,
struct va_format vaf;
va_list args;
- if (is_debug && !(drm_debug & DRM_UT_DRIVER))
+ if (is_debug && !drm_debug_enabled(DRM_UT_DRIVER))
return;
va_start(args, fmt);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d0ceb272551f..d173d2aa17fe 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5343,7 +5343,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if ((drm_debug & DRM_UT_KMS) == 0)
+ if (!drm_debug_enabled(DRM_UT_KMS))
return;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
--
2.20.1
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[Intel-gfx] [PATCH 7/9] drm/nouveau: use drm_debug_enabled() to check for debug categories
Allow better abstraction of the drm_debug global variable in the
future. No functional changes.
Cc: Ben Skeggs
Cc: nouv...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/nouveau/dispnv50/disp.h | 4 ++--
drivers/gpu/drm/nouveau/nouveau_drv.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.h
b/drivers/gpu/drm/nouveau/dispnv50/disp.h
index 7c41b0599d1a..c0a79531b087 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.h
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.h
@@ -78,14 +78,14 @@ void evo_kick(u32 *, struct nv50_dmac *);
#define evo_mthd(p, m, s) do { \
const u32 _m = (m), _s = (s); \
- if (drm_debug & DRM_UT_KMS) \
+ if (drm_debug_enabled(DRM_UT_KMS)) \
pr_err("%04x %d %s\n", _m, _s, __func__); \
*((p)++) = ((_s << 18) | _m); \
} while(0)
#define evo_data(p, d) do {\
const u32 _d = (d); \
- if (drm_debug & DRM_UT_KMS) \
+ if (drm_debug_enabled(DRM_UT_KMS)) \
pr_err("\t%08x\n", _d); \
*((p)++) = _d; \
} while(0)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h
b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 70f34cacc552..16283d1e51aa 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -248,11 +248,11 @@ void nouveau_drm_device_remove(struct drm_device *dev);
#define NV_INFO(drm,f,a...) NV_PRINTK(info, &(drm)->client, f, ##a)
#define NV_DEBUG(drm,f,a...) do {
\
- if (unlikely(drm_debug & DRM_UT_DRIVER)) \
+ if (unlikely(drm_debug_enabled(DRM_UT_DRIVER)))\
NV_PRINTK(info, &(drm)->client, f, ##a); \
} while(0)
#define NV_ATOMIC(drm,f,a...) do {
\
- if (unlikely(drm_debug & DRM_UT_ATOMIC)) \
+ if (unlikely(drm_debug_enabled(DRM_UT_ATOMIC)))\
NV_PRINTK(info, &(drm)->client, f, ##a); \
} while(0)
--
2.20.1
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[Intel-gfx] [PATCH 4/9] drm/i2c/sil164: use drm_debug_enabled() to check for debug categories
Allow better abstraction of the drm_debug global variable in the
future. No functional changes.
Cc: Francisco Jerez
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i2c/sil164_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i2c/sil164_drv.c b/drivers/gpu/drm/i2c/sil164_drv.c
index 8bcf0d199145..a839f78a4c8a 100644
--- a/drivers/gpu/drm/i2c/sil164_drv.c
+++ b/drivers/gpu/drm/i2c/sil164_drv.c
@@ -44,7 +44,7 @@ struct sil164_priv {
((struct sil164_priv *)to_encoder_slave(x)->slave_priv)
#define sil164_dbg(client, format, ...) do { \
- if (drm_debug & DRM_UT_KMS) \
+ if (drm_debug_enabled(DRM_UT_KMS)) \
dev_printk(KERN_DEBUG, &client->dev,\
"%s: " format, __func__, ## __VA_ARGS__); \
} while (0)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/9] drm/etnaviv: use drm_debug_enabled() to check for debug categories
Allow better abstraction of the drm_debug global variable in the
future. No functional changes.
Cc: Lucas Stach
Cc: Russell King
Cc: Christian Gmeiner
Cc: etna...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
index 7e4e2959bf4f..32d9fac587f9 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
@@ -326,7 +326,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32
exec_state,
lockdep_assert_held(&gpu->lock);
- if (drm_debug & DRM_UT_DRIVER)
+ if (drm_debug_enabled(DRM_UT_DRIVER))
etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
link_target = etnaviv_cmdbuf_get_va(cmdbuf,
@@ -459,13 +459,13 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32
exec_state,
etnaviv_cmdbuf_get_va(buffer,
&gpu->mmu_context->cmdbuf_mapping)
+ buffer->user_size - 4);
- if (drm_debug & DRM_UT_DRIVER)
+ if (drm_debug_enabled(DRM_UT_DRIVER))
pr_info("stream link to 0x%08x @ 0x%08x %p\n",
return_target,
etnaviv_cmdbuf_get_va(cmdbuf,
&gpu->mmu_context->cmdbuf_mapping),
cmdbuf->vaddr);
- if (drm_debug & DRM_UT_DRIVER) {
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
cmdbuf->vaddr, cmdbuf->size, 0);
@@ -484,6 +484,6 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32
exec_state,
VIV_FE_LINK_HEADER_PREFETCH(link_dwords),
link_target);
- if (drm_debug & DRM_UT_DRIVER)
+ if (drm_debug_enabled(DRM_UT_DRIVER))
etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
On Thu, Sep 12, 2019 at 12:51:31PM -0700, José Roberto de Souza wrote:
> This 3 non-atomic drivers all have the same function getting the
> only encoder available in the connector, also atomic drivers have
> this fallback. So moving it a common place and sharing between atomic
> and non-atomic drivers.
>
> While at it I also removed the mention of
> drm_atomic_helper_best_encoder() that was renamed in
> commit 297e30b5d9b6 ("drm/atomic-helper: Unexport
> drm_atomic_helper_best_encoder").
>
> v3: moving drm_connector_get_single_encoder to drm_kms_helper module
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Laurent Pinchart
> Cc: dri-de...@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: José Roberto de Souza
lgtm
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/ast/ast_mode.c | 12
> drivers/gpu/drm/drm_atomic_helper.c| 15 ++-
> drivers/gpu/drm/drm_crtc_helper.c | 17 -
> drivers/gpu/drm/drm_crtc_helper_internal.h | 3 +++
> drivers/gpu/drm/mgag200/mgag200_mode.c | 11 ---
> drivers/gpu/drm/udl/udl_connector.c| 8
> include/drm/drm_modeset_helper_vtables.h | 6 +++---
> 7 files changed, 24 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
> index d349c721501c..eef95e1af06b 100644
> --- a/drivers/gpu/drm/ast/ast_mode.c
> +++ b/drivers/gpu/drm/ast/ast_mode.c
> @@ -687,17 +687,6 @@ static void ast_encoder_destroy(struct drm_encoder
> *encoder)
> kfree(encoder);
> }
>
> -
> -static struct drm_encoder *ast_best_single_encoder(struct drm_connector
> *connector)
> -{
> - int enc_id = connector->encoder_ids[0];
> - /* pick the encoder ids */
> - if (enc_id)
> - return drm_encoder_find(connector->dev, NULL, enc_id);
> - return NULL;
> -}
> -
> -
> static const struct drm_encoder_funcs ast_enc_funcs = {
> .destroy = ast_encoder_destroy,
> };
> @@ -847,7 +836,6 @@ static void ast_connector_destroy(struct drm_connector
> *connector)
> static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
> .mode_valid = ast_mode_valid,
> .get_modes = ast_get_modes,
> - .best_encoder = ast_best_single_encoder,
> };
>
> static const struct drm_connector_funcs ast_connector_funcs = {
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 4706439fb490..9d7e4da6c292 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -97,17 +97,6 @@ drm_atomic_helper_plane_changed(struct drm_atomic_state
> *state,
> }
> }
>
> -/*
> - * For connectors that support multiple encoders, either the
> - * .atomic_best_encoder() or .best_encoder() operation must be implemented.
> - */
> -static struct drm_encoder *
> -pick_single_encoder_for_connector(struct drm_connector *connector)
> -{
> - WARN_ON(connector->encoder_ids[1]);
> - return drm_encoder_find(connector->dev, NULL,
> connector->encoder_ids[0]);
> -}
> -
> static int handle_conflicting_encoders(struct drm_atomic_state *state,
> bool disable_conflicting_encoders)
> {
> @@ -135,7 +124,7 @@ static int handle_conflicting_encoders(struct
> drm_atomic_state *state,
> else if (funcs->best_encoder)
> new_encoder = funcs->best_encoder(connector);
> else
> - new_encoder =
> pick_single_encoder_for_connector(connector);
> + new_encoder =
> drm_connector_get_single_encoder(connector);
>
> if (new_encoder) {
> if (encoder_mask & drm_encoder_mask(new_encoder)) {
> @@ -359,7 +348,7 @@ update_connector_routing(struct drm_atomic_state *state,
> else if (funcs->best_encoder)
> new_encoder = funcs->best_encoder(connector);
> else
> - new_encoder = pick_single_encoder_for_connector(connector);
> + new_encoder = drm_connector_get_single_encoder(connector);
>
> if (!new_encoder) {
> DRM_DEBUG_ATOMIC("No suitable encoder found for
> [CONNECTOR:%d:%s]\n",
> diff --git a/drivers/gpu/drm/drm_crtc_helper.c
> b/drivers/gpu/drm/drm_crtc_helper.c
> index a51824a7e7c1..4a7447a53cea 100644
> --- a/drivers/gpu/drm/drm_crtc_helper.c
> +++ b/drivers/gpu/drm/drm_crtc_helper.c
> @@ -460,6 +460,17 @@ drm_crtc_helper_disable(struct drm_crtc *crtc)
> __drm_helper_disable_unused_functions(dev);
> }
>
> +/*
> + * For connectors that support multiple encoders, either the
> + * .atomic_best_encoder() or .best_encoder() operation must be implemented.
> + */
> +struct drm_encoder *
> +drm_connector_get_single_encoder(struct drm_connector *connector)
> +{
> + WARN_ON(connector->encoder_ids[1]);
> + return drm_encoder_find(connector->dev, NULL,
> connector-
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev9)
== Series Details == Series: DC3CO Support for TGL (rev9) URL : https://patchwork.freedesktop.org/series/64923/ State : warning == Summary == $ dim checkpatch origin/drm-tip c3f36fdec82d drm/i915/tgl: Add DC3CO required register and bits 0a2bd8b728de drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask 90dfa5c2071e drm/i915/tgl: Enable DC3CO state in "DC Off" power well -:67: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #67: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:802: + udelay(200); total: 0 errors, 0 warnings, 1 checks, 193 lines checked de039280c902 drm/i915/tgl: Do modeset to enable and configure DC3CO exitline. 97cfc089ad24 drm/i915/tgl: DC3CO PSR2 helper 66cd4a46a92d drm/i915/tgl: switch between dc3co and dc5 based on display idleness a6a25c98f5fa drm/i915/tgl: Add DC3CO counter in i915_dmc_info ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
Hi José,
Thank you for the patch.
On Thu, Sep 12, 2019 at 12:51:31PM -0700, José Roberto de Souza wrote:
> This 3 non-atomic drivers all have the same function getting the
> only encoder available in the connector, also atomic drivers have
> this fallback. So moving it a common place and sharing between atomic
> and non-atomic drivers.
>
> While at it I also removed the mention of
> drm_atomic_helper_best_encoder() that was renamed in
> commit 297e30b5d9b6 ("drm/atomic-helper: Unexport
> drm_atomic_helper_best_encoder").
>
> v3: moving drm_connector_get_single_encoder to drm_kms_helper module
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Laurent Pinchart
> Cc: dri-de...@lists.freedesktop.org
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/ast/ast_mode.c | 12
> drivers/gpu/drm/drm_atomic_helper.c| 15 ++-
> drivers/gpu/drm/drm_crtc_helper.c | 17 -
> drivers/gpu/drm/drm_crtc_helper_internal.h | 3 +++
> drivers/gpu/drm/mgag200/mgag200_mode.c | 11 ---
> drivers/gpu/drm/udl/udl_connector.c| 8
> include/drm/drm_modeset_helper_vtables.h | 6 +++---
> 7 files changed, 24 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
> index d349c721501c..eef95e1af06b 100644
> --- a/drivers/gpu/drm/ast/ast_mode.c
> +++ b/drivers/gpu/drm/ast/ast_mode.c
> @@ -687,17 +687,6 @@ static void ast_encoder_destroy(struct drm_encoder
> *encoder)
> kfree(encoder);
> }
>
> -
> -static struct drm_encoder *ast_best_single_encoder(struct drm_connector
> *connector)
> -{
> - int enc_id = connector->encoder_ids[0];
> - /* pick the encoder ids */
> - if (enc_id)
> - return drm_encoder_find(connector->dev, NULL, enc_id);
> - return NULL;
> -}
> -
> -
> static const struct drm_encoder_funcs ast_enc_funcs = {
> .destroy = ast_encoder_destroy,
> };
> @@ -847,7 +836,6 @@ static void ast_connector_destroy(struct drm_connector
> *connector)
> static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
> .mode_valid = ast_mode_valid,
> .get_modes = ast_get_modes,
> - .best_encoder = ast_best_single_encoder,
> };
>
> static const struct drm_connector_funcs ast_connector_funcs = {
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 4706439fb490..9d7e4da6c292 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -97,17 +97,6 @@ drm_atomic_helper_plane_changed(struct drm_atomic_state
> *state,
> }
> }
>
> -/*
> - * For connectors that support multiple encoders, either the
> - * .atomic_best_encoder() or .best_encoder() operation must be implemented.
> - */
> -static struct drm_encoder *
> -pick_single_encoder_for_connector(struct drm_connector *connector)
> -{
> - WARN_ON(connector->encoder_ids[1]);
> - return drm_encoder_find(connector->dev, NULL,
> connector->encoder_ids[0]);
> -}
> -
> static int handle_conflicting_encoders(struct drm_atomic_state *state,
> bool disable_conflicting_encoders)
> {
> @@ -135,7 +124,7 @@ static int handle_conflicting_encoders(struct
> drm_atomic_state *state,
> else if (funcs->best_encoder)
> new_encoder = funcs->best_encoder(connector);
> else
> - new_encoder =
> pick_single_encoder_for_connector(connector);
> + new_encoder =
> drm_connector_get_single_encoder(connector);
>
> if (new_encoder) {
> if (encoder_mask & drm_encoder_mask(new_encoder)) {
> @@ -359,7 +348,7 @@ update_connector_routing(struct drm_atomic_state *state,
> else if (funcs->best_encoder)
> new_encoder = funcs->best_encoder(connector);
> else
> - new_encoder = pick_single_encoder_for_connector(connector);
> + new_encoder = drm_connector_get_single_encoder(connector);
>
> if (!new_encoder) {
> DRM_DEBUG_ATOMIC("No suitable encoder found for
> [CONNECTOR:%d:%s]\n",
> diff --git a/drivers/gpu/drm/drm_crtc_helper.c
> b/drivers/gpu/drm/drm_crtc_helper.c
> index a51824a7e7c1..4a7447a53cea 100644
> --- a/drivers/gpu/drm/drm_crtc_helper.c
> +++ b/drivers/gpu/drm/drm_crtc_helper.c
> @@ -460,6 +460,17 @@ drm_crtc_helper_disable(struct drm_crtc *crtc)
> __drm_helper_disable_unused_functions(dev);
> }
>
> +/*
> + * For connectors that support multiple encoders, either the
> + * .atomic_best_encoder() or .best_encoder() operation must be implemented.
> + */
> +struct drm_encoder *
> +drm_connector_get_single_encoder(struct drm_connector *connector)
> +{
> + WARN_ON(connector->encoder_ids[1]);
> + return drm_encoder_find(connector->dev, NULL,
> connector
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL (rev9)
== Series Details == Series: DC3CO Support for TGL (rev9) URL : https://patchwork.freedesktop.org/series/64923/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/tgl: Add DC3CO required register and bits Okay! Commit: drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Okay! Commit: drm/i915/tgl: Enable DC3CO state in "DC Off" power well Okay! Commit: drm/i915/tgl: Do modeset to enable and configure DC3CO exitline. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Don't mix srcu tag and negative error codes (rev2)
== Series Details == Series: drm/i915: Don't mix srcu tag and negative error codes (rev2) URL : https://patchwork.freedesktop.org/series/66524/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14386_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14386_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-apl4/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@fifo-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +12 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb4/igt@gem_exec_sched...@fifo-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-iclb7/igt@gem_exec_sched...@fifo-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@kms_atomic_transition@plane-all-transition-fencing: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb4/igt@kms_atomic_transit...@plane-all-transition-fencing.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-iclb7/igt@kms_atomic_transit...@plane-all-transition-fencing.html * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#103558] / [fdo#105602] / [fdo#110222]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-kbl3/igt@kms_b...@extended-pageflip-modeset-hang-oldfb-render-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-kbl2/igt@kms_b...@extended-pageflip-modeset-hang-oldfb-render-a.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-glk2/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render: - shard-kbl: [PASS][15] -> [DMESG-FAIL][16] ([fdo#103558] / [fdo#105602]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-kbl3/igt@kms_frontbuffer_track...@fbc-rgb565-draw-render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-kbl2/igt@kms_frontbuffer_track...@fbc-rgb565-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb2/igt@kms_psr2_su@page_flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14386/shard-iclb3/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb2/igt@kms_psr@ps
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Limit ourselves to just rcs0
Chris Wilson writes:
> More pruning away of features until we have a stable system and a basis
> for debugging what's missing.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 9236fccb3a83..ee9a7959204c 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -799,6 +799,7 @@ static const struct intel_device_info
> intel_tigerlake_12_info = {
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .has_rc6 = false, /* XXX disabled for debugging */
> .has_logical_ring_preemption = false, /* XXX disabled for debugging */
> + .engine_mask = BIT(RCS0), /* XXX reduced for debugging */
Yeah, that will do.
I have tried to find a pairing that works. It is either gttfill or
gem_sync depending on pair.
We yearn for coverage so,
Acked-by: Mika Kuoppala
> };
>
> #undef GEN
> --
> 2.23.0
___
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Re: [Intel-gfx] [PATCH v2] drm/i915: Don't mix srcu tag and negative error codes
Chris Wilson writes:
> While srcu may use an integer tag, it does not exclude potential error
> codes and so may overlap with our own use of -EINTR. Use a separate
> outparam to store the tag, and report the error code separately. While
> changing the function signature allow the caller to choose whether or not
> the potential wait may be interrupted.
>
> Fixes: 2caffbf11762 ("drm/i915: Revoke mmaps and prevent access to fence
> registers across reset")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Ville Syrjälä
Reviewed-by: Mika Kuoppala
> ---
> Drop state parameters, the potential user evaporated.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 6 ++
> drivers/gpu/drm/i915/gt/intel_reset.c| 8 +++-
> drivers/gpu/drm/i915/gt/intel_reset.h| 2 +-
> 3 files changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index 82db2b783123..1748e63156a2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -245,11 +245,9 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
>
> wakeref = intel_runtime_pm_get(rpm);
>
> - srcu = intel_gt_reset_trylock(ggtt->vm.gt);
> - if (srcu < 0) {
> - ret = srcu;
> + ret = intel_gt_reset_trylock(ggtt->vm.gt, &srcu);
> + if (ret)
> goto err_rpm;
> - }
>
> ret = i915_mutex_lock_interruptible(dev);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 296bbc7745fb..8327220ac558 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -1214,10 +1214,8 @@ void intel_gt_handle_error(struct intel_gt *gt,
> intel_runtime_pm_put(>->i915->runtime_pm, wakeref);
> }
>
> -int intel_gt_reset_trylock(struct intel_gt *gt)
> +int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
> {
> - int srcu;
> -
> might_lock(>->reset.backoff_srcu);
> might_sleep();
>
> @@ -1232,10 +1230,10 @@ int intel_gt_reset_trylock(struct intel_gt *gt)
>
> rcu_read_lock();
> }
> - srcu = srcu_read_lock(>->reset.backoff_srcu);
> + *srcu = srcu_read_lock(>->reset.backoff_srcu);
> rcu_read_unlock();
>
> - return srcu;
> + return 0;
> }
>
> void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h
> b/drivers/gpu/drm/i915/gt/intel_reset.h
> index 37a987b17108..52c00199e069 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.h
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.h
> @@ -38,7 +38,7 @@ int intel_engine_reset(struct intel_engine_cs *engine,
>
> void __i915_request_reset(struct i915_request *rq, bool guilty);
>
> -int __must_check intel_gt_reset_trylock(struct intel_gt *gt);
> +int __must_check intel_gt_reset_trylock(struct intel_gt *gt, int *srcu);
> void intel_gt_reset_unlock(struct intel_gt *gt, int tag);
>
> void intel_gt_set_wedged(struct intel_gt *gt);
> --
> 2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for DC3CO Support for TGL (rev9)
== Series Details ==
Series: DC3CO Support for TGL (rev9)
URL : https://patchwork.freedesktop.org/series/64923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6888 -> Patchwork_14397
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14397:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic:
- {fi-icl-u4}:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u4/igt@gem_exec_susp...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/fi-icl-u4/igt@gem_exec_susp...@basic.html
Known issues
Here are the changes found in Patchwork_14397 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_linear_blits@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@gem_linear_bl...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724] /
[fdo#111214])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/fi-icl-u3/igt@i915_module_l...@reload.html
Possible fixes
* igt@gem_ctx_create@basic:
- fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-bxt-dsi/igt@gem_ctx_cre...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/fi-bxt-dsi/igt@gem_ctx_cre...@basic.html
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u2}:[INCOMPLETE][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111593]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-tgl-u/igt@gem_exec_gttf...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/fi-tgl-u/igt@gem_exec_gttf...@basic.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111096]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][17] ([fdo#102614]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6888/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14397/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6888 -> Patchwork_14397
CI-20190529: 20190529
CI_DRM_6888: 52e9cd0877ee673ba1bb80c7c7be2e53c0821084 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5179: 3374cd0b048f9c277b2815bf80502f9f89680176 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14397: a6a25c98f5fae01d2175428deb153e07959dce58 @
git://anongit.freedesktop.org/gfx-ci/linux
== Kerne
Re: [Intel-gfx] [PATCH 2/9] drm/print: add drm_debug_enabled()
On Friday, 2019-09-13 14:51:39 +0300, Jani Nikula wrote:
> Add helper to check if a drm debug category is enabled. Convert drm core
> to use it. No functional changes.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 2 +-
> drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++---
> drivers/gpu/drm/drm_edid.c| 2 +-
> drivers/gpu/drm/drm_edid_load.c | 2 +-
> drivers/gpu/drm/drm_mipi_dbi.c| 4 ++--
> drivers/gpu/drm/drm_print.c | 4 ++--
> drivers/gpu/drm/drm_vblank.c | 6 +++---
> include/drm/drm_print.h | 5 +
> 8 files changed, 18 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 5a5b42db6f2a..6576cd997cbd 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -1406,7 +1406,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
> } else if (arg->flags & DRM_MODE_ATOMIC_NONBLOCK) {
> ret = drm_atomic_nonblocking_commit(state);
> } else {
> - if (unlikely(drm_debug & DRM_UT_STATE))
> + if (unlikely(drm_debug_enabled(DRM_UT_STATE)))
> drm_atomic_print_state(state);
>
> ret = drm_atomic_commit(state);
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 97216099a718..f47c5b6b51f7 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -1180,7 +1180,7 @@ static int drm_dp_mst_wait_tx_reply(struct
> drm_dp_mst_branch *mstb,
> }
> }
> out:
> - if (unlikely(ret == -EIO && drm_debug & DRM_UT_DP)) {
> + if (unlikely(ret == -EIO && drm_debug_enabled(DRM_UT_DP))) {
> struct drm_printer p = drm_debug_printer(DBG_PREFIX);
>
> drm_dp_mst_dump_sideband_msg_tx(&p, txmsg);
> @@ -2321,7 +2321,7 @@ static int process_single_tx_qlock(struct
> drm_dp_mst_topology_mgr *mgr,
> idx += tosend + 1;
>
> ret = drm_dp_send_sideband_msg(mgr, up, chunk, idx);
> - if (unlikely(ret && drm_debug & DRM_UT_DP)) {
> + if (unlikely(ret && drm_debug_enabled(DRM_UT_DP))) {
> struct drm_printer p = drm_debug_printer(DBG_PREFIX);
>
> drm_printf(&p, "sideband msg failed to send\n");
> @@ -2388,7 +2388,7 @@ static void drm_dp_queue_down_tx(struct
> drm_dp_mst_topology_mgr *mgr,
> mutex_lock(&mgr->qlock);
> list_add_tail(&txmsg->next, &mgr->tx_msg_downq);
>
> - if (unlikely(drm_debug & DRM_UT_DP)) {
> + if (unlikely(drm_debug_enabled(DRM_UT_DP))) {
> struct drm_printer p = drm_debug_printer(DBG_PREFIX);
>
> drm_dp_mst_dump_sideband_msg_tx(&p, txmsg);
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 12c783f4d956..58dad4d24cd4 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -1551,7 +1551,7 @@ static void connector_bad_edid(struct drm_connector
> *connector,
> {
> int i;
>
> - if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
> + if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
> return;
>
> dev_warn(connector->dev->dev,
> diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c
> index d38b3b255926..37d8ba3ddb46 100644
> --- a/drivers/gpu/drm/drm_edid_load.c
> +++ b/drivers/gpu/drm/drm_edid_load.c
> @@ -175,7 +175,7 @@ static void *edid_load(struct drm_connector *connector,
> const char *name,
> u8 *edid;
> int fwsize, builtin;
> int i, valid_extensions = 0;
> - bool print_bad_edid = !connector->bad_edid_counter || (drm_debug &
> DRM_UT_KMS);
> + bool print_bad_edid = !connector->bad_edid_counter ||
> drm_debug_enabled(DRM_UT_KMS);
>
> builtin = match_string(generic_edid_name, GENERIC_EDIDS, name);
> if (builtin >= 0) {
> diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c
> index f8154316a3b0..ccfb5b33c5e3 100644
> --- a/drivers/gpu/drm/drm_mipi_dbi.c
> +++ b/drivers/gpu/drm/drm_mipi_dbi.c
> @@ -783,7 +783,7 @@ static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi,
> int dc,
> int i, ret;
> u8 *dst;
>
> - if (drm_debug & DRM_UT_DRIVER)
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
>__func__, dc, max_chunk);
>
> @@ -907,7 +907,7 @@ static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi,
> int dc,
> max_chunk = dbi->tx_buf9_len;
> dst16 = dbi->tx_buf9;
>
> - if (drm_debug & DRM_UT_DRIVER)
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
>__func__, dc, max_chunk);
>
> diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
> index c9
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder
== Series Details == Series: series starting with [1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66619/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14387_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_6885_full and Patchwork_14387_full: ### New Piglit tests (7) ### * spec@arb_gpu_shader5@texturegather@vs-rgba-2-float-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegather@vs-rgba-3-float-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray-const: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-1-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-2-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-3-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_14387_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +6 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@fifo-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +19 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb4/igt@gem_exec_sched...@fifo-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/shard-iclb8/igt@gem_exec_sched...@fifo-bsd1.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_softpin@noreloc-s3: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#109100]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb1/igt@gem_soft...@noreloc-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/shard-iclb3/igt@gem_soft...@noreloc-s3.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#105363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-glk2/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/shard-glk3/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@basic-flip-vs-dpms: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-apl6/igt@kms_f...@basic-flip-vs-dpms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/shard-apl4/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +6 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642] / [fdo#111068]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb2/igt@kms_psr2_su@page_flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14387/shard-iclb5/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/display/icl: Bump up the hdisplay and vdisplay as per transcoder limits
Hey,
Op 29-07-2019 om 21:17 schreef Manasi Navare:
> Hi Ville,
>
> Thanks for your review, so do we want to merge this as is or
> do we need some function to reject the 8K mode on ICL in
> intel_dp_mode_valid()?
>
> Manasi
I've pushed this series as-is because it blocks my bigjoiner work. We should
probably reject modes in the connector specific functions if we can't handle
it. :)
>
> On Fri, Jul 12, 2019 at 11:29:38PM +0300, Ville Syrjälä wrote:
>> On Fri, Jul 12, 2019 at 01:22:13PM -0700, Manasi Navare wrote:
>>> On ICL+, the vertical limits for the transcoders are increased to 8192
>>> and horizontal limits are bumped to 16K so bump up
>>> limits in intel_mode_valid()
>>>
>>> v4:
>>> * Increase the hdisplay to 16K (Ville)
>>> v3:
>>> * Supported starting ICL (Ville)
>>> * Use the higher limits from TRANS_VTOTAL register (Ville)
>>> v2:
>>> * Checkpatch warning (Manasi)
>>>
>>> Cc: Maarten Lankhorst
>>> Cc: Ville Syrjälä
>>> Signed-off-by: Manasi Navare
>> Reviewed-by: Ville Syrjälä
>>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
>>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>> index f07081815b80..15006764862b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
>>>DRM_MODE_FLAG_CLKDIV2))
>>> return MODE_BAD;
>>>
>>> - if (INTEL_GEN(dev_priv) >= 9 ||
>>> - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
>>> + if (INTEL_GEN(dev_priv) >= 11) {
>>> + hdisplay_max = 16384;
>>> + vdisplay_max = 8192;
>>> + htotal_max = 16384;
>>> + vtotal_max = 8192;
>>> + } else if (INTEL_GEN(dev_priv) >= 9 ||
>>> + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
>>> hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
>>> vdisplay_max = 4096;
>>> htotal_max = 8192;
>>> --
>>> 2.19.1
>> --
>> Ville Syrjälä
>> Intel
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: introduce INTEL_DISPLAY_ENABLED() (rev2)
== Series Details == Series: drm/i915: introduce INTEL_DISPLAY_ENABLED() (rev2) URL : https://patchwork.freedesktop.org/series/66610/ State : warning == Summary == $ dim checkpatch origin/drm-tip 63b6a8f6a4d6 drm/i915: introduce INTEL_DISPLAY_ENABLED() -:142: WARNING:LONG_LINE: line over 100 characters #142: FILE: drivers/gpu/drm/i915/i915_drv.h:2196: +#define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) total: 0 errors, 1 warnings, 0 checks, 81 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Extend MI_SEMAPHORE_WAIT
== Series Details == Series: drm/i915/tgl: Extend MI_SEMAPHORE_WAIT URL : https://patchwork.freedesktop.org/series/66625/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14389_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14389_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +12 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb2/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-iclb6/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_eio@reset-stress: - shard-apl: [PASS][3] -> [FAIL][4] ([fdo#109661]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-apl2/igt@gem_...@reset-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-apl6/igt@gem_...@reset-stress.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-apl2/igt@gem_workarou...@suspend-resume-context.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([fdo#103540]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-hsw4/igt@kms_f...@flip-vs-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-hsw2/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109642] / [fdo#111068]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb2/igt@kms_psr2_su@page_flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-iclb4/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-iclb1/igt@kms_psr@psr2_primary_page_flip.html Possible fixes * igt@gem_ctx_isolation@vcs1-none: - shard-iclb: [SKIP][17] ([fdo#109276]) -> [PASS][18] +10 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb3/igt@gem_ctx_isolat...@vcs1-none.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-iclb4/igt@gem_ctx_isolat...@vcs1-none.html * igt@gem_eio@unwedge-stress: - shard-apl: [INCOMPLETE][19] ([fdo#103927]) -> [PASS][20] +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-apl5/igt@gem_...@unwedge-stress.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-apl4/igt@gem_...@unwedge-stress.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [SKIP][21] ([fdo#111325]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-iclb6/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][23] ([fdo#104108]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-skl9/igt@gem_soft...@noreloc-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14389/shard-skl7/igt@gem_soft...@noreloc-s3.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-skl: [INCOMPLETE][25] ([fdo#104108] / [fdo#107807]) -> [PASS][26] [25]: https://intel
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: introduce INTEL_DISPLAY_ENABLED() (rev2)
== Series Details ==
Series: drm/i915: introduce INTEL_DISPLAY_ENABLED() (rev2)
URL : https://patchwork.freedesktop.org/series/66610/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6889 -> Patchwork_14398
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14398:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-tgl-u/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_14398 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724] /
[fdo#111214])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-icl-u3/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][7] -> [DMESG-FAIL][8] ([fdo#08])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][9] -> [WARN][10] ([fdo#109483])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][11] -> [DMESG-WARN][12] ([fdo#102614])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [PASS][13] -> [FAIL][14] ([fdo#103167])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u}: [INCOMPLETE][15] ([fdo#111593]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-tgl-u/igt@gem_exec_gttf...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-tgl-u/igt@gem_exec_gttf...@basic.html
* igt@gem_mmap_gtt@basic-write-gtt:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][19] ([fdo#111096]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_force_connector_basic@force-edid:
- fi-ilk-650: [DMESG-WARN][21] ([fdo#106387]) -> [PASS][22] +1
similar issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6889/fi-ilk-650/igt@kms_force_connector_ba...@force-edid.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14398/fi-ilk-650/igt@kms_force_connector_ba...@force-edid.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=10638
[Intel-gfx] [PATCH 3/3] drm/i915: Check that we do find forcewake domain on gen11+
By always requiring a valid forcewake domain, even
FORCEWAKE_NONE, we can make assertions that accesses
need to land on a valid domain and not go out of bounds.
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 46 +++--
drivers/gpu/drm/i915/intel_uncore.h | 4 ++-
2 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 94a97bf8c021..8e12b5334018 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -845,7 +845,7 @@ static int fw_range_cmp(u32 offset, const struct
intel_forcewake_range *entry)
})
static enum forcewake_domains
-find_fw_domain(struct intel_uncore *uncore, u32 offset)
+__find_fw_domain(struct intel_uncore *uncore, u32 offset)
{
const struct intel_forcewake_range *entry;
@@ -855,7 +855,7 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
fw_range_cmp);
if (!entry)
- return 0;
+ return FORCEWAKE_INVALID;
/*
* The list of FW domains depends on the SKU in gen11+ so we
@@ -872,6 +872,34 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
return entry->domains;
}
+static enum forcewake_domains
+find_fw_domain(struct intel_uncore *uncore, u32 offset)
+{
+ enum forcewake_domains fw_domains;
+
+ fw_domains = __find_fw_domain(uncore, offset);
+
+ if (fw_domains == FORCEWAKE_INVALID)
+ return FORCEWAKE_NONE;
+ else
+ return fw_domains;
+}
+
+static enum forcewake_domains
+find_fw_domain_check(struct intel_uncore *uncore, u32 offset)
+{
+ enum forcewake_domains fw_domains;
+
+ fw_domains = __find_fw_domain(uncore, offset);
+
+ if (WARN(fw_domains == FORCEWAKE_INVALID,
+"Unknown forcewake domain(s) accessed at 0x%x\n",
+offset))
+ return FORCEWAKE_ALL;
+
+ return fw_domains;
+}
+
#define GEN_FW_RANGE(s, e, d) \
{ .start = (s), .end = (e), .domains = (d) }
@@ -900,10 +928,10 @@ static const struct intel_forcewake_range
__vlv_fw_ranges[] = {
})
#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
- find_fw_domain(uncore, offset)
+ find_fw_domain_check(uncore, offset)
#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
- find_fw_domain(uncore, offset)
+ find_fw_domain_check(uncore, offset)
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const i915_reg_t gen8_shadowed_regs[] = {
@@ -1033,7 +1061,7 @@ static const struct intel_forcewake_range
__chv_fw_ranges[] = {
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
- GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0xb00, 0x1fff, FORCEWAKE_NONE), /* uncore range */
GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
@@ -1069,7 +1097,7 @@ static const struct intel_forcewake_range
__gen9_fw_ranges[] = {
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen11_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
- GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0xb00, 0x1fff, FORCEWAKE_NONE), /* uncore range */
GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
@@ -1092,7 +1120,7 @@ static const struct intel_forcewake_range
__gen11_fw_ranges[] = {
GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x24800, 0x3, FORCEWAKE_BLITTER),
- GEN_FW_RANGE(0x4, 0x1b, 0),
+ GEN_FW_RANGE(0x4, 0x1b, FORCEWAKE_NONE),
GEN_FW_RANGE(0x1c, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
@@ -1105,7 +1133,7 @@ static const struct intel_forcewake_range
__gen11_fw_ranges[] = {
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen12_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
- GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0xb00, 0x1fff, FORCEWAKE_NONE), /* uncore range */
GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
@@ -1132
[Intel-gfx] [PATCH 1/3] drm/i915: Update Gen11 forcewake ranges
Daniele noticed new render ranges in Gen11 fw table.
Bspec: 18331
Cc: Daniele Ceraolo Spurio
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 9e583f13a9e4..732082a72022 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -805,9 +805,6 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
/* We give fast paths for the really cool registers */
#define NEEDS_FORCE_WAKE(reg) ((reg) < 0x4)
-#define GEN11_NEEDS_FORCE_WAKE(reg) \
- ((reg) < 0x4 || ((reg) >= 0x1c && (reg) < 0x1dc000))
-
#define __gen6_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd; \
@@ -903,12 +900,7 @@ static const struct intel_forcewake_range
__vlv_fw_ranges[] = {
})
#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
-({ \
- enum forcewake_domains __fwd = 0; \
- if (GEN11_NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(uncore, offset); \
- __fwd; \
-})
+ find_fw_domain(uncore, offset)
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const i915_reg_t gen8_shadowed_regs[] = {
@@ -1005,8 +997,9 @@ static const struct intel_forcewake_range
__chv_fw_ranges[] = {
#define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
- if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
- __fwd = find_fw_domain(uncore, offset); \
+ const u32 __offset = (offset); \
+ if (!is_gen11_shadowed(__offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
__fwd; \
})
@@ -1065,9 +1058,11 @@ static const struct intel_forcewake_range
__gen11_fw_ranges[] = {
GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
- GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x24800, 0x3, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x4, 0x1b, 0),
--
2.17.1
___
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[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Introduce gen12 forcewake ranges
From: Michel Thierry
The media ranges extend beyond what gen11 gives so we can't piggypack
on gen11 ranges, even on read side.
Introduce a table for gen12 and accessors for it.
v2: correctly implement gen12_fwtable_write/read (Daniele)
v3: update with ranges from bspec.
v4: avoid GEN11_NEEDS_FORCEWAKE (Mika)
v5: bspec ref (Daniele)
BSpec: 52078
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 75 ++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 732082a72022..94a97bf8c021 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -902,6 +902,9 @@ static const struct intel_forcewake_range __vlv_fw_ranges[]
= {
#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
find_fw_domain(uncore, offset)
+#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
+ find_fw_domain(uncore, offset)
+
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const i915_reg_t gen8_shadowed_regs[] = {
RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
@@ -927,6 +930,20 @@ static const i915_reg_t gen11_shadowed_regs[] = {
/* TODO: Other registers are not yet used */
};
+static const i915_reg_t gen12_shadowed_regs[] = {
+ RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
+ GEN6_RPNSWREQ, /* 0xA008 */
+ GEN6_RC_VIDEO_FREQ, /* 0xA00C */
+ RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
+ RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C (base) */
+ RING_TAIL(GEN11_BSD2_RING_BASE),/* 0x1C4000 (base) */
+ RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
+ RING_TAIL(GEN11_BSD3_RING_BASE),/* 0x1D (base) */
+ RING_TAIL(GEN11_BSD4_RING_BASE),/* 0x1D4000 (base) */
+ RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
+ /* TODO: Other registers are not yet used */
+};
+
static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
{
u32 offset = i915_mmio_reg_offset(*reg);
@@ -949,6 +966,7 @@ static bool is_gen##x##_shadowed(u32 offset) \
__is_genX_shadowed(8)
__is_genX_shadowed(11)
+__is_genX_shadowed(12)
static enum forcewake_domains
gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
@@ -1003,6 +1021,15 @@ static const struct intel_forcewake_range
__chv_fw_ranges[] = {
__fwd; \
})
+#define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (!is_gen12_shadowed(__offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
+
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
@@ -1075,6 +1102,46 @@ static const struct intel_forcewake_range
__gen11_fw_ranges[] = {
GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
};
+/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __gen12_fw_ranges[] = {
+ GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
+ GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x24400, 0x247ff, FORCE
Re: [Intel-gfx] [PATCH] drm/i915: Don't unwedge if reset is disabled
On Monday, September 9, 2019 11:48:42 PM CEST Chris Wilson wrote: > Quoting Chris Wilson (2019-09-07 09:39:52) > > Quoting Daniele Ceraolo Spurio (2019-09-06 23:28:05) > > > > > > > > > On 9/5/19 2:09 AM, Janusz Krzysztofik wrote: > > > > When trying to reset a device with reset capability disabled or not > > > > supported while rings are full of requests, it has been observed when > > > > running in execlists submission mode that command stream buffer tail > > > > tends to be incremented by apparently still running GPU regardless of > > > > all requests being already cancelled and command stream buffer pointers > > > > reset. As a result, kernel panic on NULL pointer dereference occurs > > > > when a trace_ports() helper is called with command stream buffer tail > > > > incremented but request pointers being NULL during final > > > > __intel_gt_set_wedged() operation called from intel_gt_reset(). > > > > > > > > Skip actual reset procedure if reset is disabled or not supported. > > > > > > This last sentence is a bit confusing. You're not skipping the reset > > > procedure, you're skipping the attempt of unwedging and resetting again > > > after a reset & wedge already happened. > > > > Loss of email over the last week, so jumping in at the end. My gut > > response is that this is still just papering over the bug, as what you > > say above makes no sense. > > So my gut response was to the run on sentence, when all you needed to > say that without a successful reset prior to calling > reset_default_submission, the engine may still generate CS events out of > the blue. And I think the patch should be written to require the > successful reset. You are right, successful reset seems the only safe protection. But anyway, while digging deeper waiting for your clarification of that gut respone ;-) , I've discovered that symptoms from which the issue can be predicted may be sometimes observed during reset_prepere() as failing intel_engine_stop_cs(). Checking for that failure alone may be too weak as it can probably happen to succeed regardless of the uncertain hardware status, but anyway, what do you think about modifying reset_prepare() so it may fail with an error propagated from functions it calls, then calling reset_prepare() at the beginning of intel_gt_reset() and skiping over __intel_gt_unset_wedgede() and further steps (do_reset(), ..., reset_finish()) if reset_prepare() fails? Wouldn't that be a useful additional layer of protection? If you think the idea is worth of being considered, please have a look at my first attempt sent to trybot already before your explanation arrived: https://patchwork.freedesktop.org/patch/329840/?series=66447&rev=1 (don't complain on its commit message making no sense, please ;-) ). Thanks, Janusz > -Chris > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/9] drm/etnaviv: use drm_debug_enabled() to check for debug categories
On Fr, 2019-09-13 at 14:51 +0300, Jani Nikula wrote:
> Allow better abstraction of the drm_debug global variable in the
> future. No functional changes.
>
> Cc: Lucas Stach
> Cc: Russell King
> Cc: Christian Gmeiner
> Cc: etna...@lists.freedesktop.org
> Signed-off-by: Jani Nikula
Acked-by: Lucas Stach
> ---
> drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
> b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
> index 7e4e2959bf4f..32d9fac587f9 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
> @@ -326,7 +326,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32
> exec_state,
>
> lockdep_assert_held(&gpu->lock);
>
> - if (drm_debug & DRM_UT_DRIVER)
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
>
> link_target = etnaviv_cmdbuf_get_va(cmdbuf,
> @@ -459,13 +459,13 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32
> exec_state,
>etnaviv_cmdbuf_get_va(buffer,
> &gpu->mmu_context->cmdbuf_mapping)
>+ buffer->user_size - 4);
>
> - if (drm_debug & DRM_UT_DRIVER)
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> pr_info("stream link to 0x%08x @ 0x%08x %p\n",
> return_target,
> etnaviv_cmdbuf_get_va(cmdbuf,
> &gpu->mmu_context->cmdbuf_mapping),
> cmdbuf->vaddr);
>
> - if (drm_debug & DRM_UT_DRIVER) {
> + if (drm_debug_enabled(DRM_UT_DRIVER)) {
> print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
> cmdbuf->vaddr, cmdbuf->size, 0);
>
> @@ -484,6 +484,6 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32
> exec_state,
> VIV_FE_LINK_HEADER_PREFETCH(link_dwords),
> link_target);
>
> - if (drm_debug & DRM_UT_DRIVER)
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
> }
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Limit ourselves to just rcs0
== Series Details ==
Series: drm/i915/tgl: Limit ourselves to just rcs0
URL : https://patchwork.freedesktop.org/series/66652/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6890 -> Patchwork_14399
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/
Known issues
Here are the changes found in Patchwork_14399 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-threads:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-apl-guc/igt@gem_close_r...@basic-threads.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/fi-apl-guc/igt@gem_close_r...@basic-threads.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] /
[fdo#108569])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@kms_addfb_basic@invalid-get-prop:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +2
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u3/igt@kms_addfb_ba...@invalid-get-prop.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/fi-icl-u3/igt@kms_addfb_ba...@invalid-get-prop.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][9] -> [FAIL][10] ([fdo#109483])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_render_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][13] ([fdo#08]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111096]) -> [FAIL][18] ([fdo#111407])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14399/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (54 -> 45)
--
Missing(9): fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-tgl-u2 fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6890 -> Patchwork_14399
CI-20190529: 20190529
CI_DRM_6890: 85db8e7ffdfa727551a7d99e77a26c4befb8e640 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5180: 811b10e2bd7fd2cd8ced9bbb55361c178886bbbd @
git://anon
[Intel-gfx] [PATCH] drm/i915/tgl: Limit ourselves to just rcs0
More pruning away of features until we have a stable system and a basis
for debugging what's missing.
v2: Fixup vdbox/vebox fusing
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 8 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9236fccb3a83..ee9a7959204c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -799,6 +799,7 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.has_rc6 = false, /* XXX disabled for debugging */
.has_logical_ring_preemption = false, /* XXX disabled for debugging */
+ .engine_mask = BIT(RCS0), /* XXX reduced for debugging */
};
#undef GEN
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 50b05a5de53b..727089dcd280 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1004,8 +1004,10 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
GEN11_GT_VEBOX_DISABLE_SHIFT;
for (i = 0; i < I915_MAX_VCS; i++) {
- if (!HAS_ENGINE(dev_priv, _VCS(i)))
+ if (!HAS_ENGINE(dev_priv, _VCS(i))) {
+ vdbox_mask &= ~BIT(i);
continue;
+ }
if (!(BIT(i) & vdbox_mask)) {
info->engine_mask &= ~BIT(_VCS(i));
@@ -1026,8 +1028,10 @@ void intel_device_info_init_mmio(struct drm_i915_private
*dev_priv)
GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv));
for (i = 0; i < I915_MAX_VECS; i++) {
- if (!HAS_ENGINE(dev_priv, _VECS(i)))
+ if (!HAS_ENGINE(dev_priv, _VECS(i))) {
+ vebox_mask &= ~BIT(i);
continue;
+ }
if (!(BIT(i) & vebox_mask)) {
info->engine_mask &= ~BIT(_VECS(i));
--
2.23.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/print: add and use drm_debug_enabled()
== Series Details ==
Series: drm/print: add and use drm_debug_enabled()
URL : https://patchwork.freedesktop.org/series/66656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6890 -> Patchwork_14400
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/
Known issues
Here are the changes found in Patchwork_14400 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] /
[fdo#111381])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_linear_blits@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u3/igt@gem_linear_bl...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/fi-icl-u3/igt@gem_linear_bl...@basic.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][5] -> [DMESG-FAIL][6] ([fdo#111678])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@i915_selftest@live_workarounds:
- fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([fdo#111373])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-bsw-kefka/igt@i915_selftest@live_workarounds.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/fi-bsw-kefka/igt@i915_selftest@live_workarounds.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_render_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
* igt@gem_sync@basic-each:
- {fi-tgl-u}: [INCOMPLETE][13] ([fdo#111647]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-tgl-u/igt@gem_s...@basic-each.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/fi-tgl-u/igt@gem_s...@basic-each.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14400/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
Participating hosts (54 -> 45)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks
fi-bsw-cyan fi-kbl-7500u fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6890 -> Patchwork_14400
CI-20190529: 20190529
CI_DRM_6890: 85db8e7ffdfa727551a7d99e77a26c4befb8e640 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5180: 811b10e2bd7fd2cd8ced9bbb55361c178886bbbd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14400: 0cf240ef4bf2fa488c4a57142bc4cb9a8790c858 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0cf240ef4bf2 drm/print: rename drm_debug to __drm_debug to dis
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Update Gen11 forcewake ranges
== Series Details == Series: series starting with [1/3] drm/i915: Update Gen11 forcewake ranges URL : https://patchwork.freedesktop.org/series/6/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: Update Gen11 forcewake ranges Okay! Commit: drm/i915/tgl: Introduce gen12 forcewake ranges +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:393:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block Commit: drm/i915: Check that we do find forcewake domain on gen11+ Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Check that we do find forcewake domain on gen11+
Quoting Mika Kuoppala (2019-09-13 15:16:52) > By always requiring a valid forcewake domain, even > FORCEWAKE_NONE, we can make assertions that accesses > need to land on a valid domain and not go out of bounds. So since we only look up restricted ranges in the fw_table, we could just have a short selftest (intel_fw_table_check) to assert those ranges are filled and we have no holes. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC
== Series Details == Series: series starting with [1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC URL : https://patchwork.freedesktop.org/series/66626/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14391_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14391_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14391_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14391_full: ### IGT changes ### Possible regressions * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-iclb: [PASS][1] -> [SKIP][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb1/igt@i915_pm_rc6_reside...@rc6-accuracy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-iclb6/igt@i915_pm_rc6_reside...@rc6-accuracy.html Known issues Here are the changes found in Patchwork_14391_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-write-cpu-active: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([fdo#106107]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-skl9/igt@gem_exec_re...@basic-write-cpu-active.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-skl6/igt@gem_exec_re...@basic-write-cpu-active.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +16 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-iclb6/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([fdo#108686]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-glk6/igt@gem_tiled_swapp...@non-threaded.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-apl: [PASS][11] -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-apl3/igt@i915_pm_rc6_reside...@rc6-accuracy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-apl5/igt@i915_pm_rc6_reside...@rc6-accuracy.html - shard-glk: [PASS][13] -> [SKIP][14] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-glk1/igt@i915_pm_rc6_reside...@rc6-accuracy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-glk6/igt@i915_pm_rc6_reside...@rc6-accuracy.html - shard-kbl: [PASS][15] -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-kbl6/igt@i915_pm_rc6_reside...@rc6-accuracy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-kbl2/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][17] -> [FAIL][18] ([fdo#105363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-glk7/igt@kms_f...@flip-vs-expired-vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-glk7/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip_tiling@flip-x-tiled: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#108303]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb5/igt@kms_flip_til...@flip-x-tiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-iclb7/igt@kms_flip_til...@flip-x-tiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14391/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Update Gen11 forcewake ranges
== Series Details ==
Series: series starting with [1/3] drm/i915: Update Gen11 forcewake ranges
URL : https://patchwork.freedesktop.org/series/6/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6890 -> Patchwork_14401
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14401:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-tgl-u/igt@i915_pm_...@basic-rte.html
Known issues
Here are the changes found in Patchwork_14401 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@create-close:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u3/igt@gem_ba...@create-close.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-icl-u3/igt@gem_ba...@create-close.html
* igt@gem_ctx_create@basic-files:
- fi-cml-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#110566])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-cml-u2/igt@gem_ctx_cre...@basic-files.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#109483])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_render_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
* igt@gem_sync@basic-each:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111647]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-tgl-u/igt@gem_s...@basic-each.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-tgl-u/igt@gem_s...@basic-each.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][13] ([fdo#08]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14401/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6890 -> Patchwork_14401
CI-20190529: 20190529
CI_DRM_6890: 85db8e7ffdfa727551a7d99e77a26c4befb8e640 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5180: 811b10e2bd7fd2cd8ced9bbb55361c178886bbbd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14401: 9e9ce022994530974159c0
Re: [Intel-gfx] [PATCH] drm/i915/gt: Only unwedge if we can reset first
On Fri, Sep 13, 2019 at 08:47:20AM +0100, Chris Wilson wrote:
> Unwedging the GPU requires a successful GPU reset before we restore the
> default submission, or else we may see residual context switch events
> that we were not expecting.
>
> v2: Pull in the special-case reset_clobbers_display, and explain why it
> should be safe in the context of unwedging.
>
> Reported-by: Janusz Krzysztofik
> Signed-off-by: Chris Wilson
> Cc: Janusz Krzysztofik
> Cc: Daniele Ceraolo Spurio
> Cc: Ville Syrjälä
> Reviewed-by: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 30 ++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index ee52947eb31d..d3b1cdafd4c2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -7,6 +7,7 @@
> #include
> #include
>
> +#include "display/intel_display.h"
> #include "display/intel_display_types.h"
> #include "display/intel_overlay.h"
>
> @@ -729,6 +730,28 @@ static void nop_submit_request(struct i915_request
> *request)
> intel_engine_queue_breadcrumbs(engine);
> }
>
> +static bool reset_clobbers_display(struct drm_i915_private *i915)
> +{
> + struct intel_crtc *crtc;
> +
> + if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
> + return false;
> +
> + /*
> + * While this appears racy, we should only be inspecting the display
> + * state at runtime from inside a GPU reset, which will be serialized
> + * with modesets on affected machines. For a full device reset,
> + * we should already have cleared the active CRTC state in
> + * intel_prepare_reset().
> + */
> + for_each_intel_crtc(&i915->drm, crtc) {
> + if (crtc->active)
> + return true;
> + }
> +
> + return false;
> +}
> +
> static void __intel_gt_set_wedged(struct intel_gt *gt)
> {
> struct intel_engine_cs *engine;
> @@ -793,6 +816,7 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
> struct intel_gt_timelines *timelines = >->timelines;
> struct intel_timeline *tl;
> unsigned long flags;
> + bool ok;
>
> if (!test_bit(I915_WEDGED, >->reset.flags))
> return true;
> @@ -838,7 +862,11 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
> }
> spin_unlock_irqrestore(&timelines->lock, flags);
>
> - intel_gt_sanitize(gt, false);
> + ok = false;
> + if (!reset_clobbers_display(gt->i915))
> + ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
/me re-reading a lot of the reset code..
I'm rather confused about the whole reset flow. We now do a reset here,
but then we still do another one later on? Except for i915_gem_sanitize(),
which gets called during probe and resume so only does the single reset
I guess.
Hopefully we can't be marked as wedged during probe because I think
this gets called before crtc->active is populated so we'd just do the
reset anyway.
As for the resume cases, I think the display should be off already
when this gets called.
So I guess I'm not really sure what this check is meant to do for us.
> + if (!ok)
> + return false;
>
> /*
>* Undo nop_submit_request. We prevent all new i915 requests from
> --
> 2.23.0
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Limit ourselves to just rcs0 (rev2)
== Series Details ==
Series: drm/i915/tgl: Limit ourselves to just rcs0 (rev2)
URL : https://patchwork.freedesktop.org/series/66652/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6890 -> Patchwork_14402
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14402:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_fence@nb-await-default:
- {fi-tgl-u}: [PASS][1] -> [WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
* igt@gem_tiled_fence_blits@basic:
- {fi-tgl-u}: NOTRUN -> [FAIL][3] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-tgl-u/igt@gem_tiled_fence_bl...@basic.html
- {fi-tgl-u2}:NOTRUN -> [FAIL][4] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-tgl-u2/igt@gem_tiled_fence_bl...@basic.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: NOTRUN -> [SKIP][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_chamelium@common-hpd-after-suspend:
- {fi-tgl-u2}:NOTRUN -> [SKIP][6] +9 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-tgl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
Known issues
Here are the changes found in Patchwork_14402 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-write-gtt-no-prefault:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt-no-prefault.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt-no-prefault.html
* igt@i915_selftest@live_mman:
- fi-bsw-kefka: [PASS][9] -> [DMESG-WARN][10] ([fdo#111373])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-bsw-kefka/igt@i915_selftest@live_mman.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-bsw-kefka/igt@i915_selftest@live_mman.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][11] -> [FAIL][12] ([fdo#109635 ])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u2}:[INCOMPLETE][13] ([fdo#111593]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-tgl-u2/igt@gem_exec_gttf...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-tgl-u2/igt@gem_exec_gttf...@basic.html
* igt@gem_render_linear_blits@basic:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-icl-u3/igt@gem_render_linear_bl...@basic.html
* igt@gem_sync@basic-each:
- {fi-tgl-u}: [INCOMPLETE][17] ([fdo#111647]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-tgl-u/igt@gem_s...@basic-each.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-tgl-u/igt@gem_s...@basic-each.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][19] ([fdo#103167]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
- fi-icl-u2: [FAIL][21] ([fdo#103167]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6890/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14402/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/sh
Re: [Intel-gfx] [PATCH] drm/i915/gt: Only unwedge if we can reset first
Quoting Ville Syrjälä (2019-09-13 17:03:34)
> On Fri, Sep 13, 2019 at 08:47:20AM +0100, Chris Wilson wrote:
> > Unwedging the GPU requires a successful GPU reset before we restore the
> > default submission, or else we may see residual context switch events
> > that we were not expecting.
> >
> > v2: Pull in the special-case reset_clobbers_display, and explain why it
> > should be safe in the context of unwedging.
> >
> > Reported-by: Janusz Krzysztofik
> > Signed-off-by: Chris Wilson
> > Cc: Janusz Krzysztofik
> > Cc: Daniele Ceraolo Spurio
> > Cc: Ville Syrjälä
> > Reviewed-by: Daniele Ceraolo Spurio
> > ---
> > drivers/gpu/drm/i915/gt/intel_reset.c | 30 ++-
> > 1 file changed, 29 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> > b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index ee52947eb31d..d3b1cdafd4c2 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -7,6 +7,7 @@
> > #include
> > #include
> >
> > +#include "display/intel_display.h"
> > #include "display/intel_display_types.h"
> > #include "display/intel_overlay.h"
> >
> > @@ -729,6 +730,28 @@ static void nop_submit_request(struct i915_request
> > *request)
> > intel_engine_queue_breadcrumbs(engine);
> > }
> >
> > +static bool reset_clobbers_display(struct drm_i915_private *i915)
> > +{
> > + struct intel_crtc *crtc;
> > +
> > + if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
> > + return false;
> > +
> > + /*
> > + * While this appears racy, we should only be inspecting the display
> > + * state at runtime from inside a GPU reset, which will be serialized
> > + * with modesets on affected machines. For a full device reset,
> > + * we should already have cleared the active CRTC state in
> > + * intel_prepare_reset().
> > + */
> > + for_each_intel_crtc(&i915->drm, crtc) {
> > + if (crtc->active)
> > + return true;
> > + }
> > +
> > + return false;
> > +}
> > +
> > static void __intel_gt_set_wedged(struct intel_gt *gt)
> > {
> > struct intel_engine_cs *engine;
> > @@ -793,6 +816,7 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
> > struct intel_gt_timelines *timelines = >->timelines;
> > struct intel_timeline *tl;
> > unsigned long flags;
> > + bool ok;
> >
> > if (!test_bit(I915_WEDGED, >->reset.flags))
> > return true;
> > @@ -838,7 +862,11 @@ static bool __intel_gt_unset_wedged(struct intel_gt
> > *gt)
> > }
> > spin_unlock_irqrestore(&timelines->lock, flags);
> >
> > - intel_gt_sanitize(gt, false);
> > + ok = false;
> > + if (!reset_clobbers_display(gt->i915))
> > + ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
>
> /me re-reading a lot of the reset code..
>
> I'm rather confused about the whole reset flow. We now do a reset here,
> but then we still do another one later on? Except for i915_gem_sanitize(),
> which gets called during probe and resume so only does the single reset
> I guess.
The idea was to keep wedging as a separate process (since that gives
nice symmetry because set-wedge unset-wedge). We can merge it so
that we only do the single reset, but we still should keep the request
flushing in place, or we need to play games with rcu barriers again.
> Hopefully we can't be marked as wedged during probe because I think
> this gets called before crtc->active is populated so we'd just do the
> reset anyway.
I was hoping the crtcs would be off at that point... They weren't.
> As for the resume cases, I think the display should be off already
> when this gets called.
>
> So I guess I'm not really sure what this check is meant to do for us.
I gave up,
- intel_gt_sanitize(gt, false);
+ /* We must reset pending GPU events before restoring our submission */
+ ok = !HAS_EXECLISTS(gt->i915);
+ if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
+ ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
+ if (!ok)
+ return false;
-Chris
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/tgl: Enable the blitter ring for basic igt support
IGT depends on the blitter for several of its basic tests, so enable it.
Hopefully, this is not the straw that breaks the camel's back.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ee9a7959204c..8dc544180076 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -799,7 +799,7 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.has_rc6 = false, /* XXX disabled for debugging */
.has_logical_ring_preemption = false, /* XXX disabled for debugging */
- .engine_mask = BIT(RCS0), /* XXX reduced for debugging */
+ .engine_mask = BIT(RCS0) | BIT(BCS0), /* XXX reduced for debugging */
};
#undef GEN
--
2.23.0
___
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[Intel-gfx] [PATCH i-g-t] igt/gem_blits: Check for blitter support before use
Not all HW supports XY blitter commands, so check before use. In
particular, this makes it easier to debug the kernel.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
lib/i915/gem_submission.c | 28 +
lib/i915/gem_submission.h | 9 +++
tests/i915/gem_bad_blit.c | 1 +
tests/i915/gem_evict_alignment.c| 1 +
tests/i915/gem_evict_everything.c | 1 +
tests/i915/gem_linear_blits.c | 1 +
tests/i915/gem_persistent_relocs.c | 1 +
tests/i915/gem_reloc_vs_gpu.c | 1 +
tests/i915/gem_request_retire.c | 1 +
tests/i915/gem_set_tiling_vs_blt.c | 1 +
tests/i915/gem_softpin.c| 1 +
tests/i915/gem_tiled_blits.c| 1 +
tests/i915/gem_tiled_fence_blits.c | 1 +
tests/i915/gem_tiled_partial_pwrite_pread.c | 1 +
tests/i915/gem_userptr_blits.c | 1 +
15 files changed, 50 insertions(+)
diff --git a/lib/i915/gem_submission.c b/lib/i915/gem_submission.c
index 7602d7f68..4f9464931 100644
--- a/lib/i915/gem_submission.c
+++ b/lib/i915/gem_submission.c
@@ -225,3 +225,31 @@ void gem_test_engine(int i915, unsigned int engine)
igt_assert(!is_wedged(i915));
close(i915);
}
+
+int gem_cmdparser_version(int i915, uint32_t engine)
+{
+ int version = 0;
+ drm_i915_getparam_t gp = {
+ .param = I915_PARAM_CMD_PARSER_VERSION,
+ .value = &version,
+ };
+
+ ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
+ return version;
+}
+
+bool gem_has_blitter(int i915)
+{
+ unsigned int blt;
+
+ blt = 0;
+ if (intel_gen(intel_get_drm_devid(i915)) >= 6)
+ blt = I915_EXEC_BLT;
+
+ return gem_has_ring(i915, blt);
+}
+
+void gem_require_blitter(int i915)
+{
+ igt_require(gem_has_blitter(i915));
+}
diff --git a/lib/i915/gem_submission.h b/lib/i915/gem_submission.h
index 1f1d63fe5..6deb7e2d0 100644
--- a/lib/i915/gem_submission.h
+++ b/lib/i915/gem_submission.h
@@ -35,6 +35,15 @@ bool gem_has_semaphores(int fd);
bool gem_has_execlists(int fd);
bool gem_has_guc_submission(int fd);
+int gem_cmdparser_version(int i915, uint32_t engine);
+static inline bool gem_has_cmdparser(int i915, uint32_t engine)
+{
+ return gem_cmdparser_version(i915, engine) > 0;
+}
+
+bool gem_has_blitter(int i915);
+void gem_require_blitter(int i915);
+
void gem_test_engine(int fd, unsigned int engine);
int gem_reopen_driver(int fd);
diff --git a/tests/i915/gem_bad_blit.c b/tests/i915/gem_bad_blit.c
index 45dfc809b..27a34038c 100644
--- a/tests/i915/gem_bad_blit.c
+++ b/tests/i915/gem_bad_blit.c
@@ -98,6 +98,7 @@ igt_simple_main
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
diff --git a/tests/i915/gem_evict_alignment.c b/tests/i915/gem_evict_alignment.c
index 140d55837..da13fb656 100644
--- a/tests/i915/gem_evict_alignment.c
+++ b/tests/i915/gem_evict_alignment.c
@@ -195,6 +195,7 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
igt_fork_hang_detector(fd);
}
diff --git a/tests/i915/gem_evict_everything.c
b/tests/i915/gem_evict_everything.c
index f36076482..2580a0b23 100644
--- a/tests/i915/gem_evict_everything.c
+++ b/tests/i915/gem_evict_everything.c
@@ -185,6 +185,7 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
size = 1024 * 1024;
count = gem_aperture_size(fd);
diff --git a/tests/i915/gem_linear_blits.c b/tests/i915/gem_linear_blits.c
index a5359288e..07ca2f29e 100644
--- a/tests/i915/gem_linear_blits.c
+++ b/tests/i915/gem_linear_blits.c
@@ -227,6 +227,7 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
}
igt_subtest("basic")
diff --git a/tests/i915/gem_persistent_relocs.c
b/tests/i915/gem_persistent_relocs.c
index dff4e9a76..2ab7091ad 100644
--- a/tests/i915/gem_persistent_relocs.c
+++ b/tests/i915/gem_persistent_relocs.c
@@ -326,6 +326,7 @@ igt_main
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+ gem_require_blitter(fd);
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
/* disable reuse, otherwise the test fails */
diff --git a/tests/i915/gem_reloc_vs_gpu.c b/tests/i915/gem_reloc_vs_gpu.c
index 328730a9b..46f145177 100644
--- a/tests/i915/gem_reloc_vs_gpu.c
+++ b/tests/i915/gem_reloc_vs_gpu.c
@@ -304,6 +304,7 @@ igt_main
igt_fix
[Intel-gfx] [PATCH] drm/i915: Enable stolen for iommu on snb/ivb
Now that we have CI testing of iommu, let's enable stolen + iommu with a
lot more confidence that we can diagnose any potential erors.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Martin Peres
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index bfbc3e3daf92..c52ecf525c24 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -369,13 +369,6 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
return 0;
}
- if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) {
- dev_notice(dev_priv->drm.dev,
- "%s, disabling use of stolen memory\n",
- "DMAR active");
- return 0;
- }
-
if (resource_size(&intel_graphics_stolen_res) == 0)
return 0;
--
2.23.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Enable the blitter ring for basic igt support
== Series Details ==
Series: drm/i915/tgl: Enable the blitter ring for basic igt support
URL : https://patchwork.freedesktop.org/series/66673/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6891 -> Patchwork_14403
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/
Known issues
Here are the changes found in Patchwork_14403 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#08])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
Possible fixes
* igt@gem_exec_fence@basic-await-default:
- {fi-tgl-u2}:[FAIL][3] ([fdo#111562] / [fdo#111597]) -> [PASS][4]
+1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-tgl-u2/igt@gem_exec_fe...@basic-await-default.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/fi-tgl-u2/igt@gem_exec_fe...@basic-await-default.html
- {fi-tgl-u}: [FAIL][5] ([fdo#111562] / [fdo#111597]) -> [PASS][6]
+1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-tgl-u/igt@gem_exec_fe...@basic-await-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/fi-tgl-u/igt@gem_exec_fe...@basic-await-default.html
* igt@gem_linear_blits@basic:
- {fi-tgl-u}: [FAIL][7] ([fdo#111563]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-tgl-u/igt@gem_linear_bl...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/fi-tgl-u/igt@gem_linear_bl...@basic.html
* igt@gem_tiled_blits@basic:
- {fi-tgl-u}: [FAIL][9] ([fdo#111604]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-tgl-u/igt@gem_tiled_bl...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/fi-tgl-u/igt@gem_tiled_bl...@basic.html
* igt@gem_tiled_fence_blits@basic:
- {fi-tgl-u}: [FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-tgl-u/igt@gem_tiled_fence_bl...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/fi-tgl-u/igt@gem_tiled_fence_bl...@basic.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-u4}:[DMESG-WARN][13] ([fdo#106107] / [fdo#106350]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14403/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
[fdo#111563]: https://bugs.freedesktop.org/show_bug.cgi?id=111563
[fdo#111564]: https://bugs.freedesktop.org/show_bug.cgi?id=111564
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
[fdo#111604]: https://bugs.freedesktop.org/show_bug.cgi?id=111604
Participating hosts (52 -> 45)
--
Additional (2): fi-icl-u3 fi-skl-6600u
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-gdg-551 fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6891 -> Patchwork_14403
CI-20190529: 20190529
CI_DRM_6891: 77f0ebb91e6a0dfd3e2531479f28e9738b83 @
git://anongit.freedesktop.org/g
[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Verify the LRC register layout between init and HW
Before we submit the first context to HW, we need to construct a valid
image of the register state. This layout is defined by the HW and should
match the layout generated by HW when it saves the context image.
Asserting that this should be equivalent should help avoid any undefined
behaviour and verify that we haven't missed anything important!
Of course, having insisted that the initial register state within the
LRC should match that returned by HW, we need to ensure that it does.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 656 --
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 62 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 141
drivers/gpu/drm/i915/i915_perf.c | 35 +-
drivers/gpu/drm/i915/i915_perf.h | 5 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
7 files changed, 639 insertions(+), 263 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index f1c0e5d958f3..3eb3c4fab110 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1115,7 +1115,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq,
offset = i915_ggtt_offset(ce->state) +
LRC_STATE_PN * PAGE_SIZE +
-(CTX_R_PWR_CLK_STATE + 1) * 4;
+CTX_R_PWR_CLK_STATE * 4;
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = lower_32_bits(offset);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a3f0e4999744..64fa2db5905f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -230,9 +230,9 @@ static int __execlists_context_alloc(struct intel_context
*ce,
struct intel_engine_cs *engine);
static void execlists_init_reg_state(u32 *reg_state,
-struct intel_context *ce,
-struct intel_engine_cs *engine,
-struct intel_ring *ring);
+const struct intel_context *ce,
+const struct intel_engine_cs *engine,
+const struct intel_ring *ring);
static inline u32 intel_hws_preempt_address(struct intel_engine_cs *engine)
{
@@ -464,6 +464,411 @@ lrc_descriptor(struct intel_context *ce, struct
intel_engine_cs *engine)
return desc;
}
+static u32 *set_offsets(u32 *regs,
+ const u8 *data,
+ const struct intel_engine_cs *engine)
+#define NOP(x) (BIT(7) | (x))
+#define LRI(count, flags) ((flags) << 6 | (count))
+#define POSTED BIT(0)
+#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))
+#define REG16(x) \
+ (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \
+ (((x) >> 2) & 0x7f)
+#define END() 0
+{
+ const u32 base = engine->mmio_base;
+
+ while (*data) {
+ u8 count, flags;
+
+ if (*data & BIT(7)) { /* skip */
+ regs += *data++ & ~BIT(7);
+ continue;
+ }
+
+ count = *data & 0x3f;
+ flags = *data >> 6;
+ data++;
+
+ *regs = MI_LOAD_REGISTER_IMM(count);
+ if (flags & POSTED)
+ *regs |= MI_LRI_FORCE_POSTED;
+ if (INTEL_GEN(engine->i915) >= 11)
+ *regs |= MI_LRI_CS_MMIO;
+ regs++;
+
+ GEM_BUG_ON(!count);
+ do {
+ u32 offset = 0;
+ u8 v;
+
+ do {
+ v = *data++;
+ offset <<= 7;
+ offset |= v & ~BIT(7);
+ } while (v & BIT(7));
+
+ *regs = base + (offset << 2);
+ regs += 2;
+ } while (--count);
+ }
+
+ return regs;
+}
+
+static const u8 gen8_xcs_offsets[] = {
+ NOP(1),
+ LRI(11, 0),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x11c),
+ REG(0x114),
+ REG(0x118),
+
+ NOP(9),
+ LRI(9, 0),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ NOP(13),
+ LRI(2, 0),
+ REG16(0x200),
+ REG(0x028),
+
+ END(),
+};
+
+static const u8 gen9_xcs_offsets[] = {
+ NOP(1),
+ LRI(14, POSTED),
+ REG16(0x244),
+
[Intel-gfx] [PATCH 1/2] drm/i915: Show the logical context ring state on dumping
Include the active context register state when dumping the engine.
Suggested-by: Mika Kuoppala
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index a8014c59b388..3c176b0f4b45 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1404,6 +1404,11 @@ void intel_engine_dump(struct intel_engine_cs *engine,
rq->timeline->hwsp_offset);
print_request_ring(m, rq);
+
+ if (rq->hw_context->lrc_reg_state) {
+ drm_printf(m, "Logical Ring Context:\n");
+ hexdump(m, rq->hw_context->lrc_reg_state, PAGE_SIZE);
+ }
}
spin_unlock_irqrestore(&engine->active.lock, flags);
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/tgl: Extend MI_SEMAPHORE_WAIT
On Tigerlake, MI_SEMAPHORE_WAIT grew an extra dword, so be sure to
update the length field and emit that extra parameter and any padding
noop as required.
v2: Define the token shift while we are adding the updated MI_SEMAPHORE_WAIT
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
Cc: Michal Winiarski
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 71 ++--
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/i915_request.c | 21 --
4 files changed, 83 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index fbad403ab7ac..da2025bc332c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -112,6 +112,7 @@
#define MI_SEMAPHORE_SIGNALMI_INSTR(0x1b, 0) /* GEN8+ */
#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
+#define MI_SEMAPHORE_WAIT_TOKENMI_INSTR(0x1c, 3) /* GEN12+ */
#define MI_SEMAPHORE_POLL(1 << 15)
#define MI_SEMAPHORE_SAD_GT_SDD (0 << 12)
#define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12)
@@ -119,6 +120,7 @@
#define MI_SEMAPHORE_SAD_LTE_SDD (3 << 12)
#define MI_SEMAPHORE_SAD_EQ_SDD (4 << 12)
#define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
+#define MI_SEMAPHORE_TOKEN_SHIFT 5
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
#define MI_STORE_DWORD_IMM_GEN4MI_INSTR(0x20, 2)
#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 64fa2db5905f..c74fc75e4980 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3237,6 +3237,22 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct
i915_request *request, u32 *cs)
return gen8_emit_fini_breadcrumb_footer(request, cs);
}
+static u32 *
+gen11_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
+{
+ cs = gen8_emit_ggtt_write_rcs(cs,
+ request->fence.seqno,
+ request->timeline->hwsp_offset,
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_TILE_CACHE_FLUSH |
+ PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_DC_FLUSH_ENABLE |
+ PIPE_CONTROL_FLUSH_ENABLE);
+
+ return gen8_emit_fini_breadcrumb_footer(request, cs);
+}
+
/*
* Note that the CS instruction pre-parser will not stall on the breadcrumb
* flush and will continue pre-fetching the instructions after it before the
@@ -3255,8 +3271,49 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct
i915_request *request, u32 *cs)
* All the above applies only to the instructions themselves. Non-inline data
* used by the instructions is not pre-fetched.
*/
-static u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *request,
- u32 *cs)
+
+static u32 *gen12_emit_preempt_busywait(struct i915_request *request, u32 *cs)
+{
+ *cs++ = MI_SEMAPHORE_WAIT_TOKEN |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_EQ_SDD;
+ *cs++ = 0;
+ *cs++ = intel_hws_preempt_address(request->engine);
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = MI_NOOP;
+
+ return cs;
+}
+
+static __always_inline u32*
+gen12_emit_fini_breadcrumb_footer(struct i915_request *request, u32 *cs)
+{
+ *cs++ = MI_USER_INTERRUPT;
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ if (intel_engine_has_semaphores(request->engine))
+ cs = gen12_emit_preempt_busywait(request, cs);
+
+ request->tail = intel_ring_offset(request, cs);
+ assert_ring_tail_valid(request->ring, request->tail);
+
+ return gen8_emit_wa_tail(request, cs);
+}
+
+static u32 *gen12_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
+{
+ cs = gen8_emit_ggtt_write(cs,
+ request->fence.seqno,
+ request->timeline->hwsp_offset,
+ 0);
+
+ return gen12_emit_fini_breadcrumb_footer(request, cs);
+}
+
+static u32 *
+gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
{
cs = gen8_emit_ggtt_write_rcs(cs,
request->fence.seqno,
@@ -3268,7 +3325,7 @@ static u32 *gen11_emit_fini_breadcrumb_rcs(struct
i915_request *request,
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
-
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Enable guc logging on guc log relay write (rev2)
== Series Details == Series: drm/i915/guc: Enable guc logging on guc log relay write (rev2) URL : https://patchwork.freedesktop.org/series/66502/ State : success == Summary == CI Bug Log - changes from CI_DRM_6885_full -> Patchwork_14392_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14392_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-queue-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb6/igt@gem_exec_sched...@preempt-queue-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +19 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-iclb6/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-glk6/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-apl4/igt@gem_workarou...@suspend-resume-context.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_cursor@pipe-a-primary-size-256: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-hsw2/igt@kms_plane_cur...@pipe-a-primary-size-256.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-hsw2/igt@kms_plane_cur...@pipe-a-primary-size-256.html * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([fdo#106885]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-skl5/igt@kms_plane_multi...@atomic-pipe-a-tiling-yf.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-skl1/igt@kms_plane_multi...@atomic-pipe-a-tiling-yf.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb2/igt@kms_psr2_su@page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-iclb5/igt@kms_psr2_su@page_flip.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#108341]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb3/igt@kms_psr@no_drrs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6885/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14392/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html Possible fixes * igt@gem_eio@
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable stolen for iommu on snb/ivb
== Series Details ==
Series: drm/i915: Enable stolen for iommu on snb/ivb
URL : https://patchwork.freedesktop.org/series/66675/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6891 -> Patchwork_14404
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14404 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14404, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14404/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14404:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14404/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_fence@nb-await-default:
- {fi-tgl-u}: [FAIL][3] ([fdo#111562] / [fdo#111597]) -> [WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14404/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
Known issues
Here are the changes found in Patchwork_14404 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-u4}:[DMESG-WARN][5] ([fdo#106107] / [fdo#106350]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14404/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][7] ([fdo#103167]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14404/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [FAIL][10] ([fdo#111096])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14404/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
[fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
Participating hosts (52 -> 47)
--
Additional (2): fi-icl-u3 fi-skl-6600u
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6891 -> Patchwork_14404
CI-20190529: 20190529
CI_DRM_6891: 77f0ebb91e6a0dfd3e2531479f28e9738b83 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5180: 811b10e2bd7fd2cd8ced9bbb55361c178886bbbd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14404: 74d98cdf523aa51a109ca933610da2cbabd24788 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
74d98cdf523a drm/i915: Enable stolen for iommu on snb/ivb
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14404/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Show the logical context ring state on dumping
== Series Details == Series: series starting with [1/2] drm/i915: Show the logical context ring state on dumping URL : https://patchwork.freedesktop.org/series/66678/ State : warning == Summary == $ dim checkpatch origin/drm-tip 70695b168708 drm/i915: Show the logical context ring state on dumping af19daf5cecf drm/i915/selftests: Verify the LRC register layout between init and HW -:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #60: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:473: +#define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) -:61: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #61: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:474: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) -:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects? #61: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:474: +#define REG16(x) \ + (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x1)), \ + (((x) >> 2) & 0x7f) total: 1 errors, 0 warnings, 2 checks, 1088 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Update Gen11 forcewake ranges
On 9/13/19 7:16 AM, Mika Kuoppala wrote:
Daniele noticed new render ranges in Gen11 fw table.
Bspec: 18331
Cc: Daniele Ceraolo Spurio
Signed-off-by: Mika Kuoppala
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/intel_uncore.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 9e583f13a9e4..732082a72022 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -805,9 +805,6 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
/* We give fast paths for the really cool registers */
#define NEEDS_FORCE_WAKE(reg) ((reg) < 0x4)
-#define GEN11_NEEDS_FORCE_WAKE(reg) \
- ((reg) < 0x4 || ((reg) >= 0x1c && (reg) < 0x1dc000))
-
#define __gen6_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd; \
@@ -903,12 +900,7 @@ static const struct intel_forcewake_range
__vlv_fw_ranges[] = {
})
#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
-({ \
- enum forcewake_domains __fwd = 0; \
- if (GEN11_NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(uncore, offset); \
- __fwd; \
-})
+ find_fw_domain(uncore, offset)
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const i915_reg_t gen8_shadowed_regs[] = {
@@ -1005,8 +997,9 @@ static const struct intel_forcewake_range
__chv_fw_ranges[] = {
#define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
- if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
- __fwd = find_fw_domain(uncore, offset); \
+ const u32 __offset = (offset); \
+ if (!is_gen11_shadowed(__offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
__fwd; \
})
@@ -1065,9 +1058,11 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
- GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x24800, 0x3, FORCEWAKE_BLITTER),
GEN_FW_RANGE(0x4, 0x1b, 0),
___
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/4] i915/gem_exec_balancer: Beware the migratory fence
On Sat, 7 Sep 2019 at 13:00, Chris Wilson wrote: > > If the object needs to be migrated, it may will need GPU relocs and so > have an exclusive fence showing up in the write domain. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Introduce gen12 forcewake ranges
On 9/13/19 7:16 AM, Mika Kuoppala wrote:
From: Michel Thierry
The media ranges extend beyond what gen11 gives so we can't piggypack
on gen11 ranges, even on read side.
Introduce a table for gen12 and accessors for it.
v2: correctly implement gen12_fwtable_write/read (Daniele)
v3: update with ranges from bspec.
v4: avoid GEN11_NEEDS_FORCEWAKE (Mika)
v5: bspec ref (Daniele)
BSpec: 52078
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_uncore.c | 75 ++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 732082a72022..94a97bf8c021 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -902,6 +902,9 @@ static const struct intel_forcewake_range __vlv_fw_ranges[]
= {
#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
find_fw_domain(uncore, offset)
+#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
+ find_fw_domain(uncore, offset)
The gen12 read path is now the same as the gen11 one so we could skip
this, but I agree it looks nice having symmetrical read/write functions
so I'm ok with keeping it. The table matches the specs, so:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const i915_reg_t gen8_shadowed_regs[] = {
RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
@@ -927,6 +930,20 @@ static const i915_reg_t gen11_shadowed_regs[] = {
/* TODO: Other registers are not yet used */
};
+static const i915_reg_t gen12_shadowed_regs[] = {
+ RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
+ GEN6_RPNSWREQ, /* 0xA008 */
+ GEN6_RC_VIDEO_FREQ, /* 0xA00C */
+ RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
+ RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C (base) */
+ RING_TAIL(GEN11_BSD2_RING_BASE),/* 0x1C4000 (base) */
+ RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
+ RING_TAIL(GEN11_BSD3_RING_BASE),/* 0x1D (base) */
+ RING_TAIL(GEN11_BSD4_RING_BASE),/* 0x1D4000 (base) */
+ RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
+ /* TODO: Other registers are not yet used */
+};
+
static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
{
u32 offset = i915_mmio_reg_offset(*reg);
@@ -949,6 +966,7 @@ static bool is_gen##x##_shadowed(u32 offset) \
__is_genX_shadowed(8)
__is_genX_shadowed(11)
+__is_genX_shadowed(12)
static enum forcewake_domains
gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
@@ -1003,6 +1021,15 @@ static const struct intel_forcewake_range
__chv_fw_ranges[] = {
__fwd; \
})
+#define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (!is_gen12_shadowed(__offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
+
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
@@ -1075,6 +1102,46 @@ static const struct intel_forcewake_range
__gen11_fw_ranges[] = {
GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
};
+/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __gen12_fw_ranges[] = {
+ GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
+ GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
+ GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
+
[Intel-gfx] [CI 1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC
Make both GuC and HuC to use "." as the separator. Hardcode the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC. The current convention being: _uc_..patch.bin Update the versions of HuC being loaded of the platforms. SKL - v2.0.0 BXT - v2.0.0 KBL - v4.0.0 GLK - v4.0.0 CFL - KBL v4.0.0 ICL - v9.0.0 CML - v4.0.0 v2: Remove the separator parameter altogether from __MAKE_UC_FW_PATH.(Daniele) - Squash all firmware update patches (Daniele) v3: s/huc/HuC - Correct the order of platforms - Change REVID of cml to 5(Michal) - Code space changes in huc_def (Daniele) Suggested-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Signed-off-by: Anusha Srivatsa Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 296a82603be0..ea9a807abd4f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -39,26 +39,27 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * Must be ordered based on platform + revid, from newer to older. */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ - fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ - fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 8, 4, 3238)) \ - fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ - fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \ - fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \ - fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01, 8, 2893)) \ - fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 1398)) - -#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ + fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ + fw_def(COFFEELAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ + fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ + fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 2, 0, 0)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0)) + +#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \ "i915/" \ __stringify(prefix_) name_ \ - __stringify(major_) separator_ \ - __stringify(minor_) separator_ \ + __stringify(major_) "." \ + __stringify(minor_) "." \ __stringify(patch_) ".bin" #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \ - __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_) + __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_) #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \ - __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_) + __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_) /* All blobs need to be declared via MODULE_FIRMWARE() */ #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Extend MI_SEMAPHORE_WAIT (rev2)
== Series Details == Series: drm/i915/tgl: Extend MI_SEMAPHORE_WAIT (rev2) URL : https://patchwork.freedesktop.org/series/66625/ State : failure == Summary == Applying: drm/i915/tgl: Extend MI_SEMAPHORE_WAIT Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_lrc.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_lrc.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/tgl: Extend MI_SEMAPHORE_WAIT When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] HAX: force enable_guc=2
Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index d29ade3b7de6..f9fbb1f2fabf 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,7 +54,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, 2) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Show the logical context ring state on dumping
== Series Details ==
Series: series starting with [1/2] drm/i915: Show the logical context ring
state on dumping
URL : https://patchwork.freedesktop.org/series/66678/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6891 -> Patchwork_14405
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14405/
New tests
-
New tests have been introduced between CI_DRM_6891 and Patchwork_14405:
### New IGT tests (1) ###
* igt@i915_selftest@live_gt_lrc:
- Statuses : 43 pass(s)
- Exec time: [0.36, 1.37] s
Known issues
Here are the changes found in Patchwork_14405 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-blb-e6850/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14405/fi-blb-e6850/igt@i915_module_l...@reload.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][3] -> [DMESG-WARN][4] ([fdo#106387]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14405/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@gem_exec_fence@nb-await-default:
- {fi-tgl-u}: [FAIL][5] ([fdo#111562] / [fdo#111597]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14405/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-u4}:[DMESG-WARN][7] ([fdo#106107] / [fdo#106350]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14405/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][9] ([fdo#103167]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14405/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
[fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
Participating hosts (52 -> 46)
--
Additional (1): fi-skl-6600u
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6891 -> Patchwork_14405
CI-20190529: 20190529
CI_DRM_6891: 77f0ebb91e6a0dfd3e2531479f28e9738b83 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5180: 811b10e2bd7fd2cd8ced9bbb55361c178886bbbd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14405: af19daf5cecf3c070190078fa04b1d893e540904 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
af19daf5cecf drm/i915/selftests: Verify the LRC register layout between init
and HW
70695b168708 drm/i915: Show the logical context ring state on dumping
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14405/index.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC
== Series Details == Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC URL : https://patchwork.freedesktop.org/series/66685/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9f557dad9e62 drm/i915/uc: Update HuC firmware naming convention and load latest HuC 6562c3a2f0b7 HAX: force enable_guc=2 -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 3/7] drm: Add DisplayPort colorspace property
On Thu, Sep 12, 2019 at 02:33:34PM +0300, Gwan-gyeong Mun wrote:
> Because between HDMI and DP have different colorspaces, it renames
> drm_mode_create_colorspace_property() function to
> drm_mode_create_hdmi_colorspace_property() function for HDMI connector.
> And it adds drm_mode_create_dp_colorspace_property() function for creating
> of DP colorspace property.
> In order to apply changed and added drm api, i915 driver has channged.
>
> v3: Addressed review comments from Ville
> - Add new colorimetry options for DP 1.4a spec.
> - Separate set of colorimetry enum values for DP.
> v4: Add additional comments to struct drm_prop_enum_list.
> Polishing an enum string of struct drm_prop_enum_list
> v5: Change definitions of DRM_MODE_COLORIMETRYs to follow HDMI prefix and
> DP abbreviations.
> Add missed variables on dp_colorspaces.
> Fix typo. [Uma]
> v6: Addressed review comments from Ilia and Ville
>- Split drm_mode_create_colorspace_property() to DP and HDMI connector.
> v7: Fix typo [Jani Saarinen]
> Fix white space.
>
> Signed-off-by: Gwan-gyeong Mun
> Reviewed-by: Uma Shankar
> ---
> drivers/gpu/drm/drm_connector.c | 110 +++---
> .../gpu/drm/i915/display/intel_connector.c| 21 +++-
> include/drm/drm_connector.h | 11 +-
> 3 files changed, 121 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 4c766624b20d..656f72c1b3d7 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -882,6 +882,47 @@ static const struct drm_prop_enum_list
> hdmi_colorspaces[] = {
> { DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-P3_RGB_Theater" },
> };
>
> +/*
> + * As per DP 1.4a spec, 2.2.5.7.5 VSC SDP Payload for Pixel
> Encoding/Colorimetry
> + * Format Table 2-120
> + */
> +static const struct drm_prop_enum_list dp_colorspaces[] = {
> + /* For Default case, driver will set the colorspace */
> + { DRM_MODE_COLORIMETRY_DEFAULT, "Default" },
> + /* Colorimetry based on sRGB (IEC 61966-2-1) */
> + { DRM_MODE_COLORIMETRY_CEA_RGB, "CEA_RGB" },
We already have other mechanism for the CEA vs. IT RGB.
I don't think we want to add another one. So I'd drop this.
> + { DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED, "RGB_Wide_Gamut_Fixed_Point" },
> + /* Colorimetry based on scRGB (IEC 61966-2-2) */
> + { DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT, "RGB_Wide_Gamut_Floating_Point"
> },
> + /* Colorimetry based on IEC 61966-2-5 */
> + { DRM_MODE_COLORIMETRY_OPRGB, "opRGB" },
> + /* Colorimetry based on SMPTE RP 431-2 */
> + { DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65, "DCI-P3_RGB_D65" },
> + { DRM_MODE_COLORIMETRY_RGB_CUSTOM_COLOR_PROFILE,
> "RGB_Custom_Color_Profile" },
I'd also drop this since we have no way to supply the profile anyway.
> + /* Colorimetry based on ITU-R BT.2020 */
> + { DRM_MODE_COLORIMETRY_BT2020_RGB, "BT2020_RGB" },
> + { DRM_MODE_COLORIMETRY_BT601_YCC, "BT601_YCC" },
> + { DRM_MODE_COLORIMETRY_BT709_YCC, "BT709_YCC" },
> + /* Standard Definition Colorimetry based on IEC 61966-2-4 */
> + { DRM_MODE_COLORIMETRY_XVYCC_601, "XVYCC_601" },
> + /* High Definition Colorimetry based on IEC 61966-2-4 */
> + { DRM_MODE_COLORIMETRY_XVYCC_709, "XVYCC_709" },
> + /* Colorimetry based on IEC 61966-2-1/Amendment 1 */
> + { DRM_MODE_COLORIMETRY_SYCC_601, "SYCC_601" },
> + /* Colorimetry based on IEC 61966-2-5 [33] */
> + { DRM_MODE_COLORIMETRY_OPYCC_601, "opYCC_601" },
> + /* Colorimetry based on ITU-R BT.2020 */
> + { DRM_MODE_COLORIMETRY_BT2020_CYCC, "BT2020_CYCC" },
> + /* Colorimetry based on ITU-R BT.2020 */
> + { DRM_MODE_COLORIMETRY_BT2020_YCC, "BT2020_YCC" },
> + /*
> + * Colorimetry based on Digital Imaging and Communications in Medicine
> + * (DICOM) Part 14: Grayscale Standard Display Function
> + */
> + { DRM_MODE_COLORIMETRY_Y_ONLY_DICOM_P14_GRAYSCALE,
> "Y_ONLY_DICOM_Part_14_Grayscale" },
> + { DRM_MODE_COLORIMETRY_RAW_CUSTOM_COLOR_PROFILE,
> "Raw_Custom_Color_Profile" },
And these last two seem rather esoteric as well. I don't think any
driver supports RAW/Y stuff so I'd drop them too.
> +};
> +
> /**
> * DOC: standard connector properties
> *
> @@ -1674,7 +1715,6 @@ EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
> * DOC: standard connector properties
> *
> * Colorspace:
> - * drm_mode_create_colorspace_property - create colorspace property
> * This property helps select a suitable colorspace based on the sink
> * capability. Modern sink devices support wider gamut like BT2020.
> * This helps switch to BT2020 mode if the BT2020 encoded video stream
> @@ -1694,32 +1734,68 @@ EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
> * - This property is just to inform sink what colorspace
> *source is trying to drive.
> *
> + * Because b
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming
convention and load latest HuC
URL : https://patchwork.freedesktop.org/series/66685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6891 -> Patchwork_14407
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14407/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14407:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_fence@nb-await-default:
- {fi-tgl-u}: [FAIL][1] ([fdo#111562] / [fdo#111597]) -> [WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14407/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
Known issues
Here are the changes found in Patchwork_14407 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14407/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@gem_exec_fence@nb-await-default:
- {fi-tgl-u2}:[FAIL][5] ([fdo#111562] / [fdo#111597]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-tgl-u2/igt@gem_exec_fe...@nb-await-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14407/fi-tgl-u2/igt@gem_exec_fe...@nb-await-default.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-u4}:[DMESG-WARN][7] ([fdo#106107] / [fdo#106350]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6891/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14407/fi-icl-u4/igt@i915_module_l...@reload-with-fault-injection.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
[fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
Participating hosts (52 -> 47)
--
Additional (2): fi-icl-u3 fi-skl-6600u
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6891 -> Patchwork_14407
CI-20190529: 20190529
CI_DRM_6891: 77f0ebb91e6a0dfd3e2531479f28e9738b83 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5180: 811b10e2bd7fd2cd8ced9bbb55361c178886bbbd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14407: 6562c3a2f0b7644e81e824b54802d371421c3918 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6562c3a2f0b7 HAX: force enable_guc=2
9f557dad9e62 drm/i915/uc: Update HuC firmware naming convention and load latest
HuC
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14407/index.html
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[Intel-gfx] [PATCH 2/4] drm/i915: Allow downscale factor of <3.0 on glk+ for all formats
From: Ville Syrjälä
Bspec says that glk+ max downscale factor is <3.0 for all pixel formats.
Older platforms had a max of <2.0 for NV12. Update the code to deal with
this.
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1f26ee8adc4e..7e29ba675241 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14556,7 +14556,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int max_scale, mult;
+ int max_scale;
int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
if (!crtc_state->base.enable)
@@ -14577,8 +14577,11 @@ skl_max_scale(const struct intel_crtc_state
*crtc_state,
*or
*cdclk/crtc_clock
*/
- mult = drm_format_info_is_yuv_semiplanar(format) ? 2 : 3;
- tmpclk1 = (1 << 16) * mult - 1;
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
+ !drm_format_info_is_yuv_semiplanar(format))
+ tmpclk1 = 0x3 - 1;
+ else
+ tmpclk1 = 0x2 - 1;
tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
max_scale = min(tmpclk1, tmpclk2);
--
2.21.0
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[Intel-gfx] [PATCH 1/4] drm/i915: Replace is_planar_yuv_format() with drm_format_info_is_yuv_semiplanar()
From: Ville Syrjälä
There's a helper in drm_fourcc.h these days to check of we're dealing
with a two plane YUV format. Make use if it.
Also s/plane/color_plane/ in skl_plane_relative_data_rate() to reduce
the confusion.
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 5 ++--
drivers/gpu/drm/i915/display/intel_display.c | 10 +++
drivers/gpu/drm/i915/display/intel_display.h | 3 ++-
drivers/gpu/drm/i915/display/intel_sprite.c | 20 +++---
drivers/gpu/drm/i915/display/intel_sprite.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 27 +--
6 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d1fcdf206da4..476ef0906ba0 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -144,6 +144,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
struct intel_plane_state
*new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
+ const struct drm_framebuffer *fb = new_plane_state->base.fb;
int ret;
new_crtc_state->active_planes &= ~BIT(plane->id);
@@ -164,11 +165,11 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->active_planes |= BIT(plane->id);
if (new_plane_state->base.visible &&
- is_planar_yuv_format(new_plane_state->base.fb->format->format))
+ drm_format_info_is_yuv_semiplanar(fb->format))
new_crtc_state->nv12_planes |= BIT(plane->id);
if (new_plane_state->base.visible &&
- new_plane_state->base.fb->format->format == DRM_FORMAT_C8)
+ fb->format->format == DRM_FORMAT_C8)
new_crtc_state->c8_planes |= BIT(plane->id);
if (new_plane_state->base.visible || old_plane_state->base.visible)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4e001113e828..1f26ee8adc4e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3545,7 +3545,7 @@ int skl_check_plane_surface(struct intel_plane_state
*plane_state)
* Handle the AUX surface first since
* the main surface setup depends on it.
*/
- if (is_planar_yuv_format(fb->format->format)) {
+ if (drm_format_info_is_yuv_semiplanar(fb->format)) {
ret = skl_check_nv12_aux_surface(plane_state);
if (ret)
return ret;
@@ -5463,7 +5463,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
return 0;
}
- if (format && is_planar_yuv_format(format->format) &&
+ if (format && drm_format_info_is_yuv_semiplanar(format) &&
(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
return -EINVAL;
@@ -5540,7 +5540,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
- fb && is_planar_yuv_format(fb->format->format))
+ fb && drm_format_info_is_yuv_semiplanar(fb->format))
need_scaler = true;
ret = skl_update_scaler(crtc_state, force_detach,
@@ -14552,7 +14552,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
int
skl_max_scale(const struct intel_crtc_state *crtc_state,
- u32 pixel_format)
+ const struct drm_format_info *format)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -14577,7 +14577,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
*or
*cdclk/crtc_clock
*/
- mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
+ mult = drm_format_info_is_yuv_semiplanar(format) ? 2 : 3;
tmpclk1 = (1 << 16) * mult - 1;
tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
max_scale = min(tmpclk1, tmpclk2);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index f4ddde171655..66330fcb10d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -34,6 +34,7 @@ struct drm_connector;
struct drm_device;
struct drm_encoder;
struct drm_file;
+struct drm_format_info;
struct drm_framebuffer;
struct drm_i915_error_state_buf;
struct drm_i915_gem_object;
@@ -548,7 +549,7 @@ void intel_crtc_arm_fifo_under
[Intel-gfx] [PATCH 3/4] drm/i915: Extract intel_modeset_calc_cdclk()
From: Ville Syrjälä
Exfiltrate the cdclk code from intel_modeset_checks() into
intel_modeset_calc_cdclk().
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 135 ++-
drivers/gpu/drm/i915/display/intel_cdclk.h | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 123 +
3 files changed, 135 insertions(+), 129 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ea3f75c72fe8..43564295b864 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
@@ -1772,9 +1773,9 @@ bool intel_cdclk_needs_modeset(const struct
intel_cdclk_state *a,
* Returns:
* True if the CDCLK states require just a cd2x divider update, false if not.
*/
-bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *a,
- const struct intel_cdclk_state *b)
+static bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,
+ const struct intel_cdclk_state *b)
{
/* Older hw doesn't have the capability */
if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
@@ -1793,8 +1794,8 @@ bool intel_cdclk_needs_cd2x_update(struct
drm_i915_private *dev_priv,
* Returns:
* True if the CDCLK states don't match, false if they do.
*/
-bool intel_cdclk_changed(const struct intel_cdclk_state *a,
-const struct intel_cdclk_state *b)
+static bool intel_cdclk_changed(const struct intel_cdclk_state *a,
+ const struct intel_cdclk_state *b)
{
return intel_cdclk_needs_modeset(a, b) ||
a->voltage_level != b->voltage_level;
@@ -2220,6 +2221,130 @@ static int bxt_modeset_calc_cdclk(struct
intel_atomic_state *state)
return 0;
}
+static int intel_lock_all_pipes(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ /* Add all pipes to the state */
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+ }
+
+ return 0;
+}
+
+static int intel_modeset_all_pipes(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ /*
+* Add all pipes to the state, and force
+* a modeset on all the active ones.
+*/
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+ int ret;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ if (!crtc_state->base.active ||
+ drm_atomic_crtc_needs_modeset(&crtc_state->base))
+ continue;
+
+ crtc_state->base.mode_changed = true;
+
+ ret = drm_atomic_add_affected_connectors(&state->base,
+&crtc->base);
+ if (ret)
+ return ret;
+
+ ret = drm_atomic_add_affected_planes(&state->base,
+&crtc->base);
+ if (ret)
+ return ret;
+
+ crtc_state->update_planes |= crtc_state->active_planes;
+ }
+
+ return 0;
+}
+
+int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ enum pipe pipe;
+ int ret;
+
+ if (!dev_priv->display.modeset_calc_cdclk)
+ return 0;
+
+ ret = dev_priv->display.modeset_calc_cdclk(state);
+ if (ret)
+ return ret;
+
+ /*
+* Writes to dev_priv->cdclk.logical must protected by
+* holding all the crtc locks, even if we don't end up
+* touching the hardware
+*/
+ if (intel_cdclk_changed(&dev_priv->cdclk.logical,
+ &state->cdclk.logical)) {
+ ret = intel_lock_all_pipes(state);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (is_power_of_2(state->active_pipes)) {
+ struct intel_crtc *crtc;
+ struct intel_crtc_st
[Intel-gfx] [PATCH 0/4] drm/i915: Extracts from plane min cdclk/fp16 series
From: Ville Syrjälä A few reviewed patches from the plane min cdclk/fp16 series. Just feeding them to CI. Ville Syrjälä (4): drm/i915: Replace is_planar_yuv_format() with drm_format_info_is_yuv_semiplanar() drm/i915: Allow downscale factor of <3.0 on glk+ for all formats drm/i915: Extract intel_modeset_calc_cdclk() drm/i915: s/pipe_config/crtc_state/ in intel_crtc_atomic_check() .../gpu/drm/i915/display/intel_atomic_plane.c | 5 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 135 +++- drivers/gpu/drm/i915/display/intel_cdclk.h| 6 +- drivers/gpu/drm/i915/display/intel_display.c | 194 -- drivers/gpu/drm/i915/display/intel_display.h | 3 +- drivers/gpu/drm/i915/display/intel_sprite.c | 20 +- drivers/gpu/drm/i915/display/intel_sprite.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 27 ++- 8 files changed, 193 insertions(+), 198 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: s/pipe_config/crtc_state/ in intel_crtc_atomic_check()
From: Ville Syrjälä
Clean up the mess with the drm vs. intel types in
intel_crtc_atomic_check() and rename varibles accordingly.
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 54 ++--
1 file changed, 26 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5fc522723662..714867d755af 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11760,25 +11760,24 @@ static bool c8_planes_changed(const struct
intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
-static int intel_crtc_atomic_check(struct drm_crtc *crtc,
- struct drm_crtc_state *crtc_state)
+static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
+ struct drm_crtc_state *_crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_crtc_state *pipe_config =
- to_intel_crtc_state(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(_crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(_crtc_state);
int ret;
- bool mode_changed = needs_modeset(pipe_config);
+ bool mode_changed = needs_modeset(crtc_state);
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
- mode_changed && !crtc_state->active)
- pipe_config->update_wm_post = true;
+ mode_changed && !crtc_state->base.active)
+ crtc_state->update_wm_post = true;
- if (mode_changed && crtc_state->enable &&
+ if (mode_changed && crtc_state->base.enable &&
dev_priv->display.crtc_compute_clock &&
- !WARN_ON(pipe_config->shared_dpll)) {
- ret = dev_priv->display.crtc_compute_clock(intel_crtc,
- pipe_config);
+ !WARN_ON(crtc_state->shared_dpll)) {
+ ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
if (ret)
return ret;
}
@@ -11787,19 +11786,19 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
* May need to update pipe gamma enable bits
* when C8 planes are getting enabled/disabled.
*/
- if (c8_planes_changed(pipe_config))
- crtc_state->color_mgmt_changed = true;
+ if (c8_planes_changed(crtc_state))
+ crtc_state->base.color_mgmt_changed = true;
- if (mode_changed || pipe_config->update_pipe ||
- crtc_state->color_mgmt_changed) {
- ret = intel_color_check(pipe_config);
+ if (mode_changed || crtc_state->update_pipe ||
+ crtc_state->base.color_mgmt_changed) {
+ ret = intel_color_check(crtc_state);
if (ret)
return ret;
}
ret = 0;
if (dev_priv->display.compute_pipe_wm) {
- ret = dev_priv->display.compute_pipe_wm(pipe_config);
+ ret = dev_priv->display.compute_pipe_wm(crtc_state);
if (ret) {
DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
return ret;
@@ -11815,7 +11814,7 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
* old state and the new state. We can program these
* immediately.
*/
- ret = dev_priv->display.compute_intermediate_wm(pipe_config);
+ ret = dev_priv->display.compute_intermediate_wm(crtc_state);
if (ret) {
DRM_DEBUG_KMS("No valid intermediate pipe watermarks
are possible\n");
return ret;
@@ -11823,21 +11822,20 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
}
if (INTEL_GEN(dev_priv) >= 9) {
- if (mode_changed || pipe_config->update_pipe)
- ret = skl_update_scaler_crtc(pipe_config);
+ if (mode_changed || crtc_state->update_pipe)
+ ret = skl_update_scaler_crtc(crtc_state);
if (!ret)
- ret = icl_check_nv12_planes(pipe_config);
+ ret = icl_check_nv12_planes(crtc_state);
if (!ret)
- ret = skl_check_pipe_max_pixel_rate(intel_crtc,
- pipe_config);
+ ret = skl_check_pipe_max_pixel_rate(crtc, crtc_state);
if (!ret)
- ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
-
[Intel-gfx] [CI] drm/i915/tgl: Re-enable rc6
From: Mika Kuoppala
We think that we got rc6 problems sorted out. Flip the switch
and let CI expose our tendency to naive optimism.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ee9a7959204c..e4a26bbd8788 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -797,7 +797,6 @@ static const struct intel_device_info
intel_tigerlake_12_info = {
.display.has_modular_fia = 1,
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
- .has_rc6 = false, /* XXX disabled for debugging */
.has_logical_ring_preemption = false, /* XXX disabled for debugging */
.engine_mask = BIT(RCS0), /* XXX reduced for debugging */
};
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Extracts from plane min cdclk/fp16 series
== Series Details ==
Series: drm/i915: Extracts from plane min cdclk/fp16 series
URL : https://patchwork.freedesktop.org/series/66688/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6892 -> Patchwork_14408
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14408/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14408:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_fence@nb-await-default:
- {fi-tgl-u}: [FAIL][1] ([fdo#111562] / [fdo#111597]) -> [WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14408/fi-tgl-u/igt@gem_exec_fe...@nb-await-default.html
Known issues
Here are the changes found in Patchwork_14408 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14408/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-icl-u3/igt@gem_mmap_...@basic-short.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14408/fi-icl-u3/igt@gem_mmap_...@basic-short.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14408/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14408/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
[fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6892 -> Patchwork_14408
CI-20190529: 20190529
CI_DRM_6892: 7724a568fbda56a403dbb53126500c523b0820d5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5182: f7104497049e3761ac297b66fd5586849b3cfcc8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14408: 18e91160749ceb5cdb38a95f0bcb7bb03573a1a6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
18e91160749c drm/i915: s/pipe_config/crtc_state/ in intel_crtc_atomic_check()
416952eae978 drm/i915: Extract intel_modeset_calc_cdclk()
3f6d80386b69 drm/i915: Allow downscale factor of <3.0 on glk+ for all formats
fea66370095a drm/i915: Replace is_planar_yuv_format() with
drm_format_info_is_yuv_semiplanar()
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14408/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Re-enable rc6
== Series Details ==
Series: drm/i915/tgl: Re-enable rc6
URL : https://patchwork.freedesktop.org/series/66689/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6892 -> Patchwork_14409
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/
Known issues
Here are the changes found in Patchwork_14409 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724] /
[fdo#111214])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-icl-u3/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-icl-u3/igt@i915_module_l...@reload.html
* igt@i915_module_load@reload-no-display:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-icl-u3/igt@i915_module_l...@reload-no-display.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-icl-u3/igt@i915_module_l...@reload-no-display.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][7] ([fdo#103927]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_mmap_gtt@basic-copy:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-icl-u3/igt@gem_mmap_...@basic-copy.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-tgl-u}: [SKIP][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-tgl-u/igt@i915_pm_...@basic-pci-d3-state.html
- {fi-tgl-u2}:[SKIP][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-tgl-u2/igt@i915_pm_...@basic-pci-d3-state.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-tgl-u2/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-u}: [FAIL][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-tgl-u/igt@i915_pm_...@basic-rte.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-tgl-u/igt@i915_pm_...@basic-rte.html
- {fi-tgl-u2}:[FAIL][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-tgl-u2/igt@i915_pm_...@basic-rte.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-tgl-u2/igt@i915_pm_...@basic-rte.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][19] ([fdo#111407]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6892/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14409/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6892 -> Patchwork_14409
CI-20190529: 20190529
CI_DRM_6892: 7724a568fbda56a403dbb53126500c523b0820d5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5182: f7104497049e3761ac297b66fd5586849b3cfcc8 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14409: 35e699e31b1bea9b9fbe330f718a5f79c76ca73c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
35e699e31b1b drm/i915/tgl: Re-enable rc6
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patc
Re: [Intel-gfx] [CI] drm/i915/tgl: Re-enable rc6
Quoting Chris Wilson (2019-09-13 21:06:38) > From: Mika Kuoppala > > We think that we got rc6 problems sorted out. Flip the switch > and let CI expose our tendency to naive optimism. > > Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] i915 firmware updates (CMl- GuC,HuC; TGL-DMC,ICL-DMC, HuC Updates-SKL,BXT,KBL,GLK,ICL)
Hi, Kyle, Josh,Ben Ignore the previous PR and kindly consider this one. It has another new update and is the latest one- The following changes since commit 6c6918ad8ae0dfb2cb591484eba525409980c16f: linux-firmware: Update firmware file for Intel Bluetooth AX201 (2019-09-09 04:22:42 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware cml_tgl-icl-dmc_huc_updates for you to fetch changes up to 3ea84e52306e7b78cc6d727d9a41c8449146d765: drm/i915/firmware: Add v9.0.0 of HuC for Icelake (2019-09-13 14:48:47 -0700) Anusha Srivatsa (9): drm/i915/firmware: Add v1.09 of DMC for ICL drm/i915/firmware: Add v2.04 of DMC for TGL drm/i915/firmware: Add v33 of GuC for CML drm/i915/firmware: Add v2.0.0 of HuC for Skylake drm/i915/firmware: Add v4.0.0 of HuC for Kabylake drm/i915/firmware: Add v2.0.0 of HuC for Broxton drm/i915/firmware: Add v4.0.0 of HuC for Geminilake drm/i915/firmware: Add v4.0.0 of HuC for Cometlake drm/i915/firmware: Add v9.0.0 of HuC for Icelake WHENCE | 28 i915/bxt_huc_2.0.0.bin | Bin 0 -> 149824 bytes i915/cml_guc_33.0.0.bin | Bin 0 -> 182912 bytes i915/cml_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/glk_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/icl_dmc_ver1_09.bin | Bin 0 -> 25952 bytes i915/icl_huc_9.0.0.bin | Bin 0 -> 498880 bytes i915/kbl_huc_4.0.0.bin | Bin 0 -> 226048 bytes i915/skl_huc_2.0.0.bin | Bin 0 -> 136320 bytes i915/tgl_dmc_ver2_04.bin | Bin 0 -> 18436 bytes 10 files changed, 28 insertions(+) create mode 100644 i915/bxt_huc_2.0.0.bin create mode 100644 i915/cml_guc_33.0.0.bin create mode 100644 i915/cml_huc_4.0.0.bin create mode 100644 i915/glk_huc_4.0.0.bin create mode 100644 i915/icl_dmc_ver1_09.bin create mode 100644 i915/icl_huc_9.0.0.bin create mode 100644 i915/kbl_huc_4.0.0.bin create mode 100644 i915/skl_huc_2.0.0.bin create mode 100644 i915/tgl_dmc_ver2_04.bin Thanks, Anusha ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/14] drm/i915/tgl: Add initial dkl pll support
From: Lucas De Marchi
The disable function can be the same as for MG phy since the same
registers are used. The others are different as registers changed,
also adding a empty dkl_pll_write() to be implemented later.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 115 +-
1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 84e734d44828..424f9213c80d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3086,6 +3086,76 @@ static bool mg_pll_get_hw_state(struct drm_i915_private
*dev_priv,
return ret;
}
+static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll,
+struct intel_dpll_hw_state *hw_state)
+{
+ const enum intel_dpll_id id = pll->info->id;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(id);
+ intel_wakeref_t wakeref;
+ bool ret = false;
+ u32 val;
+
+ wakeref = intel_display_power_get_if_enabled(dev_priv,
+POWER_DOMAIN_DISPLAY_CORE);
+ if (!wakeref)
+ return false;
+
+ val = I915_READ(MG_PLL_ENABLE(tc_port));
+ if (!(val & PLL_ENABLE))
+ goto out;
+
+ /*
+* All registers read here have the same HIP_INDEX_REG even though
+* they are on different building blocks
+*/
+ I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
+
+ hw_state->mg_refclkin_ctl = I915_READ(DKL_REFCLKIN_CTL(tc_port));
+ hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+
+ hw_state->mg_clktop2_hsclkctl =
+ I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
+ hw_state->mg_clktop2_hsclkctl &=
+ MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
+
+ hw_state->mg_clktop2_coreclkctl1 =
+ I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ hw_state->mg_clktop2_coreclkctl1 &=
+ MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+
+ hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port));
+ hw_state->mg_pll_div0 &= (DKL_PLL_DIV0_INTEG_COEFF_MASK |
+ DKL_PLL_DIV0_PROP_COEFF_MASK |
+ DKL_PLL_DIV0_FBPREDIV_MASK |
+ DKL_PLL_DIV0_FBDIV_INT_MASK);
+
+ hw_state->mg_pll_div1 = I915_READ(DKL_PLL_DIV1(tc_port));
+ hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
+ DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
+
+ hw_state->mg_pll_ssc = I915_READ(DKL_PLL_SSC(tc_port));
+ hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
+DKL_PLL_SSC_STEP_LEN_MASK |
+DKL_PLL_SSC_STEP_NUM_MASK |
+DKL_PLL_SSC_EN);
+
+ hw_state->mg_pll_bias = I915_READ(DKL_PLL_BIAS(tc_port));
+ hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
+ DKL_PLL_BIAS_FBDIV_FRAC_MASK);
+
+ hw_state->mg_pll_tdc_coldst_bias =
+ I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
+
+ ret = true;
+out:
+ intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
+ return ret;
+}
+
static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state,
@@ -3220,6 +3290,12 @@ static void icl_mg_pll_write(struct drm_i915_private
*dev_priv,
POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
}
+static void dkl_pll_write(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ /* TODO */
+}
+
static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
@@ -3325,6 +3401,32 @@ static void mg_pll_enable(struct drm_i915_private
*dev_priv,
/* DVFS post sequence would be here. See the comment above. */
}
+static void dkl_pll_enable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ /*
+* From spec: MG register instances are being used for TypeC in general.
+* The same MG register instances should be programmed for Dekel PLLs
+* as well.
+*/
+ i915_reg_t enable_reg =
+ MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+
+ icl_pll_power_enable(dev_priv, pll, enable_reg);
+
[Intel-gfx] [PATCH 07/14] drm/i915/tgl: Add support for dkl pll write
From: Vandita Kulkarni
Add a new function to write to dkl phy pll registers. As per the
bspec all the registers are read modify write.
Signed-off-by: Vandita Kulkarni
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 ++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 424f9213c80d..afc9b609b63d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3293,7 +3293,70 @@ static void icl_mg_pll_write(struct drm_i915_private
*dev_priv,
static void dkl_pll_write(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- /* TODO */
+ struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
+ u32 val;
+
+ /*
+* All registers programmed here have the same HIP_INDEX_REG even
+* though on different building block
+*/
+ I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
+
+ /* All the registers are RMW */
+ val = I915_READ(DKL_REFCLKIN_CTL(tc_port));
+ val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+ val |= hw_state->mg_refclkin_ctl;
+ I915_WRITE(DKL_REFCLKIN_CTL(tc_port), val);
+
+ val = I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+ val |= hw_state->mg_clktop2_coreclkctl1;
+ I915_WRITE(DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
+
+ val = I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
+ val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
+ val |= hw_state->mg_clktop2_hsclkctl;
+ I915_WRITE(DKL_CLKTOP2_HSCLKCTL(tc_port), val);
+
+ val = I915_READ(DKL_PLL_DIV0(tc_port));
+ val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK |
+ DKL_PLL_DIV0_PROP_COEFF_MASK |
+ DKL_PLL_DIV0_FBPREDIV_MASK |
+ DKL_PLL_DIV0_FBDIV_INT_MASK);
+ val |= hw_state->mg_pll_div0;
+ I915_WRITE(DKL_PLL_DIV0(tc_port), val);
+
+ val = I915_READ(DKL_PLL_DIV1(tc_port));
+ val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
+DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
+ val |= hw_state->mg_pll_div1;
+ I915_WRITE(DKL_PLL_DIV1(tc_port), val);
+
+ val = I915_READ(DKL_PLL_SSC(tc_port));
+ val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
+ DKL_PLL_SSC_STEP_LEN_MASK |
+ DKL_PLL_SSC_STEP_NUM_MASK |
+ DKL_PLL_SSC_EN);
+ val |= hw_state->mg_pll_ssc;
+ I915_WRITE(DKL_PLL_SSC(tc_port), val);
+
+ val = I915_READ(DKL_PLL_BIAS(tc_port));
+ val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
+ DKL_PLL_BIAS_FBDIV_FRAC_MASK);
+ val |= hw_state->mg_pll_bias;
+ I915_WRITE(DKL_PLL_BIAS(tc_port), val);
+
+ val = I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
+ DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
+ val |= hw_state->mg_pll_tdc_coldst_bias;
+ I915_WRITE(DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
+
+ POSTING_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
}
static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
--
2.23.0
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[Intel-gfx] [PATCH 13/14] drm/i915/tgl: Use dkl pll hardcoded values
From: "Taylor, Clinton A"
BSpec PLL calculation are not validated/ready yet, so for now it is
providing a table with hardcoded values to all DP link rates.
So for now lets override the calculated values with the hardcoded
ones.
With this hardcoded values the port clock calculation for 5.4Ghz
don't match but this is a minor error that we can live for now.
Bspec: 49204
Signed-off-by: Taylor, Clinton A
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 66 +++
1 file changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 25be6229b122..5b568dd57a5a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2667,6 +2667,65 @@ static bool tgl_dkl_pll_find_divisors(int clock_khz,
bool is_dp, bool use_ssc,
return false;
}
+struct tgl_dp_frequencies {
+ u32 hsclkctl;
+ u32 coreclkctl1;
+ u32 ssc_reg;
+};
+
+static void
+tgl_dkl_pll_overwrite_with_hardcoded_values(int clock_khz,
+ struct intel_dpll_hw_state *state,
+ bool is_dp)
+{
+ const struct tgl_dp_frequencies tgl_dkl_pll_dp_frequencies[] = {
+ { 0x011D, 0x10080510, 0x401320ff }, /* 8p1 */
+ { 0x121D, 0x10080510, 0x401320ff }, /* 5p4 */
+ { 0x521D, 0x10080A12, 0x401320ff }, /* 2p7 */
+ { 0x621D, 0x10080A12, 0x401320ff }, /* 1p62 */
+ };
+ int i;
+
+ if (!is_dp) {
+ /* No hardcoded values for HDMI */
+ MISSING_CASE(!is_dp);
+ return;
+ }
+
+ switch (clock_khz) {
+ case 81:
+ i = 0;
+ break;
+ case 54:
+ i = 1;
+ break;
+ case 27:
+ i = 2;
+ break;
+ case 162000:
+ i = 3;
+ break;
+ default:
+ MISSING_CASE(clock_khz);
+ return;
+ }
+
+ state->mg_clktop2_coreclkctl1 =
tgl_dkl_pll_dp_frequencies[i].coreclkctl1;
+ state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+
+ state->mg_clktop2_hsclkctl = tgl_dkl_pll_dp_frequencies[i].hsclkctl;
+ state->mg_clktop2_hsclkctl &= (MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK
|
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
+
+ state->mg_pll_ssc = tgl_dkl_pll_dp_frequencies[i].ssc_reg;
+ state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
+ DKL_PLL_SSC_STEP_LEN_MASK |
+ DKL_PLL_SSC_STEP_NUM_MASK |
+ DKL_PLL_SSC_EN);
+}
+
/*
* The specification for this function uses real numbers, so the math had to be
* adapted to integer-only calculation, that's why it looks so different.
@@ -2798,6 +2857,13 @@ static bool tgl_calc_dkl_pll_state(struct
intel_crtc_state *crtc_state,
DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
+ /*
+* BSpec PLL calculations are not validated/ready yet, so for now lets
+* fallback to the hardcoded table.
+*/
+ tgl_dkl_pll_overwrite_with_hardcoded_values(symbol_frequency,
+ pll_state, is_dp);
+
return true;
}
--
2.23.0
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[Intel-gfx] [PATCH 00/14] TGL TC enabling
This is all the patches required to have TC alt-mode working on TGL, no TBT or legacy support intented here but much of the work here will help those. The dkl pll calculation is not 100% ready, so it is using the hardcoded table provided but even with this table it results in a port_clock state mismatch when running at 5.4Ghz. Also I'm still debugging why enable clock gating after link training complete breaks all the following trainings. All of above is noted in the respective commit message. Other than the above the series is pretty much ready for reviews and testing. Make sure you have firmware of TC retimers updated. José Roberto de Souza (5): drm/i915/tgl: Finish modular FIA support on registers drm/i915/icl: Unify disable and enable phy clock gating functions drm/i915/tgl: Fix dkl phy register space addressing drm/i915/tgl: Check the UC health of tc controllers after power on drm/i915: Add dkl phy pll calculations Lucas De Marchi (2): drm/i915/tgl: Add initial dkl pll support drm/i915/tgl: initialize TC and TBT ports Taylor, Clinton A (5): drm/i915/tgl: Add missing ddi clock select during DP init sequence drm/i915/tgl: TC helper function to return pin mapping drm/i915/tgl: Fix driver crash when update_active_dpll is called drm/i915/tgl: Add dkl phy programming sequences drm/i915/tgl: Use dkl pll hardcoded values Vandita Kulkarni (2): drm/i915/tgl: Add dkl phy registers drm/i915/tgl: Add support for dkl pll write drivers/gpu/drm/i915/display/intel_ddi.c | 343 +++-- drivers/gpu/drm/i915/display/intel_display.c | 9 +- .../drm/i915/display/intel_display_power.c| 16 + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 456 +- drivers/gpu/drm/i915/display/intel_tc.c | 64 ++- drivers/gpu/drm/i915/display/intel_tc.h | 3 + drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 206 +++- 8 files changed, 1006 insertions(+), 94 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/14] drm/i915/tgl: Check the UC health of tc controllers after power on
New step added for TGL, requiring for us to check the TC
microcontroller health after power on TC aux.
BSpec: 49294
Signed-off-by: José Roberto de Souza
---
.../gpu/drm/i915/display/intel_display_power.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce88a27229ef..14e4ac6ee54d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -562,6 +562,8 @@ static void icl_tc_port_assert_ref_held(struct
drm_i915_private *dev_priv,
#endif
+#define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
+
static void
icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
@@ -578,6 +580,20 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
hsw_power_well_enable(dev_priv, power_well);
+
+ if (INTEL_GEN(dev_priv) >= 12 && !power_well->desc->hsw.is_tc_tbt) {
+ enum tc_port tc_port;
+
+ tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx);
+ val = I915_READ(HIP_INDEX_REG(tc_port));
+ val &= ~HIP_INDEX_MASK(tc_port);
+ val |= HIP_INDEX_INDEX_VAL(tc_port, 0x2);
+ I915_WRITE(HIP_INDEX_REG(tc_port), val);
+
+ if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port),
+ DKL_CMN_UC_DW27_UC_HEALTH, 1))
+ DRM_WARN("Timeout waiting TC uC health\n");
+ }
}
static void
--
2.23.0
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