[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/21] Revert "drm/i915/gem: Drop relocation slowpath"
== Series Details ==
Series: series starting with [01/21] Revert "drm/i915/gem: Drop relocation
slowpath"
URL : https://patchwork.freedesktop.org/series/75115/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8194 -> Patchwork_17096
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17096 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17096, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17096:
### IGT changes ###
Possible regressions
* igt@gem_close_race@basic-process:
- fi-ivb-3770:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-ivb-3770/igt@gem_close_r...@basic-process.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-ivb-3770/igt@gem_close_r...@basic-process.html
- fi-hsw-4770:[PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-hsw-4770/igt@gem_close_r...@basic-process.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-hsw-4770/igt@gem_close_r...@basic-process.html
- fi-hsw-4770r: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-hsw-4770r/igt@gem_close_r...@basic-process.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-hsw-4770r/igt@gem_close_r...@basic-process.html
* igt@gem_exec_fence@basic-await@rcs0:
- fi-blb-e6850: [PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-blb-e6850/igt@gem_exec_fence@basic-aw...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-blb-e6850/igt@gem_exec_fence@basic-aw...@rcs0.html
- fi-elk-e7500: [PASS][9] -> [DMESG-WARN][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@rcs0.html
- fi-pnv-d510:[PASS][11] -> [DMESG-WARN][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-pnv-d510/igt@gem_exec_fence@basic-aw...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-pnv-d510/igt@gem_exec_fence@basic-aw...@rcs0.html
- fi-ilk-650: [PASS][13] -> [DMESG-WARN][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-ilk-650/igt@gem_exec_fence@basic-aw...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-ilk-650/igt@gem_exec_fence@basic-aw...@rcs0.html
* igt@gem_exec_fence@basic-await@vcs0:
- fi-ilk-650: [PASS][15] -> [INCOMPLETE][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-ilk-650/igt@gem_exec_fence@basic-aw...@vcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-ilk-650/igt@gem_exec_fence@basic-aw...@vcs0.html
* igt@gem_render_tiled_blits@basic:
- fi-gdg-551: [PASS][17] -> [DMESG-WARN][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-gdg-551/igt@gem_render_tiled_bl...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-gdg-551/igt@gem_render_tiled_bl...@basic.html
* igt@i915_selftest@live@gem_contexts:
- fi-skl-lmem:[PASS][19] -> [DMESG-WARN][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-skl-lmem/igt@i915_selftest@live@gem_contexts.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gem_contexts:
- {fi-kbl-7560u}: NOTRUN -> [DMESG-WARN][21]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-kbl-7560u/igt@i915_selftest@live@gem_contexts.html
Known issues
Here are the changes found in Patchwork_17096 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-await@vcs0:
- fi-elk-e7500: [PASS][22] -> [INCOMPLETE][23] ([i915#66])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8194/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@vcs0.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17096/fi-elk-e7500/igt@gem_exec_fence@basic-aw...@vcs0.html
* igt@i915_selftest@live@execlists:
- fi-icl-y: [PASS][24] -> [DMESG-FAIL][25] ([fdo#108569])
[24]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning (rev2)
== Series Details == Series: drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning (rev2) URL : https://patchwork.freedesktop.org/series/75078/ State : success == Summary == CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17098 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/index.html Known issues Here are the changes found in Patchwork_17098 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@hangcheck: - fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#108569]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html Possible fixes * igt@i915_selftest@live@execlists: - fi-icl-dsi: [DMESG-FAIL][3] ([fdo#108569]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/fi-icl-dsi/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@hangcheck: - fi-icl-u2: [INCOMPLETE][5] ([fdo#108569]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 Participating hosts (49 -> 37) -- Missing(12): fi-ilk-m540 fi-bdw-samus fi-bdw-5557u fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-skl-6600u fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8195 -> Patchwork_17098 CI-20190529: 20190529 CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17098: 39b95b621dfcda82ef1437a6dfc7bd30df89e73d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 39b95b621dfc drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17098/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 14/16] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message
On Thu, 2020-03-05 at 15:12 -0500, Sean Paul wrote:
> From: Sean Paul
>
> Used to query whether an MST stream is encrypted or not.
>
> Signed-off-by: Sean Paul
>
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-s...@poorly.run
> #v4
>
> Changes in v4:
> -Added to the set
> Changes in v5:
> -None
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 117 ++
> include/drm/drm_dp_helper.h | 3 +
> include/drm/drm_dp_mst_helper.h | 44 ++
> 3 files changed, 164 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 6c62ad8f44142..5bba5aac86f31 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -25,6 +25,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -418,6 +419,22 @@ drm_dp_encode_sideband_req(const struct
> drm_dp_sideband_msg_req_body *req,
> memcpy([idx], req->u.i2c_write.bytes, req-
> >u.i2c_write.num_bytes);
> idx += req->u.i2c_write.num_bytes;
> break;
> + case DP_QUERY_STREAM_ENC_STATUS: {
> + const struct drm_dp_query_stream_enc_status *msg;
> +
> + msg = >u.enc_status;
> + buf[idx] = msg->stream_id;
> + idx++;
> + memcpy([idx], msg->client_id, sizeof(msg->client_id));
> + idx += sizeof(msg->client_id);
> + buf[idx] = 0;
> + buf[idx] |= msg->stream_event & GENMASK(1, 0);
> + buf[idx] |= msg->valid_stream_event ? BIT(2) : 0;
> + buf[idx] |= (msg->stream_behavior & GENMASK(1, 0)) << 3;
> + buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0;
> + idx++;
> + }
> + break;
> }
> raw->cur_len = idx;
> }
> @@ -930,6 +947,34 @@ static bool
> drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms
> return true;
> }
>
> +static bool
> +drm_dp_sideband_parse_query_stream_enc_status(
> + struct drm_dp_sideband_msg_rx *raw,
> + struct drm_dp_sideband_msg_reply_body *repmsg)
> +{
> + struct drm_dp_query_stream_enc_status_ack_reply *reply;
> +
> + reply = >u.enc_status;
> +
> + reply->stream_id = raw->msg[3];
> +
> + reply->reply_signed = raw->msg[2] & BIT(0);
> +
> + reply->hdcp_1x_device_present = raw->msg[2] & BIT(3);
> + reply->hdcp_2x_device_present = raw->msg[2] & BIT(4);
> +
> + reply->query_capable_device_present = raw->msg[2] & BIT(5);
> + reply->legacy_device_present = raw->msg[2] & BIT(6);
> + reply->unauthorizable_device_present = raw->msg[2] & BIT(7);
> +
> + reply->auth_completed = !!(raw->msg[1] & BIT(3));
> + reply->encryption_enabled = !!(raw->msg[1] & BIT(4));
> + reply->repeater_present = !!(raw->msg[1] & BIT(5));
> + reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6;
> +
> + return true;
> +}
I don't mind terribly either way, but since you're already using the
BIT/GENMASK() macros have you considered GET_BITFIELD()?
> +
> static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw,
> struct drm_dp_sideband_msg_reply_body
> *msg)
> {
> @@ -964,6 +1009,8 @@ static bool drm_dp_sideband_parse_reply(struct
> drm_dp_sideband_msg_rx *raw,
> return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg);
> case DP_CLEAR_PAYLOAD_ID_TABLE:
> return true; /* since there's nothing to parse */
> + case DP_QUERY_STREAM_ENC_STATUS:
> + return drm_dp_sideband_parse_query_stream_enc_status(raw,
> msg);
> default:
> DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type,
> drm_dp_mst_req_type_str(msg->req_type));
> @@ -1115,6 +1162,25 @@ static void build_power_updown_phy(struct
> drm_dp_sideband_msg_tx *msg,
> msg->path_msg = true;
> }
>
> +static int
> +build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8
> stream_id,
> + u8 *q_id)
> +{
> + struct drm_dp_sideband_msg_req_body req;
> +
> + req.req_type = DP_QUERY_STREAM_ENC_STATUS;
> + req.u.enc_status.stream_id = stream_id;
> + memcpy(req.u.enc_status.client_id, q_id,
> +sizeof(req.u.enc_status.client_id));
> + req.u.enc_status.stream_event = 0;
> + req.u.enc_status.valid_stream_event = false;
> + req.u.enc_status.stream_behavior = 0;
> + req.u.enc_status.valid_stream_behavior = false;
> +
> + drm_dp_encode_sideband_req(, msg);
> + return 0;
> +}
> +
> static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr
> *mgr,
> struct drm_dp_vcpi *vcpi)
> {
> @@ -3151,6 +3217,57 @@ int drm_dp_send_power_updown_phy(struct
> drm_dp_mst_topology_mgr *mgr,
> }
>
[Intel-gfx] [PATCH v20 06/10] drm/i915: Add proper SAGV support for TGL+
Let's refactor the whole SAGV logic, moving the main calculations from intel_can_enable_sagv to intel_compute_sagv_mask, which also handles this in a unified way calling gen specific functions to evaluate if SAGV is allowed for each crtc. If crtc sagv mask have been changed we serialize access and modify global state. intel_can_enable_sagv now uses bw_state which stores all information related to SAGV and is now a trivial helper. v2: - Rework watermark calculation algorithm to attempt to calculate Level 0 watermark with added sagv block time latency and check if it fits in DBuf in order to determine if SAGV can be enabled already at this stage, just as BSpec 49325 states. if that fails rollback to usual Level 0 latency and disable SAGV. - Remove unneeded tabs(James Ausmus) v3: Rebased the patch v4: - Added back interlaced check for Gen12 and added separate function for TGL SAGV check (thanks to James Ausmus for spotting) - Removed unneeded gen check - Extracted Gen12 SAGV decision making code to a separate function from skl_compute_wm v5: - Added SAGV global state to dev_priv, because we need to track all pipes, not only those in atomic state. Each pipe has now correspondent bit mask reflecting, whether it can tolerate SAGV or not(thanks to Ville Syrjala for suggestions). - Now using active flag instead of enable in crc usage check. v6: - Fixed rebase conflicts v7: - kms_cursor_legacy seems to get broken because of multiple memcpy calls when copying level 0 water marks for enabled SAGV, to fix this now simply using that field right away, without copying, for that introduced a new wm_level accessor which decides which wm_level to return based on SAGV state. v8: - Protect crtc_sagv_mask same way as we do for other global state changes: i.e check if changes are needed, then grab all crtc locks to serialize the changes(Ville Syrjälä) - Add crtc_sagv_mask caching in order to avoid needless recalculations (Matthew Roper) - Put back Gen12 SAGV switch in order to get it enabled in separate patch(Matthew Roper) - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper) - Check if there are no active pipes in intel_can_enable_sagv instead of platform specific functions(Matthew Roper), same for intel_has_sagv check. v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä) - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä) - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask - Extracted skl_plane_wm_level function and passing latency to separate patches(Ville Syrjälä) - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm (Ville Syrjälä) - Now using simple assignment for sagv_wm0 as it contains only pod types and no pointers(Ville Syrjälä) - Fixed intel_can_enable_sagv not to do double duty, now it only check SAGV bits by ANDing those between local and global state. The SAGV masks are now computed after watermarks are available, in order to be able to figure out if ddb ranges are fitting nicely. (Ville Syrjälä) - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic when using skl_plane_wm_level accessor, as we had previously for Gen11+ color plane and regular wm levels, so probably both has to be recalculated with additional SAGV block time for Level 0. v10: - Starting to use new global state for storing pipe_sagv_mask v11: - Fixed rebase conflict with recent drm-tip - Check if we really need to recalculate SAGV mask, otherwise bail out without making any changes. - Use cached SAGV result, instead of recalculating it everytime, if bw_state hasn't changed. v12: - Removed WARN from intel_can_enable_sagv, in some of the commits if we don't recalculated watermarks, bw_state is not recalculated, thus leading to SAGV state not recalculated by the commit state, which is still calling intel_can_enable_sagv function. Fix that by just analyzing the current global bw_state object - because we simply have no other objects related to that. v13: - Rebased, fixed warnings regarding long lines - Changed function call sites from intel_atomic_bw* to intel_wb_* as was suggested.(Jani Nikula) - Taken ddb_state_changed and bw_state_changed into use. v14: - total_affected_planes is no longer needed to check for ddb changes, just as active_pipe_changes. v15: - Fixed stupid mistake with uninitialized crtc in skl_compute_sagv_mask. v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted flag to indicate SAGV readiness for the pipe(Ville Syrjälä) - Added return value to intel_compute_sagv_mask which call intel_atomic_serialize_global_state in order to properly propagate EDEADLCK
[Intel-gfx] [PATCH v20 08/10] drm/i915: Rename bw_state to new_bw_state
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index a8b2038db4d2..d16771dd2b10 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -418,7 +418,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
- struct intel_bw_state *bw_state = NULL;
+ struct intel_bw_state *new_bw_state = NULL;
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
@@ -447,29 +447,29 @@ int intel_bw_atomic_check(struct intel_atomic_state
*state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- bw_state->data_rate[crtc->pipe] = new_data_rate;
- bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+ new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+ new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
drm_dbg_kms(_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
- bw_state->data_rate[crtc->pipe],
- bw_state->num_active_planes[crtc->pipe]);
+ new_bw_state->data_rate[crtc->pipe],
+ new_bw_state->num_active_planes[crtc->pipe]);
}
- if (!bw_state)
+ if (!new_bw_state)
return 0;
- ret = intel_atomic_lock_global_state(_state->base);
+ ret = intel_atomic_lock_global_state(_bw_state->base);
if (ret)
return ret;
- data_rate = intel_bw_data_rate(dev_priv, bw_state);
- num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
--
2.24.1.485.gad05a3d8e5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v20 00/10] SAGV support for Gen12+
For Gen11+ platforms BSpec suggests disabling specific QGV points separately, depending on bandwidth limitations and current display configuration. Thus it required adding a new PCode request for disabling QGV points and some refactoring of already existing SAGV code. Also had to refactor intel_can_enable_sagv function, as current seems to be outdated and using skl specific workarounds, also not following BSpec for Gen11+. v17: Had to rebase the whole series. v19: Added some new patches in between, rebased v20: Added new patches and rebased the series Stanislav Lisovskiy (10): drm/i915: Start passing latency as parameter drm/i915: Eliminate magic numbers "0" and "1" from color plane drm/i915: Introduce skl_plane_wm_level accessor. drm/i915: Add intel_atomic_get_bw_*_state helpers drm/i915: Extract gen specific functions from intel_can_enable_sagv drm/i915: Add proper SAGV support for TGL+ drm/i915: Added required new PCode commands drm/i915: Rename bw_state to new_bw_state drm/i915: Restrict qgv points which don't have enough bandwidth. drm/i915: Enable SAGV support for Gen12 drivers/gpu/drm/i915/display/intel_bw.c | 200 +-- drivers/gpu/drm/i915/display/intel_bw.h | 24 + drivers/gpu/drm/i915/display/intel_display.c | 29 +- .../drm/i915/display/intel_display_types.h| 12 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_pm.c | 555 +++--- drivers/gpu/drm/i915/intel_pm.h | 6 +- drivers/gpu/drm/i915/intel_sideband.c | 2 + 8 files changed, 690 insertions(+), 142 deletions(-) -- 2.24.1.485.gad05a3d8e5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v20 02/10] drm/i915: Eliminate magic numbers "0" and "1" from color plane
According to many computer science sources - magic values
in code _are_ _bad_. For many reasons: the reason is that "0"
or "1" or whatever magic values confuses and doesn't give any
info why this parameter is this value and what it's meaning
is.
I renamed "0" to COLOR_PLANE_Y and "1" to COLOR_PLANE_UV,
because we in fact already use this naming in many other places
and function names, when dealing with color planes.
Signed-off-by: Stanislav Lisovskiy
---
.../drm/i915/display/intel_display_types.h| 5 +++
drivers/gpu/drm/i915/intel_pm.c | 40 +--
2 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 176ab5f1e867..523e0444b373 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -682,6 +682,11 @@ struct skl_plane_wm {
bool is_planar;
};
+enum color_plane {
+ COLOR_PLANE_Y,
+ COLOR_PLANE_UV
+};
+
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b632b6bb9c3e..9e9a4612d842 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4013,7 +4013,7 @@ static int skl_compute_wm_params(const struct
intel_crtc_state *crtc_state,
int width, const struct drm_format_info
*format,
u64 modifier, unsigned int rotation,
u32 plane_pixel_rate, struct skl_wm_params *wp,
-int color_plane);
+enum color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
unsigned int latency,
@@ -4035,7 +4035,7 @@ skl_cursor_allocation(const struct intel_crtc_state
*crtc_state,
drm_format_info(DRM_FORMAT_ARGB),
DRM_FORMAT_MOD_LINEAR,
DRM_MODE_ROTATE_0,
- crtc_state->pixel_rate, , 0);
+ crtc_state->pixel_rate, , COLOR_PLANE_Y);
drm_WARN_ON(_priv->drm, ret);
for (level = 0; level <= max_level; level++) {
@@ -4431,7 +4431,7 @@ static u8 skl_compute_dbuf_slices(const struct
intel_crtc_state *crtc_state,
static u64
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
-int color_plane)
+enum color_plane color_plane)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -4446,7 +4446,7 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *crtc_state,
if (plane->id == PLANE_CURSOR)
return 0;
- if (color_plane == 1 &&
+ if (color_plane == COLOR_PLANE_UV &&
!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
return 0;
@@ -4459,7 +4459,7 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *crtc_state,
height = drm_rect_height(_state->uapi.src) >> 16;
/* UV plane does 1/2 pixel sub-sampling */
- if (color_plane == 1) {
+ if (color_plane == COLOR_PLANE_UV) {
width /= 2;
height /= 2;
}
@@ -4489,12 +4489,12 @@ skl_get_total_relative_data_rate(struct
intel_crtc_state *crtc_state,
u64 rate;
/* packed/y */
- rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
+ rate = skl_plane_relative_data_rate(crtc_state, plane_state,
COLOR_PLANE_Y);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
/* uv-plane */
- rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
+ rate = skl_plane_relative_data_rate(crtc_state, plane_state,
COLOR_PLANE_UV);
uv_plane_data_rate[plane_id] = rate;
total_data_rate += rate;
}
@@ -4516,7 +4516,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state
*crtc_state,
u64 rate;
if (!plane_state->planar_linked_plane) {
- rate = skl_plane_relative_data_rate(crtc_state,
plane_state, 0);
+ rate = skl_plane_relative_data_rate(crtc_state,
plane_state, COLOR_PLANE_Y);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
} else {
@@ -4533,12 +4533,12 @@ icl_get_total_relative_data_rate(struct
intel_crtc_state *crtc_state,
[Intel-gfx] [PATCH v20 09/10] drm/i915: Restrict qgv points which don't have enough bandwidth.
According to BSpec 53998, we should try to restrict qgv points, which can't provide enough bandwidth for desired display configuration. Currently we are just comparing against all of those and take minimum(worst case). v2: Fixed wrong PCode reply mask, removed hardcoded values. v3: Forbid simultaneous legacy SAGV PCode requests and restricting qgv points. Put the actual restriction to commit function, added serialization(thanks to Ville) to prevent commit being applied out of order in case of nonblocking and/or nomodeset commits. v4: - Minor code refactoring, fixed few typos(thanks to James Ausmus) - Change the naming of qgv point masking/unmasking functions(James Ausmus). - Simplify the masking/unmasking operation itself, as we don't need to mask only single point per request(James Ausmus) - Reject and stick to highest bandwidth point if SAGV can't be enabled(BSpec) v5: - Add new mailbox reply codes, which seems to happen during boot time for TGL and indicate that QGV setting is not yet available. v6: - Increase number of supported QGV points to be in sync with BSpec. v7: - Rebased and resolved conflict to fix build failure. - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus) v8: - Don't report an error if we can't restrict qgv points, as SAGV can be disabled by BIOS, which is completely legal. So don't make CI panic. Instead if we detect that there is only 1 QGV point accessible just analyze if we can fit the required bandwidth requirements, but no need in restricting. v9: - Fix wrong QGV transition if we have 0 planes and no SAGV simultaneously. v10: - Fix CDCLK corruption, because of global state getting serialized without modeset, which caused copying of non-calculated cdclk to be copied to dev_priv(thanks to Ville for the hint). v11: - Remove unneeded headers and spaces(Matthew Roper) - Remove unneeded intel_qgv_info qi struct from bw check and zero out the needed one(Matthew Roper) - Changed QGV error message to have more clear meaning(Matthew Roper) - Use state->modeset_set instead of any_ms(Matthew Roper) - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used - Keep using crtc_state->hw.active instead of .enable(Matthew Roper) - Moved unrelated changes to other patch(using latency as parameter for plane wm calculation, moved to SAGV refactoring patch) v12: - Fix rebase conflict with own temporary SAGV/QGV fix. - Remove unnecessary mask being zero check when unmasking qgv points as this is completely legal(Matt Roper) - Check if we are setting the same mask as already being set in hardware to prevent error from PCode. - Fix error message when restricting/unrestricting qgv points to "mask/unmask" which sounds more accurate(Matt Roper) - Move sagv status setting to icl_get_bw_info from atomic check as this should be calculated only once.(Matt Roper) - Edited comments for the case when we can't enable SAGV and use only 1 QGV point with highest bandwidth to be more understandable.(Matt Roper) v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä) - Changed comment for zero new_mask in qgv points masking function to better reflect reality(Ville Syrjälä) - Simplified bit mask operation in qgv points masking function (Ville Syrjälä) - Moved intel_qgv_points_mask closer to gen11 SAGV disabling, however this still can't be under modeset condition(Ville Syrjälä) - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask (Ville Syrjälä) - Extracted PCode changes to separate patch.(Ville Syrjälä) - Now treat num_planes 0 same as 1 to avoid confusion and returning max_bw as 0, which would prevent choosing QGV point having max bandwidth in case if SAGV is not allowed, as per BSpec(Ville Syrjälä) - Do the actual qgv_points_mask swap in the same place as all other global state parts like cdclk are swapped. In the next patch, this all will be moved to bw state as global state, once new global state patch series from Ville lands v14: - Now using global state to serialize access to qgv points - Added global state locking back, otherwise we seem to read bw state in a wrong way. v15: - Added TODO comment for near atomic global state locking in bw code. v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed with Jani Nikula. - Take bw_state_changed flag into use. v17: - Moved qgv point related manipulations next to SAGV code, as those are semantically related(Ville Syrjälä) - Renamed those into intel_sagv_(pre)|(post)_plane_update (Ville Syrjälä) v18: - Move sagv related calls from commit tail into intel_sagv_(pre)|(post)_plane_update(Ville
[Intel-gfx] [PATCH v20 07/10] drm/i915: Added required new PCode commands
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_sideband.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c53fe918be6..1a61db746c7e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8994,6 +8994,7 @@ enum {
#define GEN7_PCODE_ILLEGAL_DATA0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -9015,6 +9016,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)(((point) <<
16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -9027,6 +9029,8 @@ enum {
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_DATA_MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 1447e7516cb7..1e7dd6b6f103 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -370,6 +370,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
--
2.24.1.485.gad05a3d8e5
___
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[Intel-gfx] [PATCH v20 01/10] drm/i915: Start passing latency as parameter
We need to start passing memory latency as a
parameter when calculating plane wm levels,
as latency can get changed in different
circumstances(for example with or without SAGV).
So we need to be more flexible on that matter.
v2: Changed latency type from u32 to unsigned int(Ville Syrjälä)
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8375054ba27d..b632b6bb9c3e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct
intel_crtc_state *crtc_state,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+unsigned int latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */);
@@ -4038,7 +4039,9 @@ skl_cursor_allocation(const struct intel_crtc_state
*crtc_state,
drm_WARN_ON(_priv->drm, ret);
for (level = 0; level <= max_level; level++) {
- skl_compute_plane_wm(crtc_state, level, , , );
+ unsigned int latency = dev_priv->wm.skl_latency[level];
+
+ skl_compute_plane_wm(crtc_state, level, latency, , , );
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -4972,12 +4975,12 @@ static bool skl_wm_has_lines(struct drm_i915_private
*dev_priv, int level)
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
+unsigned int latency,
const struct skl_wm_params *wp,
const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- u32 latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5106,9 +5109,10 @@ skl_compute_wm_levels(const struct intel_crtc_state
*crtc_state,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = [level];
+ unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, wm_params,
-result_prev, result);
+ skl_compute_plane_wm(crtc_state, level, latency,
+wm_params, result_prev, result);
result_prev = result;
}
--
2.24.1.485.gad05a3d8e5
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[Intel-gfx] [PATCH v20 10/10] drm/i915: Enable SAGV support for Gen12
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e4d64b626f8..4c278493559a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct
drm_i915_private *dev_priv)
bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
--
2.24.1.485.gad05a3d8e5
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[Intel-gfx] [PATCH v20 09/10] drm/i915: Restrict qgv points which don't have enough bandwidth.
According to BSpec 53998, we should try to restrict qgv points, which can't provide enough bandwidth for desired display configuration. Currently we are just comparing against all of those and take minimum(worst case). v2: Fixed wrong PCode reply mask, removed hardcoded values. v3: Forbid simultaneous legacy SAGV PCode requests and restricting qgv points. Put the actual restriction to commit function, added serialization(thanks to Ville) to prevent commit being applied out of order in case of nonblocking and/or nomodeset commits. v4: - Minor code refactoring, fixed few typos(thanks to James Ausmus) - Change the naming of qgv point masking/unmasking functions(James Ausmus). - Simplify the masking/unmasking operation itself, as we don't need to mask only single point per request(James Ausmus) - Reject and stick to highest bandwidth point if SAGV can't be enabled(BSpec) v5: - Add new mailbox reply codes, which seems to happen during boot time for TGL and indicate that QGV setting is not yet available. v6: - Increase number of supported QGV points to be in sync with BSpec. v7: - Rebased and resolved conflict to fix build failure. - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus) v8: - Don't report an error if we can't restrict qgv points, as SAGV can be disabled by BIOS, which is completely legal. So don't make CI panic. Instead if we detect that there is only 1 QGV point accessible just analyze if we can fit the required bandwidth requirements, but no need in restricting. v9: - Fix wrong QGV transition if we have 0 planes and no SAGV simultaneously. v10: - Fix CDCLK corruption, because of global state getting serialized without modeset, which caused copying of non-calculated cdclk to be copied to dev_priv(thanks to Ville for the hint). v11: - Remove unneeded headers and spaces(Matthew Roper) - Remove unneeded intel_qgv_info qi struct from bw check and zero out the needed one(Matthew Roper) - Changed QGV error message to have more clear meaning(Matthew Roper) - Use state->modeset_set instead of any_ms(Matthew Roper) - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used - Keep using crtc_state->hw.active instead of .enable(Matthew Roper) - Moved unrelated changes to other patch(using latency as parameter for plane wm calculation, moved to SAGV refactoring patch) v12: - Fix rebase conflict with own temporary SAGV/QGV fix. - Remove unnecessary mask being zero check when unmasking qgv points as this is completely legal(Matt Roper) - Check if we are setting the same mask as already being set in hardware to prevent error from PCode. - Fix error message when restricting/unrestricting qgv points to "mask/unmask" which sounds more accurate(Matt Roper) - Move sagv status setting to icl_get_bw_info from atomic check as this should be calculated only once.(Matt Roper) - Edited comments for the case when we can't enable SAGV and use only 1 QGV point with highest bandwidth to be more understandable.(Matt Roper) v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä) - Changed comment for zero new_mask in qgv points masking function to better reflect reality(Ville Syrjälä) - Simplified bit mask operation in qgv points masking function (Ville Syrjälä) - Moved intel_qgv_points_mask closer to gen11 SAGV disabling, however this still can't be under modeset condition(Ville Syrjälä) - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask (Ville Syrjälä) - Extracted PCode changes to separate patch.(Ville Syrjälä) - Now treat num_planes 0 same as 1 to avoid confusion and returning max_bw as 0, which would prevent choosing QGV point having max bandwidth in case if SAGV is not allowed, as per BSpec(Ville Syrjälä) - Do the actual qgv_points_mask swap in the same place as all other global state parts like cdclk are swapped. In the next patch, this all will be moved to bw state as global state, once new global state patch series from Ville lands v14: - Now using global state to serialize access to qgv points - Added global state locking back, otherwise we seem to read bw state in a wrong way. v15: - Added TODO comment for near atomic global state locking in bw code. v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed with Jani Nikula. - Take bw_state_changed flag into use. v17: - Moved qgv point related manipulations next to SAGV code, as those are semantically related(Ville Syrjälä) - Renamed those into intel_sagv_(pre)|(post)_plane_update (Ville Syrjälä) v18: - Move sagv related calls from commit tail into intel_sagv_(pre)|(post)_plane_update(Ville
[Intel-gfx] [PATCH] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).
Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 71 ++---
1 file changed, 35 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..9e24ff7451a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request
**ports, int count)
memset_p((void **)ports, NULL, count);
}
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
execlists->queue_priority_hint);
record_preemption(execlists);
- /*
-* Don't let the RING_HEAD advance past the breadcrumb
-* as we unwind (and until we resubmit) so that we do
-* not accidentally tell it to go backwards.
-*/
- ring_set_paused(engine, 1);
-
/*
* Note that we have not stopped the GPU at this point,
* so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
last->sched.attr.priority,
execlists->queue_priority_hint);
- ring_set_paused(engine, 1);
defer_active(engine);
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* of timeslices, our queue might be.
*/
start_timeslice(engine);
- return;
+ return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
if (last && !can_merge_rq(last, rq)) {
+ /* leave this for another sibling */
spin_unlock(>base.active.lock);
start_timeslice(engine);
- return; /* leave this for another sibling */
+ return false;
}
ENGINE_TRACE(engine,
@@ -2193,32 +2186,30 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ if (!submit)
+ return false;
- if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
- switch_prio(engine, *execlists->pending);
+ *port = execlists_schedule_in(last, port - execlists->pending);
+ execlists->switch_priority_hint =
+ switch_prio(engine, *execlists->pending);
- /*
-* Skip if we ended up with exactly the same set of requests,
-* e.g. trying to timeslice a pair of ordered contexts
-*/
- if (!memcmp(active, execlists->pending,
- (port - execlists->pending + 1) * sizeof(*port))) {
- do
- execlists_schedule_out(fetch_and_zero(port));
- while (port-- != execlists->pending);
-
- goto skip_submit;
- }
- clear_ports(port + 1, last_port - port);
+ /*
+* Skip if we ended up with exactly the same set of requests,
+* e.g. trying to timeslice a pair of ordered contexts
+*/
+ if (!memcmp(active, execlists->pending,
+ (port - execlists->pending + 1) * sizeof(*port))) {
+ do
+
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf
== Series Details ==
Series: series starting with [01/12] drm/i915/selftests: Add request throughput
measurement to perf
URL : https://patchwork.freedesktop.org/series/75124/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1d8f9dafbff4 drm/i915/selftests: Add request throughput measurement to perf
-:96: WARNING:LINE_SPACING: Missing a blank line after declarations
#96: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1525:
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
-:130: WARNING:LINE_SPACING: Missing a blank line after declarations
#130: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1559:
+ struct i915_request *prev = NULL;
+ IGT_TIMEOUT(end_time);
-:165: WARNING:LINE_SPACING: Missing a blank line after declarations
#165: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1594:
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
-:188: WARNING:LINE_SPACING: Missing a blank line after declarations
#188: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1617:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:196: WARNING:LINE_SPACING: Missing a blank line after declarations
#196: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1625:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:325: WARNING:LINE_SPACING: Missing a blank line after declarations
#325: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1754:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:393: WARNING:LINE_SPACING: Missing a blank line after declarations
#393: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1822:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:462: WARNING:LINE_SPACING: Missing a blank line after declarations
#462: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1891:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:518: WARNING:LINE_SPACING: Missing a blank line after declarations
#518: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1947:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:526: WARNING:LINE_SPACING: Missing a blank line after declarations
#526: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1955:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:571: WARNING:YIELD: Using yield() is generally wrong. See yield() kernel-doc
(sched/core.c)
#571: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:2000:
+ yield(); /* start all threads before we kthread_stop() */
total: 0 errors, 11 warnings, 0 checks, 611 lines checked
b7ab7a745aca drm/i915: Wrap i915_active in a simple kreffed struct
20bb84d17d20 drm/i915/perf: Schedule oa_config after modifying the contexts
c63b2aff058b dma-buf: Prettify typecasts for dma-fence-chain
e25810547705 dma-buf: Report signaled links inside dma-fence-chain
cb7a78a6b34e dma-buf: Exercise dma-fence-chain under selftests
-:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#33:
new file mode 100644
-:61: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#61: FILE: drivers/dma-buf/st-dma-fence-chain.c:24:
+ spinlock_t lock;
-:235: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#235: FILE: drivers/dma-buf/st-dma-fence-chain.c:198:
+ pr_err("Reported %d for find_seqno(0)!\n", err);
-:244: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#244: FILE: drivers/dma-buf/st-dma-fence-chain.c:207:
+ pr_err("Reported %d for find_seqno(%d:%d)!\n",
-:249: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#249: FILE: drivers/dma-buf/st-dma-fence-chain.c:212:
+ pr_err("Incorrect fence reported by
find_seqno(%d:%d)\n",
-:272: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#272: FILE: drivers/dma-buf/st-dma-fence-chain.c:235:
+ pr_err("Error not reported for future fence:
find_seqno(%d:%d)!\n",
-:286: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#286: FILE: drivers/dma-buf/st-dma-fence-chain.c:249:
+ pr_err("Incorrect fence reported by
find_seqno(%d:%d)\n",
-:737: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'dma_fence_chain', this function's name, in a string
#737: FILE: drivers/dma-buf/st-dma-fence-chain.c:700:
+ pr_info("sizeof(dma_fence_chain)=%zu\n",
total: 0 errors, 7 warnings, 1 checks, 725 lines checked
864706ced80d dma-buf: Proxy fence, an unsignaled fence placeholder
Re: [Intel-gfx] [PATCH v2 5/5] drm/i915: Enable scaling filter for plane and CRTC
On Thu, Mar 26, 2020 at 08:45:59PM +0530, Bharadiya,Pankaj wrote:
> On Tue, Mar 24, 2020 at 06:46:10PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 24, 2020 at 03:32:09PM +, Laxminarayan Bharadiya, Pankaj
> > wrote:
> > >
> > >
> > > > -Original Message-
> > > > From: Ville Syrjälä
> > > > Sent: 23 March 2020 20:18
> > > > To: Laxminarayan Bharadiya, Pankaj
> > > >
> > > > Cc: Lattannavar, Sameer ;
> > > > jani.nik...@linux.intel.com; dan...@ffwll.ch;
> > > > intel-gfx@lists.freedesktop.org;
> > > > dri-de...@lists.freedesktop.org; dani...@collabora.com; Joonas Lahtinen
> > > > ; Vivi, Rodrigo
> > > > ;
> > > > David Airlie ; Chris Wilson
> > > > ;
> > > > Maarten Lankhorst ; Souza, Jose
> > > > ; Deak, Imre ; Shankar, Uma
> > > >
> > > > Subject: Re: [PATCH v2 5/5] drm/i915: Enable scaling filter for plane
> > > > and CRTC
> > > >
> > > > On Thu, Mar 19, 2020 at 03:51:03PM +0530, Pankaj Bharadiya wrote:
> > > > > GEN >= 10 hardware supports the programmable scaler filter.
> > > > >
> > > > > Attach scaling filter property for CRTC and plane for GEN >= 10
> > > > > hardwares and program scaler filter based on the selected filter type.
> > > > >
> > > > > changes since v1:
> > > > > * None
> > > > > Changes since RFC:
> > > > > * Enable properties for GEN >= 10 platforms (Ville)
> > > > > * Do not round off the crtc co-ordinate (Danial Stone, Ville)
> > > > > * Add new functions to handle scaling filter setup (Ville)
> > > > > * Remove coefficient set 0 hardcoding.
> > > > >
> > > > > Signed-off-by: Shashank Sharma
> > > > > Signed-off-by: Ankit Nautiyal
> > > > > Signed-off-by: Pankaj Bharadiya
> > > > >
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 32
> > > > > ++-- drivers/gpu/drm/i915/display/intel_sprite.c |
> > > > > 31 ++-
> > > > > 2 files changed, 60 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 791dd908aa89..4b3387ee332e 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -6309,6 +6309,25 @@ void
> > > > skl_scaler_setup_nearest_neighbor_filter(struct drm_i915_private
> > > > *dev_priv,
> > > > > }
> > > > > }
> > > > >
> > > > > +static u32
> > > > > +skl_scaler_crtc_setup_filter(struct drm_i915_private *dev_priv, enum
> > > > > pipe
> > > > pipe,
> > > > > + int id, int set, enum drm_crtc_scaling_filter
> > > > > filter) {
> > > > > + u32 scaler_filter_ctl = PS_FILTER_MEDIUM;
> > > > > +
> > > > > + if (filter == DRM_CRTC_SCALING_FILTER_NEAREST_NEIGHBOR) {
> > > > > + skl_scaler_setup_nearest_neighbor_filter(dev_priv,
> > > > > pipe, id,
> > > > > + set);
> > > > > + scaler_filter_ctl = PS_FILTER_PROGRAMMED |
> > > > > + PS_UV_VERT_FILTER_SELECT(set) |
> > > > > + PS_UV_HORZ_FILTER_SELECT(set) |
> > > > > + PS_Y_VERT_FILTER_SELECT(set) |
> > > > > + PS_Y_HORZ_FILTER_SELECT(set);
> > > > > +
> > > > > + }
> > > > > + return scaler_filter_ctl;
> > > >
> > > > This function does too many things.
> > >
> > > I was thinking to have a common function which configures the filter and
> > > also
> > > provides the register bits (ps_ctrl) to select a desired filter so that
> > > we need
> > > not have extra condition to figure out filter select register bits where
> > > this
> > > function is being called.
> > > How about renaming this function to some better name like
> > > skl_scaler_set_and_get_filter_select() or something else?
> > > Or shall I breakdown this function into multiple functions?
> >
> > I'd just inline the PS_CTRL stuff into the current function.
>
> I am yet to verify this, but would like to get your early comments.
> How about something like this? -
>
> +inline u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int
> set)
> +{
> + u32 filter_select = PS_FILTER_MEDIUM;
Pointless variable.
if (whatever)
return A;
else
return B;
> +
> + if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
> + filter_select = PS_FILTER_PROGRAMMED |
> + PS_UV_VERT_FILTER_SELECT(set) |
> + PS_UV_HORZ_FILTER_SELECT(set) |
> + PS_Y_VERT_FILTER_SELECT(set) |
> + PS_Y_HORZ_FILTER_SELECT(set);
> + }
> +
> + return filter_select;
> +}
> +
> +void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe
> pipe,
> +int id, int set, enum drm_scaling_filter filter)
> +{
> + switch(filter) {
> + case DRM_SCALING_FILTER_DEFAULT:
> + break;
> +
Re: [Intel-gfx] [PATCH] drm/i915/display: Fix mode private_flags comparison at atomic_check
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, March 26, 2020 9:47 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org; Maarten Lankhorst
> ; Kai Vehmanen
> ; Souza; Souza, Jose ;
> Khor, Swee Aun
> Subject: Re: [PATCH] drm/i915/display: Fix mode private_flags comparison at
> atomic_check
>
> On Thu, Mar 26, 2020 at 01:19:28PM +0530, Uma Shankar wrote:
> > This patch fixes the private_flags of mode to be checked and compared
> > against uapi.mode and not from hw.mode. This helps properly trigger
> > modeset at boot if desired by driver.
> >
> > It helps resolve audio_codec initialization issues if display is
> > connected at boot. Initial discussion on this issue has happened on
> > below thread:
> > https://patchwork.freedesktop.org/series/74828/
> >
> > Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1363
> >
> > Cc: Ville Syrjä
> > Cc: Maarten Lankhorst
> > Cc: Kai Vehmanen
> > Cc: Souza, Jose
> > Suggested-by: Ville Syrjä
>
> No one by that name here.
Copied this from an existing reference, not sure how some characters
got messed up ☹
> > Signed-off-by: Uma Shankar
> > Signed-off-by: SweeAun Khor
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index fe55c7c713f1..e630429af2c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device
> > *dev,
> > /* Catch I915_MODE_FLAG_INHERITED */
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > - if (new_crtc_state->hw.mode.private_flags !=
> > - old_crtc_state->hw.mode.private_flags)
> > + if (new_crtc_state->uapi.mode.private_flags !=
> > + old_crtc_state->uapi.mode.private_flags)
> > new_crtc_state->uapi.mode_changed = true;
> > }
> >
> > --
> > 2.22.0
>
> --
> Ville Syrjälä
> Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm:i915:display: add checks for Gen9 devices with hdr capability
== Series Details == Series: drm:i915:display: add checks for Gen9 devices with hdr capability URL : https://patchwork.freedesktop.org/series/75114/ State : failure == Summary == Applying: drm:i915:display: add checks for Gen9 devices with hdr capability error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_hdmi.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm:i915:display: add checks for Gen9 devices with hdr capability When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/perf: Do not clear pollin for small user read buffers
On Wed, Mar 25, 2020 at 06:52:52PM -0700, Dixit, Ashutosh wrote:
On Wed, 25 Mar 2020 17:32:35 -0700, Umesh Nerlige Ramappa wrote:
On Wed, Mar 25, 2020 at 11:20:19AM -0700, Ashutosh Dixit wrote:
> It is wrong to block the user thread in the next poll when OA data is
> already available which could not fit in the user buffer provided in
> the previous read. In several cases the exact user buffer size is not
> known. Blocking user space in poll can lead to data loss when the
> buffer size used is smaller than the available data.
>
> This change fixes this issue and allows user space to read all OA data
> even when using a buffer size smaller than the available data using
> multiple non-blocking reads rather than staying blocked in poll till
> the next timer interrupt.
>
> Cc: Umesh Nerlige Ramappa
> Cc: Lionel Landwerlin
> Signed-off-by: Ashutosh Dixit
> ---
> drivers/gpu/drm/i915/i915_perf.c | 62 ++--
> 1 file changed, 11 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
b/drivers/gpu/drm/i915/i915_perf.c
> index 3222f6cd8255..c1a47c030941 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2957,49 +2957,6 @@ void i915_oa_init_reg_state(const struct intel_context
*ce,
>gen8_update_reg_state_unlocked(ce, stream);
> }
>
> -/**
> - * i915_perf_read_locked - _perf_stream_ops->read with error
normalisation
> - * @stream: An i915 perf stream
> - * @file: An i915 perf stream file
> - * @buf: destination buffer given by userspace
> - * @count: the number of bytes userspace wants to read
> - * @ppos: (inout) file seek position (unused)
> - *
> - * Besides wrapping _perf_stream_ops->read this provides a common place
to
> - * ensure that if we've successfully copied any data then reporting that
takes
> - * precedence over any internal error status, so the data isn't lost.
> - *
> - * For example ret will be -ENOSPC whenever there is more buffered data than
> - * can be copied to userspace, but that's only interesting if we weren't able
> - * to copy some data because it implies the userspace buffer is too small to
> - * receive a single record (and we never split records).
> - *
> - * Another case with ret == -EFAULT is more of a grey area since it would
seem
> - * like bad form for userspace to ask us to overrun its buffer, but the user
> - * knows best:
> - *
> - * http://yarchive.net/comp/linux/partial_reads_writes.html
> - *
> - * Returns: The number of bytes copied or a negative error code on failure.
> - */
> -static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream,
> - struct file *file,
> - char __user *buf,
> - size_t count,
> - loff_t *ppos)
> -{
> - /* Note we keep the offset (aka bytes read) separate from any
> - * error status so that the final check for whether we return
> - * the bytes read with a higher precedence than any error (see
> - * comment below) doesn't need to be handled/duplicated in
> - * stream->ops->read() implementations.
> - */
> - size_t offset = 0;
> - int ret = stream->ops->read(stream, buf, count, );
> -
> - return offset ?: (ret ?: -EAGAIN);
> -}
> -
> /**
> * i915_perf_read - handles read() FOP for i915 perf stream FDs
> * @file: An i915 perf stream file
> @@ -3025,6 +2982,8 @@ static ssize_t i915_perf_read(struct file *file,
> {
>struct i915_perf_stream *stream = file->private_data;
>struct i915_perf *perf = stream->perf;
> + size_t offset = 0;
> + int __ret;
>ssize_t ret;
>
>/* To ensure it's handled consistently we simply treat all reads of a
> @@ -3048,16 +3007,18 @@ static ssize_t i915_perf_read(struct file *file,
>return ret;
>
>mutex_lock(>lock);
> - ret = i915_perf_read_locked(stream, file,
> - buf, count, ppos);
> + __ret = stream->ops->read(stream, buf, count, );
>mutex_unlock(>lock);
>} while (ret == -EAGAIN);
ret will never be EAGAIN here in the while. EAGAIN was returned by the
deleted function in this patch if offset and ret are both 0.
Good catch, I was so focussed on the non-blocking case that I missed the
blocking case.
Although I don't see how that would be true.
As you say above, the old function i915_perf_read_locked() was doing this:
return offset ?: (__ret ?: -EAGAIN);
So -EAGAIN is returned from i915_perf_read_locked() when there is no data
to read but otherwise there is no other error. Since this is blocking read
we cannot return -EAGAIN to user space (since there is no data to read), we
must go back and block again. That is the purpose of the while loop. I
broke this logic in this patch and will need to fix this.
>} else {
>mutex_lock(>lock);
> - ret =
[Intel-gfx] [PATCH v20 06/10] drm/i915: Add proper SAGV support for TGL+
Let's refactor the whole SAGV logic, moving the main calculations from intel_can_enable_sagv to intel_compute_sagv_mask, which also handles this in a unified way calling gen specific functions to evaluate if SAGV is allowed for each crtc. If crtc sagv mask have been changed we serialize access and modify global state. intel_can_enable_sagv now uses bw_state which stores all information related to SAGV and is now a trivial helper. v2: - Rework watermark calculation algorithm to attempt to calculate Level 0 watermark with added sagv block time latency and check if it fits in DBuf in order to determine if SAGV can be enabled already at this stage, just as BSpec 49325 states. if that fails rollback to usual Level 0 latency and disable SAGV. - Remove unneeded tabs(James Ausmus) v3: Rebased the patch v4: - Added back interlaced check for Gen12 and added separate function for TGL SAGV check (thanks to James Ausmus for spotting) - Removed unneeded gen check - Extracted Gen12 SAGV decision making code to a separate function from skl_compute_wm v5: - Added SAGV global state to dev_priv, because we need to track all pipes, not only those in atomic state. Each pipe has now correspondent bit mask reflecting, whether it can tolerate SAGV or not(thanks to Ville Syrjala for suggestions). - Now using active flag instead of enable in crc usage check. v6: - Fixed rebase conflicts v7: - kms_cursor_legacy seems to get broken because of multiple memcpy calls when copying level 0 water marks for enabled SAGV, to fix this now simply using that field right away, without copying, for that introduced a new wm_level accessor which decides which wm_level to return based on SAGV state. v8: - Protect crtc_sagv_mask same way as we do for other global state changes: i.e check if changes are needed, then grab all crtc locks to serialize the changes(Ville Syrjälä) - Add crtc_sagv_mask caching in order to avoid needless recalculations (Matthew Roper) - Put back Gen12 SAGV switch in order to get it enabled in separate patch(Matthew Roper) - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper) - Check if there are no active pipes in intel_can_enable_sagv instead of platform specific functions(Matthew Roper), same for intel_has_sagv check. v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä) - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä) - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask - Extracted skl_plane_wm_level function and passing latency to separate patches(Ville Syrjälä) - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm (Ville Syrjälä) - Now using simple assignment for sagv_wm0 as it contains only pod types and no pointers(Ville Syrjälä) - Fixed intel_can_enable_sagv not to do double duty, now it only check SAGV bits by ANDing those between local and global state. The SAGV masks are now computed after watermarks are available, in order to be able to figure out if ddb ranges are fitting nicely. (Ville Syrjälä) - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic when using skl_plane_wm_level accessor, as we had previously for Gen11+ color plane and regular wm levels, so probably both has to be recalculated with additional SAGV block time for Level 0. v10: - Starting to use new global state for storing pipe_sagv_mask v11: - Fixed rebase conflict with recent drm-tip - Check if we really need to recalculate SAGV mask, otherwise bail out without making any changes. - Use cached SAGV result, instead of recalculating it everytime, if bw_state hasn't changed. v12: - Removed WARN from intel_can_enable_sagv, in some of the commits if we don't recalculated watermarks, bw_state is not recalculated, thus leading to SAGV state not recalculated by the commit state, which is still calling intel_can_enable_sagv function. Fix that by just analyzing the current global bw_state object - because we simply have no other objects related to that. v13: - Rebased, fixed warnings regarding long lines - Changed function call sites from intel_atomic_bw* to intel_wb_* as was suggested.(Jani Nikula) - Taken ddb_state_changed and bw_state_changed into use. v14: - total_affected_planes is no longer needed to check for ddb changes, just as active_pipe_changes. v15: - Fixed stupid mistake with uninitialized crtc in skl_compute_sagv_mask. v16: - Convert pipe_sagv_mask to pipe_sagv_reject and now using inverted flag to indicate SAGV readiness for the pipe(Ville Syrjälä) - Added return value to intel_compute_sagv_mask which call intel_atomic_serialize_global_state in order to properly propagate EDEADLCK
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning (rev2)
== Series Details == Series: drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning (rev2) URL : https://patchwork.freedesktop.org/series/75078/ State : warning == Summary == $ dim checkpatch origin/drm-tip 39b95b621dfc drm/i915: Differentiate between aliasing-ppgtt and ggtt pinning -:41: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 0 warnings, 0 checks, 17 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/21] Revert "drm/i915/gem: Drop relocation slowpath"
== Series Details ==
Series: series starting with [01/21] Revert "drm/i915/gem: Drop relocation
slowpath"
URL : https://patchwork.freedesktop.org/series/75115/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d083289b34df Revert "drm/i915/gem: Drop relocation slowpath"
-:78: WARNING:LINE_SPACING: Missing a blank line after declarations
#78: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1579:
+ int err = __get_user(c, addr);
+ if (err)
total: 0 errors, 1 warnings, 0 checks, 257 lines checked
936cc0098d93 drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2.
-:506: WARNING:LONG_LINE: line over 100 characters
#506: FILE: drivers/gpu/drm/i915/i915_gem.c:1338:
+ while ((obj = list_first_entry_or_null(>obj_list, struct
drm_i915_gem_object, obj_link))) {
total: 0 errors, 1 warnings, 0 checks, 481 lines checked
74e05c05e4b8 drm/i915: Remove locking from i915_gem_object_prepare_read/write
41b0db48a24c drm/i915: Parse command buffer earlier in eb_relocate(slow)
4f72eac68d80 drm/i915: Use per object locking in execbuf, v6.
bfe136b956c4 drm/i915: Use ww locking in intel_renderstate.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
Convert to using ww-waiting, and make sure we always pin intel_context_state,
total: 0 errors, 1 warnings, 0 checks, 202 lines checked
0200da0a1df9 drm/i915: Add ww context handling to context_barrier_task
-:19: WARNING:LONG_LINE: line over 100 characters
#19: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:1100:
+ int (*pin)(struct intel_context *ce, struct
i915_gem_ww_ctx *ww, void *data),
total: 0 errors, 1 warnings, 0 checks, 146 lines checked
6d83bbf7ff96 drm/i915: Nuke arguments to eb_pin_engine
757c8e3383b2 drm/i915: Pin engine before pinning all objects, v3.
9f9b3ccbfee0 drm/i915: Rework intel_context pinning to do everything outside of
pin_mutex
-:125: CHECK:LINE_SPACING: Please don't use multiple blank lines
#125: FILE: drivers/gpu/drm/i915/gt/intel_context.c:176:
+
+
-:340: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#340: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:3045:
+ *vaddr = i915_gem_object_pin_map(ce->state->obj,
+
i915_coherent_map_type(ce->engine->i915) |
total: 0 errors, 0 warnings, 2 checks, 445 lines checked
cfef16270648 drm/i915: Make sure execbuffer always passes ww state to
i915_vma_pin.
-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:573:
+ err = i915_vma_pin_ww(vma, >ww,
entry->pad_to_size, entry->alignment,
-:188: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#188: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2197:
+* hsw should have this fixed, but bdw mucks it up again. */
total: 0 errors, 1 warnings, 1 checks, 812 lines checked
85863b6646f5 drm/i915: Convert i915_gem_object/client_blt.c to use ww locking
as well, v2.
cb74e29ea87a drm/i915: Kill last user of intel_context_create_request outside
of selftests
f90980b43cf5 drm/i915: Convert i915_perf to ww locking as well
26070db64fbd drm/i915: Dirty hack to fix selftests locking inversion
b03c1aeda1ed drm/i915/selftests: Fix locking inversion in lrc selftest.
75eb93acc311 drm/i915: Use ww pinning for intel_context_create_request()
5f66150eaf57 drm/i915: Move i915_vma_lock in the selftests to avoid lock
inversion, v2.
e91160d4fd13 drm/i915: Add ww locking to vm_fault_gtt
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 91 lines checked
1e09059f0103 drm/i915: Add ww locking to pin_to_display_plane
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 129 lines checked
1551e4c71efc drm/i915: Ensure we hold the pin mutex
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 37 lines checked
___
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[Intel-gfx] [PATCH v3 6/6] drm/i915/uc: do not free err log on uc_fini
We need to keep the GuC error logs around to debug the load failure,
so we can't clean them in the error unwind, which includes uc_fini().
Moving the cleanup to driver remove ensures that the logs stick around
long enough for us to dump them.
v2: reword commit msg (John)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_gt.c| 3 +--
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 +++--
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 1 +
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index d09f7596cb98..1c99cc72305a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -635,8 +635,7 @@ void intel_gt_driver_remove(struct intel_gt *gt)
{
__intel_gt_disable(gt);
- intel_uc_fini_hw(>uc);
- intel_uc_fini(>uc);
+ intel_uc_driver_remove(>uc);
intel_engines_release(gt);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index a4cbe06e06bd..b11e564ef22e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -131,6 +131,13 @@ static void __uc_free_load_err_log(struct intel_uc *uc)
i915_gem_object_put(log);
}
+void intel_uc_driver_remove(struct intel_uc *uc)
+{
+ intel_uc_fini_hw(uc);
+ intel_uc_fini(uc);
+ __uc_free_load_err_log(uc);
+}
+
static inline bool guc_communication_enabled(struct intel_guc *guc)
{
return intel_guc_ct_enabled(>ct);
@@ -311,8 +318,6 @@ static void __uc_fini(struct intel_uc *uc)
{
intel_huc_fini(>huc);
intel_guc_fini(>guc);
-
- __uc_free_load_err_log(uc);
}
static int __uc_sanitize(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 5ae7b50b7dc1..9c954c589edf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -34,6 +34,7 @@ struct intel_uc {
void intel_uc_init_early(struct intel_uc *uc);
void intel_uc_driver_late_release(struct intel_uc *uc);
+void intel_uc_driver_remove(struct intel_uc *uc);
void intel_uc_init_mmio(struct intel_uc *uc);
void intel_uc_reset_prepare(struct intel_uc *uc);
void intel_uc_suspend(struct intel_uc *uc);
--
2.24.1
___
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[Intel-gfx] [PATCH v3 1/6] drm/i915/gt: allow setting generic data pointer
From: Andi Shyti
When registering debugfs files the intel gt debugfs library
forces a 'struct *gt' private data on the caller.
To be open to different usages make the new
"intel_gt_debugfs_register_files()"[*] function more generic by
converting the 'struct *gt' pointer to a 'void *' type.
I take the chance to rename the functions by using "intel_gt_" as
prefix instead of "debugfs_", so that "debugfs_gt_register_files()"
becomes "intel_gt_debugfs_register_files()".
Signed-off-by: Andi Shyti
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/debugfs_engines.c | 2 +-
drivers/gpu/drm/i915/gt/debugfs_gt.c | 11 +--
drivers/gpu/drm/i915/gt/debugfs_gt.h | 9 -
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 14 +-
4 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.c
b/drivers/gpu/drm/i915/gt/debugfs_engines.c
index 6a5e9ab20b94..5e3725e62241 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_engines.c
@@ -32,5 +32,5 @@ void debugfs_engines_register(struct intel_gt *gt, struct
dentry *root)
{ "engines", _fops },
};
- debugfs_gt_register_files(gt, root, files, ARRAY_SIZE(files));
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
}
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index 75255aaacaed..de73b63d6ba7 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -26,15 +26,14 @@ void debugfs_gt_register(struct intel_gt *gt)
debugfs_gt_pm_register(gt, root);
}
-void debugfs_gt_register_files(struct intel_gt *gt,
- struct dentry *root,
- const struct debugfs_gt_file *files,
- unsigned long count)
+void intel_gt_debugfs_register_files(struct dentry *root,
+const struct debugfs_gt_file *files,
+unsigned long count, void *data)
{
while (count--) {
- if (!files->eval || files->eval(gt))
+ if (!files->eval || files->eval(data))
debugfs_create_file(files->name,
- 0444, root, gt,
+ 0444, root, data,
files->fops);
files++;
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.h
b/drivers/gpu/drm/i915/gt/debugfs_gt.h
index 4ea0f06cda8f..f77540f727e9 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.h
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.h
@@ -28,12 +28,11 @@ void debugfs_gt_register(struct intel_gt *gt);
struct debugfs_gt_file {
const char *name;
const struct file_operations *fops;
- bool (*eval)(const struct intel_gt *gt);
+ bool (*eval)(void *data);
};
-void debugfs_gt_register_files(struct intel_gt *gt,
- struct dentry *root,
- const struct debugfs_gt_file *files,
- unsigned long count);
+void intel_gt_debugfs_register_files(struct dentry *root,
+const struct debugfs_gt_file *files,
+unsigned long count, void *data);
#endif /* DEBUGFS_GT_H */
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 059c9e5c002e..dc024944873a 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -506,9 +506,11 @@ static int llc_show(struct seq_file *m, void *data)
return 0;
}
-static bool llc_eval(const struct intel_gt *gt)
+static bool llc_eval(void *data)
{
- return HAS_LLC(gt->i915);
+ struct intel_gt *gt = data;
+
+ return gt && HAS_LLC(gt->i915);
}
DEFINE_GT_DEBUGFS_ATTRIBUTE(llc);
@@ -580,9 +582,11 @@ static int rps_boost_show(struct seq_file *m, void *data)
return 0;
}
-static bool rps_eval(const struct intel_gt *gt)
+static bool rps_eval(void *data)
{
- return HAS_RPS(gt->i915);
+ struct intel_gt *gt = data;
+
+ return gt && HAS_RPS(gt->i915);
}
DEFINE_GT_DEBUGFS_ATTRIBUTE(rps_boost);
@@ -597,5 +601,5 @@ void debugfs_gt_pm_register(struct intel_gt *gt, struct
dentry *root)
{ "rps_boost", _boost_fops, rps_eval },
};
- debugfs_gt_register_files(gt, root, files, ARRAY_SIZE(files));
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
}
--
2.24.1
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[Intel-gfx] [PATCH v3 4/6] drm/i915/debugfs: move uC printers and update debugfs file names
Move the printers to the respective files for clarity. The
guc_load_status debugfs has been squashed in the guc_info one, has
having separate ones wasn't very useful. The HuC debugfs has been
renamed huc_info to match.
v2: keep printing HUC_STATUS2 (Tony), avoid const->non-const
container_of (Jani)
Suggested-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
Cc: Tony Ye
Cc: Jani Nikula
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 44 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 92 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 4 +
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 29 +
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 2 +
drivers/gpu/drm/i915/i915_debugfs.c| 131 +++--
7 files changed, 189 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 827d75073879..861657897c0f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -723,3 +723,47 @@ int intel_guc_allocate_and_map_vma(struct intel_guc *guc,
u32 size,
return 0;
}
+
+/**
+ * intel_guc_load_status - dump information about GuC load status
+ * @guc: the GuC
+ * @p: the _printer
+ *
+ * Pretty printer for GuC load status.
+ */
+void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct intel_uncore *uncore = gt->uncore;
+ intel_wakeref_t wakeref;
+
+ if (!intel_guc_is_supported(guc)) {
+ drm_printf(p, "GuC not supported\n");
+ return;
+ }
+
+ if (!intel_guc_is_wanted(guc)) {
+ drm_printf(p, "GuC disabled\n");
+ return;
+ }
+
+ intel_uc_fw_dump(>fw, p);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref) {
+ u32 status = intel_uncore_read(uncore, GUC_STATUS);
+ u32 i;
+
+ drm_printf(p, "\nGuC status 0x%08x:\n", status);
+ drm_printf(p, "\tBootrom status = 0x%x\n",
+ (status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
+ drm_printf(p, "\tuKernel status = 0x%x\n",
+ (status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
+ drm_printf(p, "\tMIA Core status = 0x%x\n",
+ (status & GS_MIA_MASK) >> GS_MIA_SHIFT);
+ drm_puts(p, "\nScratch registers:\n");
+ for (i = 0; i < 16; i++) {
+ drm_printf(p, "\t%2d: \t0x%x\n",
+ i, intel_uncore_read(uncore,
SOFT_SCRATCH(i)));
+ }
+ }
+}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 4594ccbeaa34..a5d7a86be4cf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -190,4 +190,6 @@ static inline void intel_guc_disable_msg(struct intel_guc
*guc, u32 mask)
int intel_guc_reset_engine(struct intel_guc *guc,
struct intel_engine_cs *engine);
+void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
+
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index caed0d57e704..8cdd6dc3df58 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -672,3 +672,95 @@ void intel_guc_log_handle_flush_event(struct intel_guc_log
*log)
{
queue_work(system_highpri_wq, >relay.flush_work);
}
+
+static const char *
+stringify_guc_log_type(enum guc_log_buffer_type type)
+{
+ switch (type) {
+ case GUC_ISR_LOG_BUFFER:
+ return "ISR";
+ case GUC_DPC_LOG_BUFFER:
+ return "DPC";
+ case GUC_CRASH_DUMP_LOG_BUFFER:
+ return "CRASH";
+ default:
+ MISSING_CASE(type);
+ }
+
+ return "";
+}
+
+/**
+ * intel_guc_log_info - dump information about GuC log relay
+ * @guc: the GuC
+ * @p: the _printer
+ *
+ * Pretty printer for GuC log info
+ */
+void intel_guc_log_info(struct intel_guc_log *log, struct drm_printer *p)
+{
+ enum guc_log_buffer_type type;
+
+ if (!intel_guc_log_relay_created(log)) {
+ drm_puts(p, "GuC log relay not created\n");
+ return;
+ }
+
+ drm_puts(p, "GuC logging stats:\n");
+
+ drm_printf(p, "\tRelay full count: %u\n", log->relay.full_count);
+
+ for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
+ drm_printf(p, "\t%s:\tflush count %10u, overflow count %10u\n",
+ stringify_guc_log_type(type),
+ log->stats[type].flush,
+
[Intel-gfx] [PATCH v20 04/10] drm/i915: Add intel_atomic_get_bw_*_state helpers
Add correspondent helpers to be able to get old/new bandwidth
global state object.
v2: - Fixed typo in function call
v3: - Changed new functions naming to use convention proposed
by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
v4: - Change function naming back to intel_atomic* pattern,
was decided to rename in a separate patch series.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 29 -
drivers/gpu/drm/i915/display/intel_bw.h | 9
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 58b264bc318d..a8b2038db4d2 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -374,7 +374,34 @@ static unsigned int intel_bw_data_rate(struct
drm_i915_private *dev_priv,
return data_rate;
}
-static struct intel_bw_state *
+struct intel_bw_state *
+intel_atomic_get_bw_old_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_old_global_obj_state(state,
_priv->bw_obj);
+ if (IS_ERR(bw_state))
+ return ERR_CAST(bw_state);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
+intel_atomic_get_bw_new_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *bw_state;
+
+ bw_state = intel_atomic_get_new_global_obj_state(state,
_priv->bw_obj);
+
+ if (IS_ERR(bw_state))
+ return ERR_CAST(bw_state);
+
+ return to_intel_bw_state(bw_state);
+}
+
+struct intel_bw_state *
intel_atomic_get_bw_state(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
b/drivers/gpu/drm/i915/display/intel_bw.h
index a8aa7624c5aa..fe6579c952f5 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,15 @@ struct intel_bw_state {
#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
+struct intel_bw_state *
+intel_atomic_get_bw_old_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_bw_new_state(struct intel_atomic_state *state);
+
+struct intel_bw_state *
+intel_atomic_get_bw_state(struct intel_atomic_state *state);
+
void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
--
2.24.1.485.gad05a3d8e5
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[Intel-gfx] [PATCH v20 05/10] drm/i915: Extract gen specific functions from intel_can_enable_sagv
Addressing one of the comments, recommending to extract platform
specific code from intel_can_enable_sagv as a preparation, before
we are going to add support for tgl+.
Current code in intel_can_enable_sagv is valid only for skl,
so this patch adds also proper support for icl, subsequent
patches will add support for tgl+, combined with other required
changes.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 89 ++---
1 file changed, 61 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f8d62d1977ac..64193b098175 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3757,41 +3757,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static bool icl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = state->base.dev;
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
struct intel_plane *plane;
- struct intel_crtc_state *crtc_state;
- enum pipe pipe;
+ struct intel_plane_state *plane_state;
int level, latency;
- if (!intel_has_sagv(dev_priv))
- return false;
+ crtc = to_intel_crtc(crtc_state->uapi.crtc);
- /*
-* If there are no active CRTCs, no additional checks need be performed
-*/
- if (hweight8(state->active_pipes) == 0)
- return true;
-
- /*
-* SKL+ workaround: bspec recommends we disable SAGV when we have
-* more then one pipe enabled
-*/
- if (hweight8(state->active_pipes) > 1)
- return false;
-
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
-
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
+ pipe_name(crtc->pipe));
return false;
+ }
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
crtc_state) {
struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane->id];
@@ -3807,7 +3790,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
latency = dev_priv->wm.skl_latency[level];
if (skl_needs_memory_bw_wa(dev_priv) &&
- plane->base.state->fb->modifier ==
+ plane_state->uapi.fb->modifier ==
I915_FORMAT_MOD_X_TILED)
latency += 15;
@@ -3816,8 +3799,58 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
* incur memory latencies higher than sagv_block_time_us we
* can't enable SAGV.
*/
- if (latency < dev_priv->sagv_block_time_us)
+ if (latency < dev_priv->sagv_block_time_us) {
+ DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV
for pipe %c\n",
+ latency, dev_priv->sagv_block_time_us,
pipe_name(crtc->pipe));
return false;
+ }
+ }
+
+ return true;
+}
+
+static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
+{
+ struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->uapi.state);
+
+ /*
+* It has been recommended that for Gen 9 we switch SAGV off when
+* multiple pipes are used.
+*/
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ /*
+* Besides active pipe limitation, rest of checks pretty much match ICL
+* so no need to duplicate code
+*/
+ return icl_can_enable_sagv_on_pipe(crtc_state);
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
+ /*
+* If there are no active CRTCs, no additional checks need be performed
+*/
+ if (hweight8(state->active_pipes) == 0)
+ return true;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ if (INTEL_GEN(dev_priv) <= 9) {
+ if
[Intel-gfx] [PATCH v20 03/10] drm/i915: Introduce skl_plane_wm_level accessor.
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.
v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
(Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
skl_plane_wm_level
v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
- Changed colorplane id type from boolean to int as index
(Ville Syrjälä)
- Moved crtc_state param so that it is first now
(Ville Syrjälä)
- Moved wm_level declaration to tigher scope in
skl_write_plane_wm(Ville Syrjälä)
v4: - Started to use enum values for color plane
- Do sizeof for a type what we are memset'ing
- Zero out wm_uv as well(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 85 ++---
1 file changed, 67 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9e9a4612d842..f8d62d1977ac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4547,6 +4547,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state
*crtc_state,
return total_data_rate;
}
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
+ int level,
+ enum color_plane color_plane)
+{
+ const struct skl_plane_wm *wm =
+ _state->wm.skl.optimal.planes[plane_id];
+
+ return color_plane == COLOR_PLANE_Y ? >wm[level] :
>uv_wm[level];
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -4606,22 +4618,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
*crtc_state)
*/
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
+
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- _state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, COLOR_PLANE_Y);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+level, COLOR_PLANE_UV);
if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc >
total[PLANE_CURSOR]) {
+ if (wm_level->min_ddb_alloc >
total[PLANE_CURSOR]) {
drm_WARN_ON(_priv->drm,
- wm->wm[level].min_ddb_alloc
!= U16_MAX);
+ wm_level->min_ddb_alloc !=
U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
- blocks += wm->wm[level].min_ddb_alloc;
- blocks += wm->uv_wm[level].min_ddb_alloc;
+ blocks += wm_level->min_ddb_alloc;
+ blocks += wm_uv_level->min_ddb_alloc;
}
if (blocks <= alloc_size) {
@@ -4644,11 +4662,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
*crtc_state)
* proportional to its relative data rate.
*/
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- _state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, COLOR_PLANE_Y);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+level, COLOR_PLANE_UV);
+
if (plane_id == PLANE_CURSOR)
continue;
@@ -4663,7 +4686,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+
Re: [Intel-gfx] [PATCH] drm/i915/display: Fix mode private_flags comparison at atomic_check
On Thu, Mar 26, 2020 at 01:19:28PM +0530, Uma Shankar wrote:
> This patch fixes the private_flags of mode to be checked and
> compared against uapi.mode and not from hw.mode. This helps
> properly trigger modeset at boot if desired by driver.
>
> It helps resolve audio_codec initialization issues if display
> is connected at boot. Initial discussion on this issue has happened
> on below thread:
> https://patchwork.freedesktop.org/series/74828/
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1363
>
> Cc: Ville Syrjä
> Cc: Maarten Lankhorst
> Cc: Kai Vehmanen
> Cc: Souza, Jose
> Suggested-by: Ville Syrjä
No one by that name here.
> Signed-off-by: Uma Shankar
> Signed-off-by: SweeAun Khor
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index fe55c7c713f1..e630429af2c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device *dev,
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - if (new_crtc_state->hw.mode.private_flags !=
> - old_crtc_state->hw.mode.private_flags)
> + if (new_crtc_state->uapi.mode.private_flags !=
> + old_crtc_state->uapi.mode.private_flags)
> new_crtc_state->uapi.mode_changed = true;
> }
>
> --
> 2.22.0
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH] drm/i915/selftests: Check timeout before flush and cond checks
Allow a bit of leniency for the CPU scheduler to be distracted while we
flush the tasklet and so ensure that we always check the status of the
request once more before timing out.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 6f06ba750a0a..b8c8355b1095 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -74,20 +74,19 @@ static int wait_for_submit(struct intel_engine_cs *engine,
{
timeout += jiffies;
do {
- cond_resched();
- intel_engine_flush_submission(engine);
+ bool done = time_after(jiffies, timeout);
- if (READ_ONCE(engine->execlists.pending[0]))
- continue;
+ intel_engine_flush_submission(engine);
if (i915_request_is_active(rq))
return 0;
if (i915_request_started(rq)) /* that was quick! */
return 0;
- } while (time_before(jiffies, timeout));
- return -ETIME;
+ if (done)
+ return -ETIME;
+ } while (1);
}
static int wait_for_reset(struct intel_engine_cs *engine,
--
2.20.1
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[Intel-gfx] [PATCH v3 2/6] drm/i915/guc: drop stage_pool debugfs
The pool will be private to GuC in the new submission scheme, so we
won't be able to print it and we can just drop the current legacy code.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_debugfs.c | 53 -
1 file changed, 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 25bf997e2dd1..ef875cec3524 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1356,58 +1356,6 @@ static int i915_guc_info(struct seq_file *m, void *data)
return 0;
}
-static int i915_guc_stage_pool(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_uc *uc = _priv->gt.uc;
- struct guc_stage_desc *desc = uc->guc.stage_desc_pool_vaddr;
- int index;
-
- if (!intel_uc_uses_guc_submission(uc))
- return -ENODEV;
-
- for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
- struct intel_engine_cs *engine;
-
- if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
- continue;
-
- seq_printf(m, "GuC stage descriptor %u:\n", index);
- seq_printf(m, "\tIndex: %u\n", desc->stage_id);
- seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
- seq_printf(m, "\tPriority: %d\n", desc->priority);
- seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
- seq_printf(m, "\tEngines used: 0x%x\n",
- desc->engines_used);
- seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK:
0x%x\n",
- desc->db_trigger_phy,
- desc->db_trigger_cpu,
- desc->db_trigger_uk);
- seq_printf(m, "\tProcess descriptor: 0x%x\n",
- desc->process_desc);
- seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
- desc->wq_addr, desc->wq_size);
- seq_putc(m, '\n');
-
- for_each_uabi_engine(engine, dev_priv) {
- u32 guc_engine_id = engine->guc_id;
- struct guc_execlist_context *lrc =
- >lrc[guc_engine_id];
-
- seq_printf(m, "\t%s LRC:\n", engine->name);
- seq_printf(m, "\t\tContext desc: 0x%x\n",
- lrc->context_desc);
- seq_printf(m, "\t\tContext id: 0x%x\n",
lrc->context_id);
- seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
- seq_printf(m, "\t\tRing begin: 0x%x\n",
lrc->ring_begin);
- seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
- seq_putc(m, '\n');
- }
- }
-
- return 0;
-}
-
static int i915_guc_log_dump(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
@@ -2143,7 +2091,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
- {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
{"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_ring_freq_table", i915_ring_freq_table, 0},
--
2.24.1
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[Intel-gfx] [PATCH v3 3/6] drm/i915/huc: make "support huc" reflect HW capabilities
We currently initialize HuC support based on GuC being enabled in
modparam; this means that huc_is_supported() can return false on HW that
does have a HuC when enable_guc=0. The rationale for this behavior is
that HuC requires GuC for authentication and therefore is not supported
by itself. However, we do not allow defining HuC fw wthout GuC fw and
selecting HuC in modparam implicitly selects GuC as well, so we can't
actually hit a scenario where HuC is selected alone. Therefore, we can
flip the support check to reflect the HW capabilities and fw
availability, which is more intuitive and will make it cleaner to log
HuC the difference between not supported in HW and not selected.
Removing the difference between GuC and HuC also allows us to simplify
the init_early, since we don't need to differentiate the support based
on the type of uC.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
Reviewed-by: Andi Shyti
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 14 -
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h | 1 -
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 17 ---
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 -
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 25 +++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 3 +--
8 files changed, 20 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 819f09ef51fc..827d75073879 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -169,7 +169,7 @@ void intel_guc_init_early(struct intel_guc *guc)
{
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
- intel_guc_fw_init_early(guc);
+ intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_GUC);
intel_guc_ct_init_early(>ct);
intel_guc_log_init_early(>log);
intel_guc_submission_init_early(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 3a1c47d600ea..d4a87f4c9421 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -13,20 +13,6 @@
#include "intel_guc_fw.h"
#include "i915_drv.h"
-/**
- * intel_guc_fw_init_early() - initializes GuC firmware struct
- * @guc: intel_guc struct
- *
- * On platforms with GuC selects firmware for uploading
- */
-void intel_guc_fw_init_early(struct intel_guc *guc)
-{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
- intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_GUC, HAS_GT_UC(i915),
- INTEL_INFO(i915)->platform, INTEL_REVID(i915));
-}
-
static void guc_prepare_xfer(struct intel_uncore *uncore)
{
u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
index b5ab639d7259..0b4d2a9c9435 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
@@ -8,7 +8,6 @@
struct intel_guc;
-void intel_guc_fw_init_early(struct intel_guc *guc);
int intel_guc_fw_upload(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index a74b65694512..d73dc21686e7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -41,7 +41,7 @@ void intel_huc_init_early(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
- intel_huc_fw_init_early(huc);
+ intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_HUC);
if (INTEL_GEN(i915) >= 11) {
huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 9cdf4cbe691c..e5ef509c70e8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -7,23 +7,6 @@
#include "intel_huc_fw.h"
#include "i915_drv.h"
-/**
- * intel_huc_fw_init_early() - initializes HuC firmware struct
- * @huc: intel_huc struct
- *
- * On platforms with HuC selects firmware for uploading
- */
-void intel_huc_fw_init_early(struct intel_huc *huc)
-{
- struct intel_gt *gt = huc_to_gt(huc);
- struct intel_uc *uc = >uc;
- struct drm_i915_private *i915 = gt->i915;
-
- intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_HUC,
- intel_uc_wants_guc(uc),
- INTEL_INFO(i915)->platform, INTEL_REVID(i915));
-}
-
/**
* intel_huc_fw_upload() - load HuC uCode to device
* @huc: intel_huc structure
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
index b791269ce923..12f264ee3e0b 100644
---
[Intel-gfx] [PATCH v3 5/6] drm/i915/uc: Move uC debugfs to its own folder under GT
uC is a component of the GT, so it makes sense for the uC debugfs files
to be in the GT folder. A subfolder has been used to keep the same
structure we have for the code.
v2: use intel_* prefix (Jani), rebase on new gt_debugfs_register_files,
fix permissions for writable debugfs files.
v3: Rename files (Michal), remove blank line (Jani), fix sparse warns.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Andi Shyti
Cc: Michal Wajdeczko
Cc: John Harrison
Cc: Matthew Brost
Cc: Tony Ye
Cc: Jani Nikula
Reviewed-by: Andi Shyti #v2
---
drivers/gpu/drm/i915/Makefile | 4 +
drivers/gpu/drm/i915/gt/debugfs_gt.c | 6 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 5 +
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 42 ++
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.h| 14 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 5 -
.../drm/i915/gt/uc/intel_guc_log_debugfs.c| 124
.../drm/i915/gt/uc/intel_guc_log_debugfs.h| 15 ++
.../gpu/drm/i915/gt/uc/intel_huc_debugfs.c| 36 +
.../gpu/drm/i915/gt/uc/intel_huc_debugfs.h| 14 ++
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 30
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h | 14 ++
drivers/gpu/drm/i915/i915_debugfs.c | 137 --
13 files changed, 303 insertions(+), 143 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 99cd3d25f816..2fce8b0040f3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -167,14 +167,18 @@ i915-y += \
# general-purpose microcontroller (GuC) support
i915-y += gt/uc/intel_uc.o \
+ gt/uc/intel_uc_debugfs.o \
gt/uc/intel_uc_fw.o \
gt/uc/intel_guc.o \
gt/uc/intel_guc_ads.o \
gt/uc/intel_guc_ct.o \
+ gt/uc/intel_guc_debugfs.o \
gt/uc/intel_guc_fw.o \
gt/uc/intel_guc_log.o \
+ gt/uc/intel_guc_log_debugfs.o \
gt/uc/intel_guc_submission.o \
gt/uc/intel_huc.o \
+ gt/uc/intel_huc_debugfs.o \
gt/uc/intel_huc_fw.o
# modesetting core code
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index de73b63d6ba7..1de5fbaa1cf9 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -9,6 +9,7 @@
#include "debugfs_engines.h"
#include "debugfs_gt.h"
#include "debugfs_gt_pm.h"
+#include "uc/intel_uc_debugfs.h"
#include "i915_drv.h"
void debugfs_gt_register(struct intel_gt *gt)
@@ -24,6 +25,8 @@ void debugfs_gt_register(struct intel_gt *gt)
debugfs_engines_register(gt, root);
debugfs_gt_pm_register(gt, root);
+
+ intel_uc_debugfs_register(>uc, root);
}
void intel_gt_debugfs_register_files(struct dentry *root,
@@ -31,9 +34,10 @@ void intel_gt_debugfs_register_files(struct dentry *root,
unsigned long count, void *data)
{
while (count--) {
+ umode_t mode = files->fops->write ? 0644 : 0444;
if (!files->eval || files->eval(data))
debugfs_create_file(files->name,
- 0444, root, data,
+ mode, root, data,
files->fops);
files++;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index a5d7a86be4cf..e84ab67b317d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -74,6 +74,11 @@ struct intel_guc {
struct mutex send_mutex;
};
+static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
+{
+ return container_of(log, struct intel_guc, log);
+}
+
static
inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
new file mode 100644
index ..fe7cb7b29a1e
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include
+
+#include "gt/debugfs_gt.h"
+#include "intel_guc.h"
+#include "intel_guc_debugfs.h"
+#include "intel_guc_log_debugfs.h"
+
+static int guc_info_show(struct seq_file *m, void *data)
+{
+
[Intel-gfx] [PATCH v3 0/6] Re-org uC debugfs files and move them under GT
Minor changes applied to patch 5, which is the only one missing a review. As multiple people have noted, intel_gt_debugfs_register_files is now generic enough to be pulled out of gt/. Andi has patches for that and will follow up after this series is merged. Cc: Andi Shyti Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost Andi Shyti (1): drm/i915/gt: allow setting generic data pointer Daniele Ceraolo Spurio (5): drm/i915/guc: drop stage_pool debugfs drm/i915/huc: make "support huc" reflect HW capabilities drm/i915/debugfs: move uC printers and update debugfs file names drm/i915/uc: Move uC debugfs to its own folder under GT drm/i915/uc: do not free err log on uc_fini drivers/gpu/drm/i915/Makefile | 4 + drivers/gpu/drm/i915/gt/debugfs_engines.c | 2 +- drivers/gpu/drm/i915/gt/debugfs_gt.c | 15 +- drivers/gpu/drm/i915/gt/debugfs_gt.h | 9 +- drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 14 +- drivers/gpu/drm/i915/gt/intel_gt.c| 3 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 46 ++- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 7 + .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 42 +++ .../gpu/drm/i915/gt/uc/intel_guc_debugfs.h| 14 + drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 14 - drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h | 1 - drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 97 +- drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 4 + .../drm/i915/gt/uc/intel_guc_log_debugfs.c| 124 .../drm/i915/gt/uc/intel_guc_log_debugfs.h| 15 + drivers/gpu/drm/i915/gt/uc/intel_huc.c| 31 +- drivers/gpu/drm/i915/gt/uc/intel_huc.h| 2 + .../gpu/drm/i915/gt/uc/intel_huc_debugfs.c| 36 +++ .../gpu/drm/i915/gt/uc/intel_huc_debugfs.h| 14 + drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 17 -- drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 - drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 +- drivers/gpu/drm/i915/gt/uc/intel_uc.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 30 ++ drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h | 14 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 25 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 3 +- drivers/gpu/drm/i915/i915_debugfs.c | 289 -- 29 files changed, 523 insertions(+), 360 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/execlists: Explicitly reset both reg and context runtime
Upon a GPU reset, we copy the default context image over top of the guilty image. This will rollback the CTX_TIMESTAMP register to before our value of ce->runtime.last. Reset both back to 0 so that we do not encounter an underflow on the next schedule out after resume. This should not be a huge issue in practice, as hangs should be rare in correct code. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index b12355048501..b458f8e17cf5 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1154,6 +1154,7 @@ static void restore_default_state(struct intel_context *ce, engine->context_size - PAGE_SIZE); execlists_init_reg_state(regs, ce, engine, ce->ring, false); + ce->runtime.last = intel_context_get_runtime(ce); } static void reset_active(struct i915_request *rq, @@ -4581,6 +4582,7 @@ static void init_common_reg_state(u32 * const regs, regs[CTX_CONTEXT_CONTROL] = ctl; regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID; + regs[CTX_TIMESTAMP] = 0; } static void init_wa_bb_reg_state(u32 * const regs, -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for i915 lpsp support for lpsp igt (rev5)
== Series Details ==
Series: i915 lpsp support for lpsp igt (rev5)
URL : https://patchwork.freedesktop.org/series/74648/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17097
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17097:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@debugfs_test@read_all_entries:
- {fi-ehl-1}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-ehl-1/igt@debugfs_test@read_all_entries.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-ehl-1/igt@debugfs_test@read_all_entries.html
* igt@runner@aborted:
- {fi-ehl-1}: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-ehl-1/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_17097 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-kbl-8809g: [PASS][4] -> [SKIP][5] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-8809g/igt@i915_pm_...@module-reload.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-kbl-8809g/igt@i915_pm_...@module-reload.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-icl-dsi: [DMESG-FAIL][6] ([fdo#108569]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-icl-u2: [INCOMPLETE][8] ([fdo#108569]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (49 -> 38)
--
Missing(11): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-kbl-7500u fi-ctg-p8600 fi-gdg-551 fi-skl-lmem fi-kbl-7560u fi-byt-clapper
fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* IGT: IGT_5539 -> IGTPW_4358
* Linux: CI_DRM_8195 -> Patchwork_17097
CI-20190529: 20190529
CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_4358: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4358/index.html
IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17097: df3af2bc5b98bdca45f071d60a5931f9d2af49eb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
df3af2bc5b98 drm/i915: Add connector dbgfs for all connectors
79871fceb2e0 drm/i915: Add i915_lpsp_info debugfs
ff6b22d263e3 drm/i915: Power well id for ICL PG3
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17097/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf
== Series Details == Series: series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf URL : https://patchwork.freedesktop.org/series/75124/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17099 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17099 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17099, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17099: ### IGT changes ### Possible regressions * igt@i915_selftest@live@execlists: - fi-skl-lmem:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-lmem/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-skl-lmem/igt@i915_selftest@l...@execlists.html - fi-skl-guc: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-guc/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-skl-guc/igt@i915_selftest@l...@execlists.html - fi-cfl-guc: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cfl-guc/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-cfl-guc/igt@i915_selftest@l...@execlists.html New tests - New tests have been introduced between CI_DRM_8195 and Patchwork_17099: ### New IGT tests (2) ### * igt@dmabuf@all@dma_fence_chain: - Statuses : 18 pass(s) - Exec time: [7.35, 29.18] s * igt@dmabuf@all@dma_fence_proxy: - Statuses : 18 pass(s) - Exec time: [0.03, 0.07] s Known issues Here are the changes found in Patchwork_17099 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-apl-guc: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927] / [fdo#112175]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-apl-guc/igt@i915_selftest@l...@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-apl-guc/igt@i915_selftest@l...@execlists.html - fi-kbl-x1275: [PASS][9] -> [INCOMPLETE][10] ([fdo#112259]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html - fi-cml-s: [PASS][11] -> [INCOMPLETE][12] ([i915#283]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cml-s/igt@i915_selftest@l...@execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-cml-s/igt@i915_selftest@l...@execlists.html - fi-skl-6700k2: [PASS][13] -> [INCOMPLETE][14] ([fdo#112175]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html - fi-cml-u2: [PASS][15] -> [INCOMPLETE][16] ([fdo#112175] / [i915#283]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cml-u2/igt@i915_selftest@l...@execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-cml-u2/igt@i915_selftest@l...@execlists.html - fi-kbl-guc: [PASS][17] -> [INCOMPLETE][18] ([CI#80] / [fdo#112175] / [fdo#112259]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-guc/igt@i915_selftest@l...@execlists.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-kbl-guc/igt@i915_selftest@l...@execlists.html - fi-kbl-7500u: [PASS][19] -> [INCOMPLETE][20] ([fdo#112175] / [fdo#112259]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-7500u/igt@i915_selftest@l...@execlists.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-kbl-7500u/igt@i915_selftest@l...@execlists.html - fi-kbl-8809g: [PASS][21] -> [INCOMPLETE][22] ([CI#80] / [fdo#112175] / [fdo#112259]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-8809g/igt@i915_selftest@l...@execlists.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17099/fi-kbl-8809g/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@requests: - fi-icl-guc: [PASS][23] -> [INCOMPLETE][24] ([fdo#109644] / [fdo#110464]) [23]:
Re: [Intel-gfx] [PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma
On Thu, 26 Mar 2020, Nathan Chancellor wrote: > This is the only warning on an x86_64 defconfig build. Apologies if we > are being too persistent or nagging but we need guidance from the i915 > maintainers on which solution they would prefer so it can be picked up. > I understand you all are busy and I appreciate the work you all do but > I do not want this to fall between the cracks because it is annoying to > constantly see this warning. Apologies for the delay. As I replied first thing in this thread, this works for me. Thanks for the patch, pushed to drm-intel-next-queued. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Check timeout before flush and cond checks
== Series Details ==
Series: drm/i915/selftests: Check timeout before flush and cond checks
URL : https://patchwork.freedesktop.org/series/75126/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17100
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17100 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17100, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17100:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@execlists:
- fi-skl-lmem:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-skl-lmem/igt@i915_selftest@l...@execlists.html
- fi-skl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-guc/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-skl-guc/igt@i915_selftest@l...@execlists.html
- fi-cfl-guc: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cfl-guc/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-cfl-guc/igt@i915_selftest@l...@execlists.html
- fi-bdw-5557u: [PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-bdw-5557u/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-bdw-5557u/igt@i915_selftest@l...@execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-ehl-1}: [PASS][9] -> [INCOMPLETE][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-ehl-1/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-ehl-1/igt@i915_selftest@l...@execlists.html
Known issues
Here are the changes found in Patchwork_17100 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-kbl-r: [PASS][11] -> [INCOMPLETE][12] ([fdo#112175] /
[fdo#112259])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-r/igt@i915_selftest@l...@execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-kbl-r/igt@i915_selftest@l...@execlists.html
- fi-apl-guc: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927] /
[fdo#112175])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-apl-guc/igt@i915_selftest@l...@execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-apl-guc/igt@i915_selftest@l...@execlists.html
- fi-kbl-x1275: [PASS][15] -> [INCOMPLETE][16] ([fdo#112259])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
- fi-skl-6600u: [PASS][17] -> [INCOMPLETE][18] ([i915#1260])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-6600u/igt@i915_selftest@l...@execlists.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-skl-6600u/igt@i915_selftest@l...@execlists.html
- fi-cml-s: [PASS][19] -> [INCOMPLETE][20] ([i915#283])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cml-s/igt@i915_selftest@l...@execlists.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-cml-s/igt@i915_selftest@l...@execlists.html
- fi-skl-6700k2: [PASS][21] -> [INCOMPLETE][22] ([fdo#112175])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html
- fi-icl-y: [PASS][23] -> [INCOMPLETE][24] ([i915#140])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-y/igt@i915_selftest@l...@execlists.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17100/fi-icl-y/igt@i915_selftest@l...@execlists.html
- fi-bxt-dsi: [PASS][25] -> [INCOMPLETE][26] ([fdo#103927])
[25]:
[Intel-gfx] [PATCH 2/2] drm/i915/execlists: Explicitly reset both reg and context runtime
Upon a GPU reset, we copy the default context image over top of the
guilty image. This will rollback the CTX_TIMESTAMP register to before
our value of ce->runtime.last. Reset both back to 0 so that we do not
encounter an underflow on the next schedule out after resume.
This should not be a huge issue in practice, as hangs should be rare in
correct code.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4edda15eba26..47cec545a069 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -238,6 +238,17 @@ __execlists_update_reg_state(const struct intel_context
*ce,
const struct intel_engine_cs *engine,
u32 head);
+static u32 intel_context_get_runtime(const struct intel_context *ce)
+{
+ /*
+* We can use either ppHWSP[16] which is recorded before the context
+* switch (and so excludes the cost of context switches) or use the
+* value from the context image itself, which is saved/restored earlier
+* and so includes the cost of the save.
+*/
+ return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
+}
+
static void mark_eio(struct i915_request *rq)
{
if (i915_request_completed(rq))
@@ -1154,6 +1165,7 @@ static void restore_default_state(struct intel_context
*ce,
engine->context_size - PAGE_SIZE);
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+ ce->runtime.last = intel_context_get_runtime(ce);
}
static void reset_active(struct i915_request *rq,
@@ -1195,17 +1207,6 @@ static void reset_active(struct i915_request *rq,
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
}
-static u32 intel_context_get_runtime(const struct intel_context *ce)
-{
- /*
-* We can use either ppHWSP[16] which is recorded before the context
-* switch (and so excludes the cost of context switches) or use the
-* value from the context image itself, which is saved/restored earlier
-* and so includes the cost of the save.
-*/
- return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
-}
-
static void st_update_runtime_underflow(struct intel_context *ce, s32 dt)
{
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
@@ -4581,6 +4582,7 @@ static void init_common_reg_state(u32 * const regs,
regs[CTX_CONTEXT_CONTROL] = ctl;
regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
+ regs[CTX_TIMESTAMP] = 0;
}
static void init_wa_bb_reg_state(u32 * const regs,
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).
process_csb: vecs0: cs-irq head=0, tail=1
process_csb: vecs0: csb[1]: status=0x0882:0x0020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
process_csb: vecs0: cs-irq head=1, tail=2
process_csb: vecs0: csb[2]: status=0x0814:0x0040
trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
process_csb: vecs0: cs-irq head=2, tail=5
process_csb: vecs0: csb[3]: status=0x0812:0x0020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[4]: status=0x0814:0x0060
trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[5]: status=0x0818:0x0020
trace_ports: vecs0: completed { 8c0:32, 0:0 }
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8,
ctl:, mode:0200}
process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32,
hwsp:30},
process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
process_csb: GEM_BUG_ON("context completed before request")
Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 72 ++---
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..4edda15eba26 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request
**ports, int count)
memset_p((void **)ports, NULL, count);
}
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
execlists->queue_priority_hint);
record_preemption(execlists);
- /*
-* Don't let the RING_HEAD advance past the breadcrumb
-* as we unwind (and until we resubmit) so that we do
-* not accidentally tell it to go backwards.
-*/
- ring_set_paused(engine, 1);
-
/*
* Note that we have not stopped the GPU at this point,
* so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
last->sched.attr.priority,
execlists->queue_priority_hint);
- ring_set_paused(engine, 1);
defer_active(engine);
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* of timeslices, our queue might be.
*/
start_timeslice(engine);
- return;
+ return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
if (last && !can_merge_rq(last, rq)) {
+ /* leave this for another sibling */
spin_unlock(>base.active.lock);
start_timeslice(engine);
- return; /* leave this for another sibling */
+ return false;
}
ENGINE_TRACE(engine,
@@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ if (!submit)
+ return false;
- if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev2)
== Series Details ==
Series: drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle
context (rev2)
URL : https://patchwork.freedesktop.org/series/75130/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17104
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/index.html
Known issues
Here are the changes found in Patchwork_17104 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-cml-s: [PASS][1] -> [INCOMPLETE][2] ([i915#283])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-cml-s/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-cml-s/igt@i915_selftest@l...@execlists.html
- fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([i915#140])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-y/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-icl-y/igt@i915_selftest@l...@execlists.html
- fi-bxt-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-icl-u2: [INCOMPLETE][7] ([fdo#108569]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-icl-dsi: [DMESG-FAIL][9] ([fdo#108569]) -> [INCOMPLETE][10]
([i915#140])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
[i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647
Participating hosts (49 -> 38)
--
Missing(11): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-ivb-3770 fi-kbl-7560u fi-byt-clapper fi-bsw-nick fi-bdw-samus
fi-snb-2600
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8195 -> Patchwork_17104
CI-20190529: 20190529
CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17104: f75f1d1d76f832a0e3d9d64dd675ceb56040582c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f75f1d1d76f8 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle
context
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17104/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).
process_csb: vecs0: cs-irq head=0, tail=1
process_csb: vecs0: csb[1]: status=0x0882:0x0020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
process_csb: vecs0: cs-irq head=1, tail=2
process_csb: vecs0: csb[2]: status=0x0814:0x0040
trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
process_csb: vecs0: cs-irq head=2, tail=5
process_csb: vecs0: csb[3]: status=0x0812:0x0020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[4]: status=0x0814:0x0060
trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[5]: status=0x0818:0x0020
trace_ports: vecs0: completed { 8c0:32, 0:0 }
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8,
ctl:, mode:0200}
process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32,
hwsp:30},
process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
process_csb: GEM_BUG_ON("context completed before request")
Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 68 ++---
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..132816235d8a 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request
**ports, int count)
memset_p((void **)ports, NULL, count);
}
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
execlists->queue_priority_hint);
record_preemption(execlists);
- /*
-* Don't let the RING_HEAD advance past the breadcrumb
-* as we unwind (and until we resubmit) so that we do
-* not accidentally tell it to go backwards.
-*/
- ring_set_paused(engine, 1);
-
/*
* Note that we have not stopped the GPU at this point,
* so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
last->sched.attr.priority,
execlists->queue_priority_hint);
- ring_set_paused(engine, 1);
defer_active(engine);
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* of timeslices, our queue might be.
*/
start_timeslice(engine);
- return;
+ return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
if (last && !can_merge_rq(last, rq)) {
+ /* leave this for another sibling */
spin_unlock(>base.active.lock);
start_timeslice(engine);
- return; /* leave this for another sibling */
+ return false;
}
ENGINE_TRACE(engine,
@@ -2193,32 +2186,30 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ if (!submit)
+ return false;
- if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
-
[Intel-gfx] [PATCH 2/2] drm/i915/execlists: Explicitly reset both reg and context runtime
Upon a GPU reset, we copy the default context image over top of the
guilty image. This will rollback the CTX_TIMESTAMP register to before
our value of ce->runtime.last. Reset both back to 0 so that we do not
encounter an underflow on the next schedule out after resume.
This should not be a huge issue in practice, as hangs should be rare in
correct code.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 132816235d8a..987dbdf2542e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -238,6 +238,17 @@ __execlists_update_reg_state(const struct intel_context
*ce,
const struct intel_engine_cs *engine,
u32 head);
+static u32 intel_context_get_runtime(const struct intel_context *ce)
+{
+ /*
+* We can use either ppHWSP[16] which is recorded before the context
+* switch (and so excludes the cost of context switches) or use the
+* value from the context image itself, which is saved/restored earlier
+* and so includes the cost of the save.
+*/
+ return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
+}
+
static void mark_eio(struct i915_request *rq)
{
if (i915_request_completed(rq))
@@ -1154,6 +1165,7 @@ static void restore_default_state(struct intel_context
*ce,
engine->context_size - PAGE_SIZE);
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+ ce->runtime.last = intel_context_get_runtime(ce);
}
static void reset_active(struct i915_request *rq,
@@ -1195,17 +1207,6 @@ static void reset_active(struct i915_request *rq,
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
}
-static u32 intel_context_get_runtime(const struct intel_context *ce)
-{
- /*
-* We can use either ppHWSP[16] which is recorded before the context
-* switch (and so excludes the cost of context switches) or use the
-* value from the context image itself, which is saved/restored earlier
-* and so includes the cost of the save.
-*/
- return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
-}
-
static void st_update_runtime_underflow(struct intel_context *ce, s32 dt)
{
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
@@ -4581,6 +4582,7 @@ static void init_common_reg_state(u32 * const regs,
regs[CTX_CONTEXT_CONTROL] = ctl;
regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
+ regs[CTX_TIMESTAMP] = 0;
}
static void init_wa_bb_reg_state(u32 * const regs,
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Re-org uC debugfs files and move them under GT (rev3)
== Series Details == Series: Re-org uC debugfs files and move them under GT (rev3) URL : https://patchwork.freedesktop.org/series/74051/ State : success == Summary == CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17102 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17102/index.html Known issues Here are the changes found in Patchwork_17102 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live@execlists: - fi-icl-dsi: [DMESG-FAIL][1] ([fdo#108569]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17102/fi-icl-dsi/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@hangcheck: - fi-icl-u2: [INCOMPLETE][3] ([fdo#108569]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17102/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 Participating hosts (49 -> 38) -- Missing(11): fi-ilk-m540 fi-kbl-7560u fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-blb-e6850 fi-byt-clapper fi-bdw-samus fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8195 -> Patchwork_17102 CI-20190529: 20190529 CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17102: 209216ba5e1f65dfed02f205abefae348e040176 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 209216ba5e1f drm/i915/uc: do not free err log on uc_fini 33c4bb916643 drm/i915/uc: Move uC debugfs to its own folder under GT ada6ea1bdc35 drm/i915/debugfs: move uC printers and update debugfs file names 6d5324446d31 drm/i915/huc: make "support huc" reflect HW capabilities 72a498f33e07 drm/i915/guc: drop stage_pool debugfs e19786b07259 drm/i915/gt: allow setting generic data pointer == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17102/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev3)
== Series Details == Series: SAGV support for Gen12+ (rev3) URL : https://patchwork.freedesktop.org/series/75129/ State : success == Summary == CI Bug Log - changes from CI_DRM_8195 -> Patchwork_17103 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/index.html Known issues Here are the changes found in Patchwork_17103 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@hangcheck: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-apl-guc/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/fi-apl-guc/igt@i915_selftest@l...@hangcheck.html Possible fixes * igt@i915_selftest@live@execlists: - fi-icl-dsi: [DMESG-FAIL][3] ([fdo#108569]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-dsi/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/fi-icl-dsi/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@hangcheck: - fi-icl-u2: [INCOMPLETE][5] ([fdo#108569]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8195/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 Participating hosts (49 -> 37) -- Missing(12): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-bsw-kefka fi-kbl-7560u fi-byt-clapper fi-skl-6600u Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8195 -> Patchwork_17103 CI-20190529: 20190529 CI_DRM_8195: bcb3db890b651ee74ca510bbc4dacebdaa65d311 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17103: 17b1ab4ef65f19f4159f1dcf8939b989d1cf83b9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 17b1ab4ef65f drm/i915: Enable SAGV support for Gen12 9ab9d139acd7 drm/i915: Restrict qgv points which don't have enough bandwidth. 7ddef9fc5a42 drm/i915: Rename bw_state to new_bw_state 5ac95b3960a7 drm/i915: Added required new PCode commands 37f392cf14b8 drm/i915: Add proper SAGV support for TGL+ 345239c1e284 drm/i915: Extract gen specific functions from intel_can_enable_sagv 9cd6396bdbd9 drm/i915: Add intel_atomic_get_bw_*_state helpers b76321aa6824 drm/i915: Introduce skl_plane_wm_level accessor. 930754956920 drm/i915: Eliminate magic numbers "0" and "1" from color plane ad8810ff373a drm/i915: Start passing latency as parameter == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17103/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drivers/gpu/drm/i915/selftests/i915_buddy.c: Fix bug
On Wed, 25 Mar 2020 at 21:23, George Spelvin wrote: > > igt_mm_config() calls ilog2() on the (pseudo)random 21-bit number > s>>12. Once in 2 million seeds, this is zero and ilog2 summons > the nasal demons. > > There was an attempt to handle this case with a max(), but that's > too late; ms could already be something bizarre. > > Given that the low 12 bits of s and ms are always zero, it's a lot > simpler just to divide them by 4096, then everything fits into 32 > bits, and we can easily generate a random number 1 <= s <= 0x1f. > > Signed-off-by: George Spelvin > Fixes: 14d1b9a6247c > Cc: Matthew Auld > Cc: Jani Nikula > Cc: Joonas Lahtinen > Cc: Rodrigo Vivi > Cc: intel-gfx@lists.freedesktop.org Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).
process_csb: vecs0: cs-irq head=0, tail=1
process_csb: vecs0: csb[1]: status=0x0882:0x0020
trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
process_csb: vecs0: cs-irq head=1, tail=2
process_csb: vecs0: csb[2]: status=0x0814:0x0040
trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
process_csb: vecs0: cs-irq head=2, tail=5
process_csb: vecs0: csb[3]: status=0x0812:0x0020
trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
process_csb: vecs0: csb[4]: status=0x0814:0x0060
trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[5]: status=0x0818:0x0020
trace_ports: vecs0: completed { 8c0:32, 0:0 }
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8,
ctl:, mode:0200}
process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32,
hwsp:30},
process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
process_csb: process_csb:2449 GEM_BUG_ON("context completed before request")
Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 71 ++---
1 file changed, 35 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..9e24ff7451a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request
**ports, int count)
memset_p((void **)ports, NULL, count);
}
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
execlists->queue_priority_hint);
record_preemption(execlists);
- /*
-* Don't let the RING_HEAD advance past the breadcrumb
-* as we unwind (and until we resubmit) so that we do
-* not accidentally tell it to go backwards.
-*/
- ring_set_paused(engine, 1);
-
/*
* Note that we have not stopped the GPU at this point,
* so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
last->sched.attr.priority,
execlists->queue_priority_hint);
- ring_set_paused(engine, 1);
defer_active(engine);
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* of timeslices, our queue might be.
*/
start_timeslice(engine);
- return;
+ return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
if (last && !can_merge_rq(last, rq)) {
+ /* leave this for another sibling */
spin_unlock(>base.active.lock);
start_timeslice(engine);
- return; /* leave this for another sibling */
+ return false;
}
ENGINE_TRACE(engine,
@@ -2193,32 +2186,30 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ if (!submit)
+ return false;
- if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
-
Re: [Intel-gfx] [PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma
On Mon, Mar 16, 2020 at 02:41:23PM -0700, Nick Desaulniers wrote: > On Fri, Feb 14, 2020 at 7:36 AM Michel Dänzer wrote: > > > > On 2020-02-14 12:49 p.m., Jani Nikula wrote: > > > On Fri, 14 Feb 2020, Chris Wilson wrote: > > >> Quoting Jani Nikula (2020-02-14 06:36:15) > > >>> On Thu, 13 Feb 2020, Nathan Chancellor wrote: > > A recent commit in clang added -Wtautological-compare to -Wall, which > > is > > enabled for i915 after -Wtautological-compare is disabled for the rest > > of the kernel so we see the following warning on x86_64: > > > > ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1433:22: warning: > > result of comparison of constant 576460752303423487 with expression of > > type 'unsigned int' is always false > > [-Wtautological-constant-out-of-range-compare] > > if (unlikely(remain > N_RELOC(ULONG_MAX))) > > ^ > > ../include/linux/compiler.h:78:42: note: expanded from macro > > 'unlikely' > > # define unlikely(x)__builtin_expect(!!(x), 0) > > ^ > > 1 warning generated. > > > > It is not wrong in the case where ULONG_MAX > UINT_MAX but it does not > > account for the case where this file is built for 32-bit x86, where > > ULONG_MAX == UINT_MAX and this check is still relevant. > > > > Cast remain to unsigned long, which keeps the generated code the same > > (verified with clang-11 on x86_64 and GCC 9.2.0 on x86 and x86_64) and > > the warning is silenced so we can catch more potential issues in the > > future. > > > > Link: https://github.com/ClangBuiltLinux/linux/issues/778 > > Suggested-by: Michel Dänzer > > Signed-off-by: Nathan Chancellor > > >>> > > >>> Works for me as a workaround, > > >> > > >> But the whole point was that the compiler could see that it was > > >> impossible and not emit the code. Doesn't this break that? > > > > > > It seems that goal and the warning are fundamentally incompatible. > > > > Not really: > > > > if (sizeof(remain) >= sizeof(unsigned long) && > > unlikely(remain > N_RELOC(ULONG_MAX))) > > return -EINVAL; > > > > In contrast to the cast, this doesn't generate any machine code on 64-bit: > > > > https://godbolt.org/z/GmUE4S > > > > but still generates the same code on 32-bit: > > > > https://godbolt.org/z/hAoz8L > > Exactly. > > This check is only a tautology when `sizeof(long) == sizeof(int)` (ie. > ILP32 platforms, like 32b x86), notice how BOTH GCC AND Clang generate > exactly the same code: https://godbolt.org/z/6ShrDM > > Both compilers eliminate the check when `-m32` is not set, and > generate the exact same check otherwise. How about: > ``` > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index d3f4f28e9468..25b9d3f3ad57 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -1415,8 +1415,10 @@ static int eb_relocate_vma(struct > i915_execbuffer *eb, struct eb_vma *ev) > > urelocs = u64_to_user_ptr(entry->relocs_ptr); > remain = entry->relocation_count; > +#ifndef CONFIG_64BIT > if (unlikely(remain > N_RELOC(ULONG_MAX))) > return -EINVAL; > +#endif > > /* > * We must check that the entire relocation array is safe > ``` > > We now have 4 proposed solutions: > 1. > https://lore.kernel.org/lkml/20191123195321.41305-1-natechancel...@gmail.com/ > 2. > https://lore.kernel.org/lkml/20200211050808.29463-1-natechancel...@gmail.com/ > 3. > https://lore.kernel.org/lkml/20200214054706.33870-1-natechancel...@gmail.com/ > 4. my diff above > Let's please come to a resolution on this. This is the only warning on an x86_64 defconfig build. Apologies if we are being too persistent or nagging but we need guidance from the i915 maintainers on which solution they would prefer so it can be picked up. I understand you all are busy and I appreciate the work you all do but I do not want this to fall between the cracks because it is annoying to constantly see this warning. Cheers, Nathan ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/execlists: Explicitly reset both reg and context runtime
== Series Details == Series: drm/i915/execlists: Explicitly reset both reg and context runtime URL : https://patchwork.freedesktop.org/series/75127/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o drivers/gpu/drm/i915/gt/intel_lrc.c: In function ‘restore_default_state’: drivers/gpu/drm/i915/gt/intel_lrc.c:1157:21: error: implicit declaration of function ‘intel_context_get_runtime’; did you mean ‘intel_context_get_avg_runtime_ns’? [-Werror=implicit-function-declaration] ce->runtime.last = intel_context_get_runtime(ce); ^ intel_context_get_avg_runtime_ns drivers/gpu/drm/i915/gt/intel_lrc.c: At top level: drivers/gpu/drm/i915/gt/intel_lrc.c:1199:12: error: conflicting types for ‘intel_context_get_runtime’ static u32 intel_context_get_runtime(const struct intel_context *ce) ^ drivers/gpu/drm/i915/gt/intel_lrc.c:1157:21: note: previous implicit declaration of ‘intel_context_get_runtime’ was here ce->runtime.last = intel_context_get_runtime(ce); ^ cc1: all warnings being treated as errors scripts/Makefile.build:267: recipe for target 'drivers/gpu/drm/i915/gt/intel_lrc.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/intel_lrc.o] Error 1 scripts/Makefile.build:505: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:505: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:505: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1683: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Re-org uC debugfs files and move them under GT (rev3)
== Series Details == Series: Re-org uC debugfs files and move them under GT (rev3) URL : https://patchwork.freedesktop.org/series/74051/ State : warning == Summary == $ dim checkpatch origin/drm-tip e19786b07259 drm/i915/gt: allow setting generic data pointer 72a498f33e07 drm/i915/guc: drop stage_pool debugfs 6d5324446d31 drm/i915/huc: make "support huc" reflect HW capabilities ada6ea1bdc35 drm/i915/debugfs: move uC printers and update debugfs file names 33c4bb916643 drm/i915/uc: Move uC debugfs to its own folder under GT -:97: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #97: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 516 lines checked 209216ba5e1f drm/i915/uc: do not free err log on uc_fini ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev2)
== Series Details ==
Series: drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle
context (rev2)
URL : https://patchwork.freedesktop.org/series/75130/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f75f1d1d76f8 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle
context
-:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#29:
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8,
ctl:, mode:0200}
total: 0 errors, 1 warnings, 0 checks, 125 lines checked
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/perf: Do not clear pollin for small user read buffers (rev2)
== Series Details == Series: drm/i915/perf: Do not clear pollin for small user read buffers (rev2) URL : https://patchwork.freedesktop.org/series/75085/ State : success == Summary == CI Bug Log - changes from CI_DRM_8190_full -> Patchwork_17092_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17092_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180] / [i915#93] / [i915#95]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-kbl4/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-kbl1/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_isolation@vcs1-nonpriv: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb1/igt@gem_ctx_isolat...@vcs1-nonpriv.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-iclb5/igt@gem_ctx_isolat...@vcs1-nonpriv.html * igt@gem_exec_schedule@implicit-read-write-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#677]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb8/igt@gem_exec_sched...@implicit-read-write-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-iclb4/igt@gem_exec_sched...@implicit-read-write-bsd.html * igt@gem_exec_schedule@implicit-write-read-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb1/igt@gem_exec_sched...@implicit-write-read-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-iclb3/igt@gem_exec_sched...@implicit-write-read-bsd2.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb8/igt@gem_exec_sched...@preempt-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-iclb2/igt@gem_exec_sched...@preempt-bsd.html * igt@i915_selftest@live@requests: - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#109644] / [fdo#110464]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb2/igt@i915_selftest@l...@requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-iclb7/igt@i915_selftest@l...@requests.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [PASS][13] -> [FAIL][14] ([IGT#5]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-skl5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#52] / [i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl3/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-untiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-skl9/igt@kms_draw_...@draw-method-rgb565-mmap-cpu-untiled.html * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#52] / [i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-glk5/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-xtiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-glk6/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-xtiled.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl4/igt@kms_...@bpc-switch.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-skl1/igt@kms_...@bpc-switch.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-kbl7/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17092/shard-kbl7/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-apl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [24]:
[Intel-gfx] [PATCH 1/7] drm/i915/display: Add HDR Capability detection for LSPCON
From: Uma Shankar
LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES
DPCD register. LSPCON implementations capable of supporting
HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch
reads the same, detects the HDR capability and adds this to
intel_lspcon struct.
Signed-off-by: Uma Shankar
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 32 +++
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 888ea8a170d1..2f281da6d253 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1333,6 +1333,7 @@ struct intel_lspcon {
bool active;
enum drm_lspcon_mode mode;
enum lspcon_vendor vendor;
+ bool hdr_supported;
};
struct intel_digital_port {
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d807c5648c87..2e41ae483a23 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -35,6 +35,8 @@
#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
#define LSPCON_VENDOR_MCA_OUI 0x0060AD
+#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
+
/* AUX addresses to write MCA AVI IF */
#define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
#define LSPCON_MCA_AVI_IF_CTRL 0x5DF
@@ -104,6 +106,31 @@ static bool lspcon_detect_vendor(struct intel_lspcon
*lspcon)
return true;
}
+static bool lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
+{
+ struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ u8 hdr_caps;
+ int ret;
+
+ /* Enable HDR for MCA based LSPCON devices */
+ if (lspcon->vendor == LSPCON_VENDOR_MCA)
+ ret = drm_dp_dpcd_read(>aux, DPCD_MCA_LSPCON_HDR_STATUS,
+ _caps, 1);
+ else
+ return false;
+
+ if (ret < 0) {
+ DRM_DEBUG_KMS("hdr capability detection failed\n");
+ lspcon->hdr_supported = false;
+ return false;
+ } else if (hdr_caps & 0x1) {
+ DRM_DEBUG_KMS("lspcon capable of HDR\n");
+ lspcon->hdr_supported = true;
+ }
+
+ return true;
+}
+
static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon
*lspcon)
{
enum drm_lspcon_mode current_mode;
@@ -581,6 +608,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
return false;
}
+ if (!lspcon_detect_hdr_capability(lspcon)) {
+ DRM_ERROR("LSPCON hdr detection failed\n");
+ return false;
+ }
+
connector->ycbcr_420_allowed = true;
lspcon->active = true;
DRM_DEBUG_KMS("Success: LSPCON init\n");
--
2.26.0
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable HDR on Gen9 devices with lspcon hdr capability
== Series Details == Series: Enable HDR on Gen9 devices with lspcon hdr capability URL : https://patchwork.freedesktop.org/series/75148/ State : failure == Summary == Applying: drm/i915/display: Add HDR Capability detection for LSPCON Applying: drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Applying: drm/i915/display: Attach HDR property for capable Gen9 devices Applying: drm/i915/display: Set HDR Infoframe for HDR capable LSPCON devices Applying: drm/i915/display: Enable BT2020 for HDR on LSPCON devices Applying: drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON Applying: drm:i915:display: add checks for Gen9 devices with hdr capability error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_hdmi.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0007 drm:i915:display: add checks for Gen9 devices with hdr capability When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON
From: Uma Shankar
Blanking needs to be reduced to incorporate DP and HDMI timing/link
bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
This will cause mode to blank out. Reduced Htotal by shortening the
back porch and front porch within permissible limits.
v2: This is marked as Not for merge and the responsibilty to program
these custom timings will be on userspace. This patch is just for
reference purposes. This is based on Ville's recommendation.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c7424e2a04a3..3ab1fadb2ea3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -616,9 +616,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
{
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct intel_encoder *intel_encoder =
intel_attached_encoder(intel_connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_i915_private *dev_priv = to_i915(connector->dev);
int target_clock = mode->clock;
+ struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder);
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk;
u16 dsc_max_output_bpp = 0;
@@ -638,6 +640,20 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock = fixed_mode->clock;
}
+ /*
+* Reducing Blanking to incorporate DP and HDMI timing/link bandwidth
+* limitations for CEA modes (4k@60 at 10 bpp). DP can drive 17.28Gbs
+* while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will
+* cause mode to blank out. Reduced Htotal by shortening the back porch
+* and front porch within permissible limits.
+*/
+ if (lspcon->active && lspcon->hdr_supported &&
+ mode->clock > 57) {
+ mode->clock = 57;
+ mode->htotal -= 180;
+ mode->hsync_start -= 72;
+ mode->hsync_end -= 72;
+ }
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
--
2.26.0
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[Intel-gfx] [PATCH 5/7] drm/i915/display: Enable BT2020 for HDR on LSPCON devices
From: Uma Shankar
Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
data for HDR using AVI infoframe. LSPCON firmware expects this and though
SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
which transfers the same to HDMI sink.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 4d8027493f2c..5cede4f07f22 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -506,6 +506,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder,
/* FIXME implement this */
}
+/* HDMI HDR Colorspace Spec Definitions */
+#define NORMAL_COLORIMETRY_MASK0x3
+#define EXTENDED_COLORIMETRY_MASK 0x7
+#define HDMI_COLORIMETRY_BT2020_YCC((3 << 0) | (6 << 2) | (0 << 5))
+
void lspcon_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
@@ -550,6 +555,19 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
HDMI_QUANTIZATION_RANGE_LIMITED :
HDMI_QUANTIZATION_RANGE_FULL);
+ /*
+* Set BT2020 colorspace if driving HDR data
+* ToDo: Make this generic and expose all colorspaces for lspcon
+*/
+ if (lspcon->active && conn_state->hdr_metadata_changed) {
+ frame.avi.colorimetry =
+ HDMI_COLORIMETRY_BT2020_YCC &
+ NORMAL_COLORIMETRY_MASK;
+ frame.avi.extended_colorimetry =
+ (HDMI_COLORIMETRY_BT2020_YCC >> 2) &
+EXTENDED_COLORIMETRY_MASK;
+ }
+
ret = hdmi_infoframe_pack(, buf, sizeof(buf));
if (ret < 0) {
DRM_ERROR("Failed to pack AVI IF\n");
--
2.26.0
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[Intel-gfx] [PATCH 3/7] drm/i915/display: Attach HDR property for capable Gen9 devices
From: Uma Shankar
Attach HDR property for Gen9 devices with MCA LSPCON
chips.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index c5ddabf903d6..4d8027493f2c 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -628,6 +628,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
return false;
}
+ if (lspcon->vendor == LSPCON_VENDOR_MCA && lspcon->hdr_supported)
+ drm_object_attach_property(>base,
+
connector->dev->mode_config.hdr_output_metadata_property,
+ 0);
+
connector->ycbcr_420_allowed = true;
lspcon->active = true;
DRM_DEBUG_KMS("Success: LSPCON init\n");
--
2.26.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/7] drm:i915:display: add checks for Gen9 devices with hdr capability
this patch adds hdr capabilities checks for Gen9 devices with
lspcon support.
Signed-off-by: Vipin Anand
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 17 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 9 +++--
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 9ae2f88cc925..70d0d76ed606 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -833,9 +833,12 @@ intel_hdmi_compute_drm_infoframe(struct intel_encoder
*encoder,
{
struct hdmi_drm_infoframe *frame = _state->infoframes.drm.drm;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
int ret;
- if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
+ if (!(INTEL_GEN(dev_priv) >= 10 ||
+ (((INTEL_GEN(dev_priv) >= 9)) &&
+ intel_dig_port->lspcon.active)))
return true;
if (!crtc_state->has_infoframe)
@@ -2102,9 +2105,12 @@ static int intel_hdmi_source_max_tmds_clock(struct
intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
const struct ddi_vbt_port_info *info =
_priv->vbt.ddi_port_info[encoder->port];
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
int max_tmds_clock;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 10 ||
+ (((INTEL_GEN(dev_priv) >= 9)) &&
+intel_dig_port->lspcon.active))
max_tmds_clock = 594000;
else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
max_tmds_clock = 30;
@@ -2423,6 +2429,7 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
int ret;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -2469,7 +2476,8 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
pipe_config->lane_count = 4;
if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
- IS_GEMINILAKE(dev_priv))) {
+ (((INTEL_GEN(dev_priv) >= 9)) &&
+ intel_dig_port->lspcon.active))) {
if (scdc->scrambling.low_rates)
pipe_config->hdmi_scrambling = true;
@@ -3171,7 +3179,8 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
connector->doublescan_allowed = 0;
connector->stereo_allowed = 1;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 10 ||
+ (((INTEL_GEN(dev_priv) >= 9)) && intel_dig_port->lspcon.active))
connector->ycbcr_420_allowed = true;
intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 5cede4f07f22..be074acd74f3 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -116,6 +116,8 @@ static bool lspcon_detect_hdr_capability(struct
intel_lspcon *lspcon)
if (lspcon->vendor == LSPCON_VENDOR_MCA)
ret = drm_dp_dpcd_read(>aux, DPCD_MCA_LSPCON_HDR_STATUS,
_caps, 1);
+ else if (lspcon->vendor == LSPCON_VENDOR_PARADE)
+ return true;
else
return false;
@@ -474,7 +476,8 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
* Todo: Add support for Parade later
*/
if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
- lspcon->vendor != LSPCON_VENDOR_MCA)
+ (lspcon->vendor != LSPCON_VENDOR_MCA ||
+lspcon->vendor != LSPCON_VENDOR_PARADE))
return;
if (lspcon->vendor == LSPCON_VENDOR_MCA) {
@@ -646,7 +649,9 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
return false;
}
- if (lspcon->vendor == LSPCON_VENDOR_MCA && lspcon->hdr_supported)
+ if ((lspcon->vendor == LSPCON_VENDOR_MCA ||
+lspcon->vendor == LSPCON_VENDOR_PARADE) &&
+lspcon->hdr_supported)
drm_object_attach_property(>base,
connector->dev->mode_config.hdr_output_metadata_property,
0);
--
2.26.0
[Intel-gfx] [PATCH 2/7] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
From: Uma Shankar
Gen9 hardware supports HDMI2.0 through LSPCON chips.
Extending HDR support for MCA LSPCON based GEN9 devices.
SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering Infoframe (DRM packets) and send it to HDR capable
HDMI sink devices.
v2: Re-used hsw infoframe write implementation for HDR metadata
for LSPCON as per Ville's suggestion.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++
drivers/gpu/drm/i915/display/intel_lspcon.c | 35 +++--
drivers/gpu/drm/i915/display/intel_lspcon.h | 5 ++-
3 files changed, 39 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 93ac0f296852..9ae2f88cc925 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -577,6 +577,16 @@ static u32 hsw_infoframes_enabled(struct intel_encoder
*encoder,
return val & mask;
}
+void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type,
+ const void *frame, ssize_t len)
+{
+ DRM_DEBUG_KMS("Update HDR metadata for lspcon\n");
+ /* It uses the legacy hsw implementation for the same */
+ hsw_write_infoframe(encoder, crtc_state, type, frame, len);
+}
+
static const u8 infoframe_type_to_idx[] = {
HDMI_PACKET_TYPE_GENERAL_CONTROL,
HDMI_PACKET_TYPE_GAMUT_METADATA,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 2e41ae483a23..c5ddabf903d6 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -460,27 +460,42 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
unsigned int type,
const void *frame, ssize_t len)
{
- bool ret;
+ bool ret = true;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
/* LSPCON only needs AVI IF */
- if (type != HDMI_INFOFRAME_TYPE_AVI)
+ if (!(type == HDMI_INFOFRAME_TYPE_AVI ||
+ type == HDMI_PACKET_TYPE_GAMUT_METADATA))
return;
- if (lspcon->vendor == LSPCON_VENDOR_MCA)
- ret = _lspcon_write_avi_infoframe_mca(_dp->aux,
- frame, len);
- else
- ret = _lspcon_write_avi_infoframe_parade(_dp->aux,
-frame, len);
+ /*
+* Supporting HDR on MCA LSPCON
+* Todo: Add support for Parade later
+*/
+ if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
+ lspcon->vendor != LSPCON_VENDOR_MCA)
+ return;
+
+ if (lspcon->vendor == LSPCON_VENDOR_MCA) {
+ if (type == HDMI_INFOFRAME_TYPE_AVI)
+ ret = _lspcon_write_avi_infoframe_mca(_dp->aux,
+ frame, len);
+ else if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
+ lspcon_drm_write_infoframe(encoder, crtc_state,
+
HDMI_PACKET_TYPE_GAMUT_METADATA,
+ frame, VIDEO_DIP_DATA_SIZE);
+ } else {
+ ret = _lspcon_write_avi_infoframe_parade(_dp->aux, frame,
+len);
+ }
if (!ret) {
- DRM_ERROR("Failed to write AVI infoframes\n");
+ DRM_ERROR("Failed to write infoframes\n");
return;
}
- DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
+ DRM_DEBUG_DRIVER("Infoframes updated successfully\n");
}
void lspcon_read_infoframe(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 37cfddf8a9c5..b2051f236223 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -34,5 +34,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config);
void lspcon_ycbcr420_config(struct drm_connector *connector,
struct intel_crtc_state *crtc_state);
-
+void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type,
+ const void *frame, ssize_t len);
#endif /* __INTEL_LSPCON_H__ */
--
2.26.0
___
Intel-gfx
[Intel-gfx] [PATCH 4/7] drm/i915/display: Set HDR Infoframe for HDR capable LSPCON devices
From: Uma Shankar
Send Dynamic Range and Mastering Infoframe (DRM for HDR metadata)
as SDP packet to LSPCON following the DP spec. LSPCON receives the
same and sends it to HDMI sink.
v2: Suppressed some warnings. No functional change.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 1 +
drivers/gpu/drm/drm_atomic_uapi.c | 1 +
drivers/gpu/drm/i915/display/intel_lspcon.h | 1 +
include/drm/drm_connector.h | 1 +
4 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index 7cf3cf936547..7cf98c06f424 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -468,6 +468,7 @@ __drm_atomic_helper_connector_duplicate_state(struct
drm_connector *connector,
if (state->hdr_output_metadata)
drm_property_blob_get(state->hdr_output_metadata);
+ state->hdr_metadata_changed = false;
/* Don't copy over a writeback job, they are used only once */
state->writeback_job = NULL;
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index a1e5e262bae2..4c520e0b9872 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -734,6 +734,7 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
val,
sizeof(struct hdr_output_metadata), -1,
);
+ state->hdr_metadata_changed |= replaced;
return ret;
} else if (property == config->aspect_ratio_property) {
state->picture_aspect_ratio = val;
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h
b/drivers/gpu/drm/i915/display/intel_lspcon.h
index b2051f236223..bc34124f532e 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -38,4 +38,5 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
unsigned int type,
const void *frame, ssize_t len);
+
#endif /* __INTEL_LSPCON_H__ */
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 221910948b37..28df268aa1a7 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -661,6 +661,7 @@ struct drm_connector_state {
* DRM blob property for HDR output metadata
*/
struct drm_property_blob *hdr_output_metadata;
+ u8 hdr_metadata_changed : 1;
};
/**
--
2.26.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/7] Enable HDR on Gen9 devices with lspcon hdr capability
Initial patch series submitted https://patchwork.freedesktop.org/series/68081/ this patch series add hdr support for GLK platform, I have added patch to add checks for all Gen9 platforms with lspcon hdr capability. Uma Shankar (6): drm/i915/display: Add HDR Capability detection for LSPCON drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon drm/i915/display: Attach HDR property for capable Gen9 devices drm/i915/display: Set HDR Infoframe for HDR capable LSPCON devices drm/i915/display: Enable BT2020 for HDR on LSPCON devices drm/i915/display: Reduce blanking to support 4k60@10bpp for LSPCON Vipin Anand (1): drm:i915:display: add checks for Gen9 devices with hdr capability drivers/gpu/drm/drm_atomic_state_helper.c | 1 + drivers/gpu/drm/drm_atomic_uapi.c | 1 + .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 16 drivers/gpu/drm/i915/display/intel_hdmi.c | 27 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 95 +-- drivers/gpu/drm/i915/display/intel_lspcon.h | 4 + include/drm/drm_connector.h | 1 + 8 files changed, 132 insertions(+), 14 deletions(-) -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on
ELSP[1] promotion to idle context
URL : https://patchwork.freedesktop.org/series/75137/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5868edb0b7b7 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle
context
-:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#29:
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8,
ctl:, mode:0200}
total: 0 errors, 1 warnings, 0 checks, 116 lines checked
ad443fa00c35 drm/i915/execlists: Explicitly reset both reg and context runtime
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Make Wa_14010229206 permanent
== Series Details == Series: drm/i915/tgl: Make Wa_14010229206 permanent URL : https://patchwork.freedesktop.org/series/75139/ State : success == Summary == CI Bug Log - changes from CI_DRM_8197 -> Patchwork_17107 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/index.html Known issues Here are the changes found in Patchwork_17107 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-skl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#656]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-skl-guc/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/fi-skl-guc/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gem_contexts: - fi-cml-s: [PASS][3] -> [DMESG-FAIL][4] ([i915#877]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cml-s/igt@i915_selftest@live@gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/fi-cml-s/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@hangcheck: - fi-icl-y: [PASS][5] -> [INCOMPLETE][6] ([fdo#108569]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-icl-y/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/fi-icl-y/igt@i915_selftest@l...@hangcheck.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 Participating hosts (44 -> 39) -- Additional (2): fi-kbl-r fi-kbl-7500u Missing(7): fi-hsw-4200u fi-byt-squawks fi-icl-guc fi-bwr-2160 fi-bsw-cyan fi-byt-n2820 fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8197 -> Patchwork_17107 CI-20190529: 20190529 CI_DRM_8197: 198bab1da198b9d6d5c36d52704dd4abab6e81a8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17107: 1ecd505ffa0483c39d25bd333b360ecea7eda96e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1ecd505ffa04 drm/i915/tgl: Make Wa_14010229206 permanent == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17107/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on
ELSP[1] promotion to idle context
URL : https://patchwork.freedesktop.org/series/75137/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8197 -> Patchwork_17105
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17105 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17105, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17105:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@execlists:
- fi-skl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-skl-guc/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-skl-guc/igt@i915_selftest@l...@execlists.html
- fi-cfl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cfl-guc/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-cfl-guc/igt@i915_selftest@l...@execlists.html
Known issues
Here are the changes found in Patchwork_17105 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-apl-guc/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-apl-guc/igt@i915_selftest@l...@execlists.html
- fi-icl-dsi: [PASS][7] -> [INCOMPLETE][8] ([i915#140])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
- fi-cml-u2: [PASS][9] -> [INCOMPLETE][10] ([i915#283])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cml-u2/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-cml-u2/igt@i915_selftest@l...@execlists.html
Possible fixes
* igt@i915_selftest@live@late_gt_pm:
- fi-bwr-2160:[INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
[i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647
Participating hosts (44 -> 35)
--
Additional (2): fi-kbl-r fi-kbl-7500u
Missing(11): fi-hsw-4770r fi-bxt-dsi fi-bdw-samus fi-bsw-n3050
fi-byt-j1900 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-kbl-7560u
fi-skl-6600u
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8197 -> Patchwork_17105
CI-20190529: 20190529
CI_DRM_8197: 198bab1da198b9d6d5c36d52704dd4abab6e81a8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17105: ad443fa00c35a13b98b4452da2be652582c3f1d5 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ad443fa00c35 drm/i915/execlists: Explicitly reset both reg and context runtime
5868edb0b7b7 drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle
context
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17105/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on
ELSP[1] promotion to idle context
URL : https://patchwork.freedesktop.org/series/75138/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d6626ef65d6d drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle
context
-:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#29:
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8,
ctl:, mode:0200}
total: 0 errors, 1 warnings, 0 checks, 126 lines checked
185b85c7368a drm/i915/execlists: Explicitly reset both reg and context runtime
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
== Series Details ==
Series: series starting with [1/2] drm/i915/execlists: Prevent GPU death on
ELSP[1] promotion to idle context
URL : https://patchwork.freedesktop.org/series/75138/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8197 -> Patchwork_17106
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/index.html
Known issues
Here are the changes found in Patchwork_17106 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-apl-guc/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-apl-guc/igt@i915_selftest@l...@execlists.html
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#140])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-icl-dsi/igt@i915_selftest@l...@execlists.html
- fi-cml-s: [PASS][5] -> [INCOMPLETE][6] ([i915#283])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cml-s/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-cml-s/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][7] -> [FAIL][8] ([i915#262])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@i915_selftest@live@late_gt_pm:
- fi-bwr-2160:[INCOMPLETE][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8197/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/fi-bwr-2160/igt@i915_selftest@live@late_gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
[i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (44 -> 41)
--
Additional (2): fi-kbl-r fi-kbl-7500u
Missing(5): fi-hsw-4770r fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8197 -> Patchwork_17106
CI-20190529: 20190529
CI_DRM_8197: 198bab1da198b9d6d5c36d52704dd4abab6e81a8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5539: e7aae12e37771a8b7796ba252574eb832a5839c3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17106: 185b85c7368afa95d0c352b09e7ac161ae19e2bc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
185b85c7368a drm/i915/execlists: Explicitly reset both reg and context runtime
d6626ef65d6d drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle
context
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17106/index.html
___
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[Intel-gfx] [PATCH] drm/i915/tgl: Make Wa_14010229206 permanent
This workaround now applies to all steppings, not just A0.
Wa_1409085225 is a temporary A0-only W/A however it is
identical to Wa_14010229206 and hence the combined workaround
is made permanent.
Bspec: 52890
Signed-off-by: Swathi Dhanavanthri
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e96cc7fa0936..c3c42cf614a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1380,12 +1380,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
- /*
-* Wa_1409085225:tgl
-* Wa_14010229206:tgl
-*/
- wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
-
/* Wa_1408615072:tgl */
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
VSUNIT_CLKGATE_DIS_TGL);
@@ -1403,6 +1397,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_masked_en(wal,
GEN9_CS_DEBUG_MODE1,
FF_DOP_CLOCK_GATE_DISABLE);
+ /*
+* Wa_1409085225:tgl
+* Wa_14010229206:tgl
+*/
+ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
}
if (IS_GEN(i915, 11)) {
--
2.20.1
___
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Re: [Intel-gfx] [PATCH] drm/i915/perf: Do not clear pollin for small user read buffers
On Thu, 26 Mar 2020 02:09:34 -0700, Lionel Landwerlin wrote:
>
> On 26/03/2020 06:43, Ashutosh Dixit wrote:
> > It is wrong to block the user thread in the next poll when OA data is
> > already available which could not fit in the user buffer provided in
> > the previous read. In several cases the exact user buffer size is not
> > known. Blocking user space in poll can lead to data loss when the
> > buffer size used is smaller than the available data.
> >
> > This change fixes this issue and allows user space to read all OA data
> > even when using a buffer size smaller than the available data using
> > multiple non-blocking reads rather than staying blocked in poll till
> > the next timer interrupt.
> >
> > v2: Fix ret value for blocking reads (Umesh)
> >
> > Cc: Umesh Nerlige Ramappa
> > Cc: Lionel Landwerlin
> > Signed-off-by: Ashutosh Dixit
> > ---
> > drivers/gpu/drm/i915/i915_perf.c | 63 ++--
> > 1 file changed, 12 insertions(+), 51 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c
> > b/drivers/gpu/drm/i915/i915_perf.c
> > index 3222f6cd8255..e2d083efba6d 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -2957,49 +2957,6 @@ void i915_oa_init_reg_state(const struct
> > intel_context *ce,
> > gen8_update_reg_state_unlocked(ce, stream);
> > }
> > -/**
> > - * i915_perf_read_locked - _perf_stream_ops->read with error
> > normalisation
> > - * @stream: An i915 perf stream
> > - * @file: An i915 perf stream file
> > - * @buf: destination buffer given by userspace
> > - * @count: the number of bytes userspace wants to read
> > - * @ppos: (inout) file seek position (unused)
> > - *
> > - * Besides wrapping _perf_stream_ops->read this provides a common
> > place to
> > - * ensure that if we've successfully copied any data then reporting that
> > takes
> > - * precedence over any internal error status, so the data isn't lost.
> > - *
> > - * For example ret will be -ENOSPC whenever there is more buffered data
> > than
> > - * can be copied to userspace, but that's only interesting if we weren't
> > able
> > - * to copy some data because it implies the userspace buffer is too small
> > to
> > - * receive a single record (and we never split records).
> > - *
> > - * Another case with ret == -EFAULT is more of a grey area since it would
> > seem
> > - * like bad form for userspace to ask us to overrun its buffer, but the
> > user
> > - * knows best:
> > - *
> > - * http://yarchive.net/comp/linux/partial_reads_writes.html
> > - *
> > - * Returns: The number of bytes copied or a negative error code on failure.
> > - */
> > -static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream,
> > -struct file *file,
> > -char __user *buf,
> > -size_t count,
> > -loff_t *ppos)
> > -{
> > - /* Note we keep the offset (aka bytes read) separate from any
> > -* error status so that the final check for whether we return
> > -* the bytes read with a higher precedence than any error (see
> > -* comment below) doesn't need to be handled/duplicated in
> > -* stream->ops->read() implementations.
> > -*/
> > - size_t offset = 0;
> > - int ret = stream->ops->read(stream, buf, count, );
> > -
> > - return offset ?: (ret ?: -EAGAIN);
> > -}
> > -
> > /**
> >* i915_perf_read - handles read() FOP for i915 perf stream FDs
> >* @file: An i915 perf stream file
> > @@ -3025,6 +2982,8 @@ static ssize_t i915_perf_read(struct file *file,
> > {
> > struct i915_perf_stream *stream = file->private_data;
> > struct i915_perf *perf = stream->perf;
> > + size_t offset = 0;
> > + int __ret;
> > ssize_t ret;
> > /* To ensure it's handled consistently we simply treat all
> > reads of
> > a
> > @@ -3048,16 +3007,19 @@ static ssize_t i915_perf_read(struct file *file,
> > return ret;
> > mutex_lock(>lock);
> > - ret = i915_perf_read_locked(stream, file,
> > - buf, count, ppos);
> > + __ret = stream->ops->read(stream, buf, count, );
> > + ret = offset ?: (__ret ?: -EAGAIN);
> > mutex_unlock(>lock);
> > } while (ret == -EAGAIN);
> > } else {
> > mutex_lock(>lock);
> > - ret = i915_perf_read_locked(stream, file, buf, count, ppos);
> > + __ret = stream->ops->read(stream, buf, count, );
> > + ret = offset ?: (__ret ?: -EAGAIN);
> > mutex_unlock(>lock);
> > }
> > + /* Possible values for __ret are 0, -EFAULT, -ENOSPC, -EAGAIN,
> > ... */
> > +
> > /* We allow the poll checking to sometimes report false positive EPOLLIN
> > * events where we might actually report EAGAIN on
Re: [Intel-gfx] [PATCH] drm/i915/perf: Do not clear pollin for small user read buffers
On Thu, 26 Mar 2020 11:02:46 -0700, Umesh Nerlige Ramappa wrote:
> On Wed, Mar 25, 2020 at 06:52:52PM -0700, Dixit, Ashutosh wrote:
> > On Wed, 25 Mar 2020 17:32:35 -0700, Umesh Nerlige Ramappa wrote:
> >>
> >> On Wed, Mar 25, 2020 at 11:20:19AM -0700, Ashutosh Dixit wrote:
> >> >
> >> > +/* Possible values for __ret are 0, -EFAULT, -ENOSPC, -EAGAIN,
> >> > ... */
> >>
> >> __ret may never be EAGAIN either (comment^). I don't see EAGAIN in the read
> >> path.
> >
> > It's here:
> >
> > gen8_append_oa_reports()
> > {
> >
> >/*
> > * An invalid tail pointer here means we're still waiting for the
> > poll
> > * hrtimer callback to give us a pointer
> > */
> >if (tail == INVALID_TAIL_PTR)
> >return -EAGAIN;
> > }
>
> Oh, you are right, EAGAIN is returned here. I was looking for it with the
> poll period patch series applied and these references are removed in that
> series.
No, you are right, since that series is likely to be merged first, it is
better to remove it from this patch.
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev3)
== Series Details ==
Series: SAGV support for Gen12+ (rev3)
URL : https://patchwork.freedesktop.org/series/75129/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ad8810ff373a drm/i915: Start passing latency as parameter
930754956920 drm/i915: Eliminate magic numbers "0" and "1" from color plane
-:118: WARNING:LONG_LINE: line over 100 characters
#118: FILE: drivers/gpu/drm/i915/intel_pm.c:4541:
+ rate = skl_plane_relative_data_rate(crtc_state,
plane_state, COLOR_PLANE_UV);
total: 0 errors, 1 warnings, 0 checks, 163 lines checked
b76321aa6824 drm/i915: Introduce skl_plane_wm_level accessor.
9cd6396bdbd9 drm/i915: Add intel_atomic_get_bw_*_state helpers
345239c1e284 drm/i915: Extract gen specific functions from intel_can_enable_sagv
37f392cf14b8 drm/i915: Add proper SAGV support for TGL+
-:234: WARNING:BRACES: braces {} are not necessary for single statement blocks
#234: FILE: drivers/gpu/drm/i915/display/intel_display.c:15662:
+ if (bw_state && state->modeset &&
intel_can_enable_sagv(bw_state)) {
+ intel_enable_sagv(dev_priv);
+ }
-:341: WARNING:BRACES: braces {} are not necessary for any arm of this statement
#341: FILE: drivers/gpu/drm/i915/intel_pm.c:3874:
+ if (INTEL_GEN(dev_priv) >= 12) {
[...]
+ } else if (INTEL_GEN(dev_priv) >= 11) {
[...]
+ } else {
[...]
total: 0 errors, 2 warnings, 0 checks, 480 lines checked
5ac95b3960a7 drm/i915: Added required new PCode commands
7ddef9fc5a42 drm/i915: Rename bw_state to new_bw_state
9ab9d139acd7 drm/i915: Restrict qgv points which don't have enough bandwidth.
17b1ab4ef65f drm/i915: Enable SAGV support for Gen12
___
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Re: [Intel-gfx] [PATCH] drm/i915/display: Trigger Modeset at boot for audio codec init
> -Original Message-
> From: Khor, Swee Aun
> Sent: Tuesday, March 24, 2020 11:26 AM
> To: Ville Syrjälä ; Shankar, Uma
>
> Cc: Souza, Jose ; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/display: Trigger Modeset at boot
> for audio
> codec init
>
> Git diff without debug print. Please review. Thanks.
Will send this as a separate patch as this commit header doesn't hold good now.
Please review the change here: https://patchwork.freedesktop.org/series/75106/
Thanks Ville, Maarten and Jose for all your inputs. Thanks SweeAun for trying
this at your end
and confirming the change suggested by Ville works to resolve audio codec
issues.
Regards,
Uma Shankar
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4d1634ed6a1b..806cf622fb39 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14108,11 +14108,13 @@ static int intel_atomic_check(struct drm_device
> *dev,
> int ret, i;
> bool any_ms = false;
>
> +
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - if (new_crtc_state->hw.mode.private_flags !=
> - old_crtc_state->hw.mode.private_flags)
> +
> + if (new_crtc_state->uapi.mode.private_flags !=
> + old_crtc_state->uapi.mode.private_flags)
> new_crtc_state->uapi.mode_changed = true;
> }
>
> Regards,
> SweeAun
>
> -Original Message-
> From: Khor, Swee Aun
> Sent: Monday, March 23, 2020 10:29 PM
> To: 'Ville Syrjälä' ; Shankar, Uma
>
> Cc: Souza, Jose ; 'intel-gfx@lists.freedesktop.org'
> g...@lists.freedesktop.org>
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/display: Trigger Modeset at boot
> for audio
> codec init
>
> Hi Ville,
>
> You are right, your suggestion will fix this issue.
>
> #Based on dmesg log, uapi mode private flags change is captured ...
> [ 11.404578] fbcon: i915drmfb (fb0) is primary device
> [ 11.404743] [drm] SA: intel_atomic_check: uapi change
> [ 11.404744] [drm] SA2: intel_atomic_check: new_crtc_state-
> >uapi.mode.private_flags= 0, old_crtc_state->uapi.mode.private_flags= 1
> [ 11.404744] [drm] SA2: intel_atomic_check: new_crtc_state-
> >uapi.mode.private_flags= 0, old_crtc_state->uapi.mode.private_flags= 0
> [ 11.404745] [drm] SA2: intel_atomic_check: new_crtc_state-
> >uapi.mode.private_flags= 0, old_crtc_state->uapi.mode.private_flags= 0
> [ 11.404799] [drm:intel_atomic_check [i915]] [CONNECTOR:110:HDMI-A-2]
> Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max
> platform
> bpp 36
> [ 11.404855] [drm:intel_hdmi_compute_config [i915]] picking 8 bpc for HDMI
> output (pipe bpp: 24)
> [ 11.404898] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24,
> dithering: 0
> ...
>
> #Here is the git diff
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4d1634ed6a1b..b5c56cd513d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14108,11 +14108,15 @@ static int intel_atomic_check(struct drm_device
> *dev, int ret, i; bool any_ms = false;
>
> +DRM_INFO("SA: intel_atomic_check: uapi change \n");
> +
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> -if (new_crtc_state->hw.mode.private_flags !=
> -old_crtc_state->hw.mode.private_flags)
> +
> +DRM_INFO("SA2: intel_atomic_check:
> +new_crtc_state->uapi.mode.private_flags= %d, old_crtc_state-
> >uapi.mode.private_flags= %d \n", new_crtc_state->uapi.mode.private_flags,
> old_crtc_state->uapi.mode.private_flags ); if (new_crtc_state-
> >uapi.mode.private_flags !=
> +old_crtc_state->uapi.mode.private_flags)
> new_crtc_state->uapi.mode_changed = true; }
>
> Regards,
> SweeAun
>
> -Original Message-
> From: Khor, Swee Aun
> Sent: Saturday, March 21, 2020 12:55 AM
> To: Ville Syrjälä ; Shankar, Uma
>
> Cc: Souza, Jose ; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/display: Trigger Modeset at boot
> for audio
> codec init
>
> Hi Ville,
> You means this change right? Sure. Will try your suggestion as well.
> By the way, what is different between hw.mode and uapi.mode and how we know
> which to be used? It used to only base.mode before hw/uapi split patches.
>
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14671,8 +14671,8 @@ static int intel_atomic_check(struct drm_device
> > *dev,
> > /* Catch I915_MODE_FLAG_INHERITED */
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> >
Re: [Intel-gfx] [PATCH v2 09/16] drm/i915: remove always-defined CONFIG_AS_MOVNTDQA
On Thu, 26 Mar 2020, Masahiro Yamada wrote:
> CONFIG_AS_MOVNTDQA was introduced by commit 0b1de5d58e19 ("drm/i915:
> Use SSE4.1 movntdqa to accelerate reads from WC memory").
>
> We raise the minimal supported binutils version from time to time.
> The last bump was commit 1fb12b35e5ff ("kbuild: Raise the minimum
> required binutils version to 2.21").
>
> I confirmed the code in $(call as-instr,...) can be assembled by the
> binutils 2.21 assembler and also by LLVM integrated assembler.
>
> Remove CONFIG_AS_MOVNTDQA, which is always defined.
>
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Nick Desaulniers
Ack for merging this via whichever tree you see fit; please let me know
if you want me to pick this up via drm-intel.
BR,
Jani.
> ---
>
> Changes in v2: None
>
> drivers/gpu/drm/i915/Makefile | 3 ---
> drivers/gpu/drm/i915/i915_memcpy.c | 5 -
> 2 files changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index a1f2411aa21b..e559e53fc634 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -28,9 +28,6 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
> CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
> CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
>
> -subdir-ccflags-y += \
> - $(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
> -
> subdir-ccflags-y += -I$(srctree)/$(src)
>
> # Please keep these build lists sorted!
> diff --git a/drivers/gpu/drm/i915/i915_memcpy.c
> b/drivers/gpu/drm/i915/i915_memcpy.c
> index fdd550405fd3..7b3b83bd5ab8 100644
> --- a/drivers/gpu/drm/i915/i915_memcpy.c
> +++ b/drivers/gpu/drm/i915/i915_memcpy.c
> @@ -35,7 +35,6 @@
>
> static DEFINE_STATIC_KEY_FALSE(has_movntdqa);
>
> -#ifdef CONFIG_AS_MOVNTDQA
> static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len)
> {
> kernel_fpu_begin();
> @@ -93,10 +92,6 @@ static void __memcpy_ntdqu(void *dst, const void *src,
> unsigned long len)
>
> kernel_fpu_end();
> }
> -#else
> -static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len) {}
> -static void __memcpy_ntdqu(void *dst, const void *src, unsigned long len) {}
> -#endif
>
> /**
> * i915_memcpy_from_wc: perform an accelerated *aligned* read from WC
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Remove useless but deadly local
== Series Details ==
Series: drm/i915/display: Remove useless but deadly local
URL : https://patchwork.freedesktop.org/series/75109/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8190 -> Patchwork_17094
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/index.html
Known issues
Here are the changes found in Patchwork_17094 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#108569])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-cml-u2: [PASS][3] -> [DMESG-WARN][4] ([IGT#4])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/fi-cml-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/fi-cml-u2/igt@kms_chamel...@common-hpd-after-suspend.html
Possible fixes
* igt@i915_selftest@live@execlists:
- {fi-tgl-u}: [DMESG-FAIL][5] ([i915#656]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/fi-tgl-u/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/fi-tgl-u/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (40 -> 41)
--
Additional (9): fi-glk-dsi fi-ilk-650 fi-gdg-551 fi-ivb-3770 fi-elk-e7500
fi-bsw-kefka fi-blb-e6850 fi-bsw-nick fi-snb-2600
Missing(8): fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-cfl-8109u fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8190 -> Patchwork_17094
CI-20190529: 20190529
CI_DRM_8190: 73f711b364bc85c8a7189487c09431eb1f515ed0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5538: 47becbc9cd1fc7b1b78692f90fd3dcd5a9066965 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17094: 007816da9e131891dace85d46c9bcc3c2ce4deac @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
007816da9e13 drm/i915/display: Remove useless but deadly local
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/index.html
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Re: [Intel-gfx] [PATCH] drm/i915: Drop final few uses of drm_i915_private.engine
On 25/03/2020 23:48, Chris Wilson wrote:
We've migrated all the heavy users over to the intel_gt, and can finally
drop the last few users and with that the mirror in dev_priv->engine[].
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Andi Shyti
---
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
.../gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4
drivers/gpu/drm/i915/i915_drv.h| 1 -
drivers/gpu/drm/i915/i915_irq.c| 8
drivers/gpu/drm/i915/selftests/i915_request.c | 14 ++
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 6 +++---
7 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 481187223101..6e1d66323223 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -1342,7 +1342,7 @@ void intel_overlay_setup(struct drm_i915_private
*dev_priv)
if (!HAS_OVERLAY(dev_priv))
return;
- engine = dev_priv->engine[RCS0];
+ engine = dev_priv->gt.engine[RCS0];
if (!engine || !engine->kernel_context)
return;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 54b86cf7f5d2..f4f933240b39 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1925,7 +1925,7 @@ static int mock_context_barrier(void *arg)
goto out;
}
- rq = igt_request_alloc(ctx, i915->engine[RCS0]);
+ rq = igt_request_alloc(ctx, i915->gt.engine[RCS0]);
if (IS_ERR(rq)) {
pr_err("Request allocation failed!\n");
goto out;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3aa8a652c16d..dff0bbe9e1a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -347,8 +347,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
gt->engine_class[info->class][info->instance] = engine;
gt->engine[id] = engine;
- i915->engine[id] = engine;
-
return 0;
}
@@ -425,8 +423,6 @@ void intel_engines_release(struct intel_gt *gt)
engine->release = NULL;
memset(>reset, 0, sizeof(engine->reset));
-
- gt->i915->engine[id] = NULL;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9bcea97c39de..b09a1c929c94 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -884,7 +884,6 @@ struct drm_i915_private {
struct pci_dev *bridge_dev;
- struct intel_engine_cs *engine[I915_NUM_ENGINES];
struct rb_root uabi_engines;
struct resource mch_res;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9f0653cf0510..1502ab44f1a5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3658,7 +3658,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
intel_uncore_write16(_priv->uncore, GEN2_IIR, iir);
if (iir & I915_USER_INTERRUPT)
- intel_engine_signal_breadcrumbs(dev_priv->engine[RCS0]);
+
intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
if (iir & I915_MASTER_ERROR_INTERRUPT)
i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
@@ -3763,7 +3763,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
I915_WRITE(GEN2_IIR, iir);
if (iir & I915_USER_INTERRUPT)
- intel_engine_signal_breadcrumbs(dev_priv->engine[RCS0]);
+
intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
if (iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
@@ -3905,10 +3905,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
I915_WRITE(GEN2_IIR, iir);
if (iir & I915_USER_INTERRUPT)
- intel_engine_signal_breadcrumbs(dev_priv->engine[RCS0]);
+
intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
if (iir & I915_BSD_USER_INTERRUPT)
- intel_engine_signal_breadcrumbs(dev_priv->engine[VCS0]);
+
intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
if (iir & I915_MASTER_ERROR_INTERRUPT)
i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 7ac9616de9d8..1dab0360f76a 100644
---
[Intel-gfx] [PATCH] drm/i915/display: Fix mode private_flags comparison at atomic_check
This patch fixes the private_flags of mode to be checked and
compared against uapi.mode and not from hw.mode. This helps
properly trigger modeset at boot if desired by driver.
It helps resolve audio_codec initialization issues if display
is connected at boot. Initial discussion on this issue has happened
on below thread:
https://patchwork.freedesktop.org/series/74828/
Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1363
Cc: Ville Syrjä
Cc: Maarten Lankhorst
Cc: Kai Vehmanen
Cc: Souza, Jose
Suggested-by: Ville Syrjä
Signed-off-by: Uma Shankar
Signed-off-by: SweeAun Khor
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fe55c7c713f1..e630429af2c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device *dev,
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (new_crtc_state->hw.mode.private_flags !=
- old_crtc_state->hw.mode.private_flags)
+ if (new_crtc_state->uapi.mode.private_flags !=
+ old_crtc_state->uapi.mode.private_flags)
new_crtc_state->uapi.mode_changed = true;
}
--
2.22.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Fix mode private_flags comparison at atomic_check
== Series Details ==
Series: drm/i915/display: Fix mode private_flags comparison at atomic_check
URL : https://patchwork.freedesktop.org/series/75106/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8190 -> Patchwork_17093
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/index.html
Known issues
Here are the changes found in Patchwork_17093 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] /
[i915#1430] / [i915#656])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html
Possible fixes
* igt@i915_selftest@live@execlists:
- {fi-tgl-u}: [DMESG-FAIL][3] ([i915#656]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/fi-tgl-u/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/fi-tgl-u/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-icl-u2: [INCOMPLETE][5] ([fdo#108569]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[i915#1430]: https://gitlab.freedesktop.org/drm/intel/issues/1430
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (40 -> 37)
--
Additional (8): fi-glk-dsi fi-ilk-650 fi-ivb-3770 fi-elk-e7500 fi-bsw-kefka
fi-blb-e6850 fi-bsw-nick fi-snb-2600
Missing(11): fi-bdw-5557u fi-hsw-4200u fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-hsw-4770 fi-cfl-8109u fi-kbl-7560u fi-byt-clapper
fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8190 -> Patchwork_17093
CI-20190529: 20190529
CI_DRM_8190: 73f711b364bc85c8a7189487c09431eb1f515ed0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5538: 47becbc9cd1fc7b1b78692f90fd3dcd5a9066965 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17093: c8956fda0a604ceb7e6400886acc9019ab4142e0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c8956fda0a60 drm/i915/display: Fix mode private_flags comparison at atomic_check
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/index.html
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Re: [Intel-gfx] [PATCH] drm/i915/display: Remove useless but deadly local
On Thu, 26 Mar 2020, Chris Wilson wrote:
> Beware dereferencing the NULL pointer prior to checking for its
> existence.
Huh, I don't see the failure mode. Please enlighten me.
BR,
Jani.
>
> Fixes: 419190429cd1 ("drm/i915/hdmi: use struct drm_device based logging")
> Signed-off-by: Chris Wilson
> Cc: Wambui Karuga
> Cc: Jani Nikula
> Cc: "Ville Syrjälä"
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 395dc192baa0..0076abc63851 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -691,7 +691,6 @@ void intel_read_infoframe(struct intel_encoder *encoder,
> union hdmi_infoframe *frame)
> {
> struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
> u8 buffer[VIDEO_DIP_DATA_SIZE];
> int ret;
>
> @@ -708,13 +707,13 @@ void intel_read_infoframe(struct intel_encoder *encoder,
> /* see comment above for the reason for this offset */
> ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
> if (ret) {
> - drm_dbg_kms(>drm,
> + drm_dbg_kms(encoder->base.dev,
> "Failed to unpack infoframe type 0x%02x\n", type);
> return;
> }
>
> if (frame->any.type != type)
> - drm_dbg_kms(>drm,
> + drm_dbg_kms(encoder->base.dev,
> "Found the wrong infoframe type 0x%x (expected
> 0x%02x)\n",
> frame->any.type, type);
> }
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Fix mode private_flags comparison at atomic_check
== Series Details == Series: drm/i915/display: Fix mode private_flags comparison at atomic_check URL : https://patchwork.freedesktop.org/series/75106/ State : success == Summary == CI Bug Log - changes from CI_DRM_8190_full -> Patchwork_17093_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17093_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-apl2/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-apl1/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb1/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@implicit-read-write-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [i915#677]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb4/igt@gem_exec_sched...@implicit-read-write-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-iclb8/igt@gem_exec_sched...@implicit-read-write-bsd1.html * igt@gem_exec_schedule@implicit-write-read-blt: - shard-snb: [PASS][7] -> [INCOMPLETE][8] ([i915#82]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-snb6/igt@gem_exec_sched...@implicit-write-read-blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-snb2/igt@gem_exec_sched...@implicit-write-read-blt.html * igt@gem_exec_schedule@pi-shared-iova-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb3/igt@gem_exec_sched...@pi-shared-iova-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-iclb4/igt@gem_exec_sched...@pi-shared-iova-bsd.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb6/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-iclb1/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180] / [i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-kbl4/igt@gem_exec_susp...@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-kbl2/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@execlists: - shard-apl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103927] / [i915#1430] / [i915#656]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-apl7/igt@i915_selftest@l...@execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-apl7/igt@i915_selftest@l...@execlists.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#72]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-skl: [PASS][19] -> [FAIL][20] ([IGT#5]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl7/igt@kms_cursor_leg...@flip-vs-cursor-busy-crc-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-skl3/igt@kms_cursor_leg...@flip-vs-cursor-busy-crc-legacy.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#46]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17093/shard-skl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#34]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl9/igt@kms_f...@plain-flip-fb-recreate-interruptible.html [24]:
[Intel-gfx] [PATCH] drm/i915/display: Remove useless but deadly local
Beware dereferencing the NULL pointer prior to checking for its
existence.
Fixes: 419190429cd1 ("drm/i915/hdmi: use struct drm_device based logging")
Signed-off-by: Chris Wilson
Cc: Wambui Karuga
Cc: Jani Nikula
Cc: "Ville Syrjälä"
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 395dc192baa0..0076abc63851 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -691,7 +691,6 @@ void intel_read_infoframe(struct intel_encoder *encoder,
union hdmi_infoframe *frame)
{
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
- struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
u8 buffer[VIDEO_DIP_DATA_SIZE];
int ret;
@@ -708,13 +707,13 @@ void intel_read_infoframe(struct intel_encoder *encoder,
/* see comment above for the reason for this offset */
ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
if (ret) {
- drm_dbg_kms(>drm,
+ drm_dbg_kms(encoder->base.dev,
"Failed to unpack infoframe type 0x%02x\n", type);
return;
}
if (frame->any.type != type)
- drm_dbg_kms(>drm,
+ drm_dbg_kms(encoder->base.dev,
"Found the wrong infoframe type 0x%x (expected
0x%02x)\n",
frame->any.type, type);
}
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915/perf: Do not clear pollin for small user read buffers
On 26/03/2020 06:43, Ashutosh Dixit wrote:
It is wrong to block the user thread in the next poll when OA data is
already available which could not fit in the user buffer provided in
the previous read. In several cases the exact user buffer size is not
known. Blocking user space in poll can lead to data loss when the
buffer size used is smaller than the available data.
This change fixes this issue and allows user space to read all OA data
even when using a buffer size smaller than the available data using
multiple non-blocking reads rather than staying blocked in poll till
the next timer interrupt.
v2: Fix ret value for blocking reads (Umesh)
Cc: Umesh Nerlige Ramappa
Cc: Lionel Landwerlin
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 63 ++--
1 file changed, 12 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 3222f6cd8255..e2d083efba6d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2957,49 +2957,6 @@ void i915_oa_init_reg_state(const struct intel_context
*ce,
gen8_update_reg_state_unlocked(ce, stream);
}
-/**
- * i915_perf_read_locked - _perf_stream_ops->read with error normalisation
- * @stream: An i915 perf stream
- * @file: An i915 perf stream file
- * @buf: destination buffer given by userspace
- * @count: the number of bytes userspace wants to read
- * @ppos: (inout) file seek position (unused)
- *
- * Besides wrapping _perf_stream_ops->read this provides a common place to
- * ensure that if we've successfully copied any data then reporting that takes
- * precedence over any internal error status, so the data isn't lost.
- *
- * For example ret will be -ENOSPC whenever there is more buffered data than
- * can be copied to userspace, but that's only interesting if we weren't able
- * to copy some data because it implies the userspace buffer is too small to
- * receive a single record (and we never split records).
- *
- * Another case with ret == -EFAULT is more of a grey area since it would seem
- * like bad form for userspace to ask us to overrun its buffer, but the user
- * knows best:
- *
- * http://yarchive.net/comp/linux/partial_reads_writes.html
- *
- * Returns: The number of bytes copied or a negative error code on failure.
- */
-static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream,
-struct file *file,
-char __user *buf,
-size_t count,
-loff_t *ppos)
-{
- /* Note we keep the offset (aka bytes read) separate from any
-* error status so that the final check for whether we return
-* the bytes read with a higher precedence than any error (see
-* comment below) doesn't need to be handled/duplicated in
-* stream->ops->read() implementations.
-*/
- size_t offset = 0;
- int ret = stream->ops->read(stream, buf, count, );
-
- return offset ?: (ret ?: -EAGAIN);
-}
-
/**
* i915_perf_read - handles read() FOP for i915 perf stream FDs
* @file: An i915 perf stream file
@@ -3025,6 +2982,8 @@ static ssize_t i915_perf_read(struct file *file,
{
struct i915_perf_stream *stream = file->private_data;
struct i915_perf *perf = stream->perf;
+ size_t offset = 0;
+ int __ret;
ssize_t ret;
/* To ensure it's handled consistently we simply treat all reads of a
@@ -3048,16 +3007,19 @@ static ssize_t i915_perf_read(struct file *file,
return ret;
mutex_lock(>lock);
- ret = i915_perf_read_locked(stream, file,
- buf, count, ppos);
+ __ret = stream->ops->read(stream, buf, count, );
+ ret = offset ?: (__ret ?: -EAGAIN);
mutex_unlock(>lock);
} while (ret == -EAGAIN);
} else {
mutex_lock(>lock);
- ret = i915_perf_read_locked(stream, file, buf, count, ppos);
+ __ret = stream->ops->read(stream, buf, count, );
+ ret = offset ?: (__ret ?: -EAGAIN);
mutex_unlock(>lock);
}
+ /* Possible values for __ret are 0, -EFAULT, -ENOSPC, -EAGAIN, ... */
+
/* We allow the poll checking to sometimes report false positive EPOLLIN
* events where we might actually report EAGAIN on read() if there's
* not really any data available. In this situation though we don't
@@ -3065,13 +3027,12 @@ static ssize_t i915_perf_read(struct file *file,
* and read() returning -EAGAIN. Clearing the oa.pollin state here
* effectively ensures we back off until the next hrtimer callback
* before reporting another EPOLLIN event.
+* The exception to this is if
Re: [Intel-gfx] [PATCH 00/16] x86, crypto: remove always-defined CONFIG_AS_* and cosolidate Kconfig/Makefiles
* Masahiro Yamada wrote:
> > LGTM. I've got these four from Jason A. Donenfeld queued up in
> > tip:WIP.x86/asm:
> >
> > bd5b1283e41c: ("crypto: Curve25519 - do not pollute dispatcher based on
> > assembler")
> > 829f32d78588: ("crypto: X86 - rework configuration, based on Kconfig")
> > 95ef9f80ed63: ("x86/build: Probe assembler from Kconfig instead of Kbuild")
> > 1651e700664b: ("x86: Fix bitops.h warning with a moved cast")
> >
> > I suppose these might interact (maybe even conflict), and are topically
> > related.
> >
> > Would you like to pull these into the kbuild tree? You can find them in:
> >
> >git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WIP.x86/asm
> >
> > Thanks,
> >
> > Ingo
>
>
> I did not know that these had already landed in tip tree.
>
> They are immature version.
> (In fact CONFIG_AS_CFI and AS_ADX are false-negative
> if GCC that defaults to 32-bit is used.)
>
> Can you simply discard the WIP.x86/asm branch,
> and only reapply
> 1651e700664b: ("x86: Fix bitops.h warning with a moved cast")
>
> ?
Sure, done!
In case you need any x86 maintainer acks for your series:
Acked-by: Ingo Molnar
Thanks,
Ingo
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Re: [Intel-gfx] [PATCH v2 00/16] x86, crypto: remove always-defined CONFIG_AS_* and cosolidate Kconfig/Makefiles
* Jason A. Donenfeld wrote: > Very little has changed from last time, and this whole series still > looks good to me. I think I already ack'd most packages, but in case > it helps: > > Reviewed-by: Jason A. Donenfeld Acked-by: Ingo Molnar > Since this touches a lot of stuff, it might be best to get it in as > early as possible during the merge window, as I imagine new code being > added is going to want to be touching those makefiles too. I'd argue the opposite: please merge this later in the merge window, to not disrupt the vast body of other stuff that has already been lined up and has been tested, and to give time for these new bits to get tested some more. Also, please get it into -next ASAP, today would be ideal for test coverage ... Thanks, Ingo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Remove useless but deadly local
== Series Details == Series: drm/i915/display: Remove useless but deadly local URL : https://patchwork.freedesktop.org/series/75109/ State : success == Summary == CI Bug Log - changes from CI_DRM_8190_full -> Patchwork_17094_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17094_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb1/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@implicit-read-write-bsd1: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [i915#677]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb4/igt@gem_exec_sched...@implicit-read-write-bsd1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-iclb7/igt@gem_exec_sched...@implicit-read-write-bsd1.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112146]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb3/igt@gem_exec_sched...@in-order-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-iclb4/igt@gem_exec_sched...@in-order-bsd.html * igt@gem_exec_schedule@pi-shared-iova-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb3/igt@gem_exec_sched...@pi-shared-iova-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-iclb2/igt@gem_exec_sched...@pi-shared-iova-bsd.html * igt@i915_suspend@forcewake: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#69]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl9/igt@i915_susp...@forcewake.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-skl2/igt@i915_susp...@forcewake.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#79]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl6/igt@kms_f...@flip-vs-expired-vblank.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-skl3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-apl3/igt@kms_f...@flip-vs-suspend-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-apl6/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl4/igt@kms_...@bpc-switch.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-skl6/igt@kms_...@bpc-switch.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#899]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-glk7/igt@kms_plane_low...@pipe-a-tiling-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-glk6/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_prime@basic-crc: - shard-apl: [PASS][21] -> [FAIL][22] ([i915#1031] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-apl4/igt@kms_pr...@basic-crc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-apl8/igt@kms_pr...@basic-crc.html - shard-kbl: [PASS][23] -> [FAIL][24] ([i915#1031] / [i915#93] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-kbl7/igt@kms_pr...@basic-crc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-kbl1/igt@kms_pr...@basic-crc.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8190/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17094/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html *
[Intel-gfx] [PATCH] drm:i915:display: add checks for Gen9 devices with hdr capability
this patch adds hdr capabilities checks for Gen9 devices with
lspcon support.
Signed-off-by: Vipin Anand
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 17 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 9 +++--
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 9ae2f88cc925..70d0d76ed606 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -833,9 +833,12 @@ intel_hdmi_compute_drm_infoframe(struct intel_encoder
*encoder,
{
struct hdmi_drm_infoframe *frame = _state->infoframes.drm.drm;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
int ret;
- if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
+ if (!(INTEL_GEN(dev_priv) >= 10 ||
+ (((INTEL_GEN(dev_priv) >= 9)) &&
+ intel_dig_port->lspcon.active)))
return true;
if (!crtc_state->has_infoframe)
@@ -2102,9 +2105,12 @@ static int intel_hdmi_source_max_tmds_clock(struct
intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
const struct ddi_vbt_port_info *info =
_priv->vbt.ddi_port_info[encoder->port];
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
int max_tmds_clock;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 10 ||
+ (((INTEL_GEN(dev_priv) >= 9)) &&
+intel_dig_port->lspcon.active))
max_tmds_clock = 594000;
else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
max_tmds_clock = 30;
@@ -2423,6 +2429,7 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
int ret;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -2469,7 +2476,8 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
pipe_config->lane_count = 4;
if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
- IS_GEMINILAKE(dev_priv))) {
+ (((INTEL_GEN(dev_priv) >= 9)) &&
+ intel_dig_port->lspcon.active))) {
if (scdc->scrambling.low_rates)
pipe_config->hdmi_scrambling = true;
@@ -3171,7 +3179,8 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
connector->doublescan_allowed = 0;
connector->stereo_allowed = 1;
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 10 ||
+ (((INTEL_GEN(dev_priv) >= 9)) && intel_dig_port->lspcon.active))
connector->ycbcr_420_allowed = true;
intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 5cede4f07f22..be074acd74f3 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -116,6 +116,8 @@ static bool lspcon_detect_hdr_capability(struct
intel_lspcon *lspcon)
if (lspcon->vendor == LSPCON_VENDOR_MCA)
ret = drm_dp_dpcd_read(>aux, DPCD_MCA_LSPCON_HDR_STATUS,
_caps, 1);
+ else if (lspcon->vendor == LSPCON_VENDOR_PARADE)
+ return true;
else
return false;
@@ -474,7 +476,8 @@ void lspcon_write_infoframe(struct intel_encoder *encoder,
* Todo: Add support for Parade later
*/
if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
- lspcon->vendor != LSPCON_VENDOR_MCA)
+ (lspcon->vendor != LSPCON_VENDOR_MCA ||
+lspcon->vendor != LSPCON_VENDOR_PARADE))
return;
if (lspcon->vendor == LSPCON_VENDOR_MCA) {
@@ -646,7 +649,9 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
return false;
}
- if (lspcon->vendor == LSPCON_VENDOR_MCA && lspcon->hdr_supported)
+ if ((lspcon->vendor == LSPCON_VENDOR_MCA ||
+lspcon->vendor == LSPCON_VENDOR_PARADE) &&
+lspcon->hdr_supported)
drm_object_attach_property(>base,
connector->dev->mode_config.hdr_output_metadata_property,
0);
--
2.26.0
[Intel-gfx] [v2] drm/i915/display: Fix mode private_flags comparison at atomic_check
This patch fixes the private_flags of mode to be checked and
compared against uapi.mode and not from hw.mode. This helps
properly trigger modeset at boot if desired by driver.
It helps resolve audio_codec initialization issues if display
is connected at boot. Initial discussion on this issue has happened
on below thread:
https://patchwork.freedesktop.org/series/74828/
v2: No functional change. Fixed the Closes tag and added
Maarten's RB.
Cc: Ville Syrjä
Cc: Maarten Lankhorst
Cc: Kai Vehmanen
Cc: Souza, Jose
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1363
Suggested-by: Ville Syrjä
Signed-off-by: Uma Shankar
Signed-off-by: SweeAun Khor
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fe55c7c713f1..e630429af2c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device *dev,
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (new_crtc_state->hw.mode.private_flags !=
- old_crtc_state->hw.mode.private_flags)
+ if (new_crtc_state->uapi.mode.private_flags !=
+ old_crtc_state->uapi.mode.private_flags)
new_crtc_state->uapi.mode_changed = true;
}
--
2.22.0
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Re: [Intel-gfx] [v2] drm/i915/display: Fix mode private_flags comparison at atomic_check
> -Original Message-
> From: Maarten Lankhorst
> Sent: Thursday, March 26, 2020 5:38 PM
> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjä ; Kai Vehmanen
> ; Souza, Jose ; Khor, Swee
> Aun
> Subject: Re: [v2] drm/i915/display: Fix mode private_flags comparison at
> atomic_check
>
> Op 26-03-2020 om 13:24 schreef Uma Shankar:
> > This patch fixes the private_flags of mode to be checked and compared
> > against uapi.mode and not from hw.mode. This helps properly trigger
> > modeset at boot if desired by driver.
> >
> > It helps resolve audio_codec initialization issues if display is
> > connected at boot. Initial discussion on this issue has happened on
> > below thread:
> > https://patchwork.freedesktop.org/series/74828/
> >
> > v2: No functional change. Fixed the Closes tag and added Maarten's RB.
> >
> > Cc: Ville Syrjä
> > Cc: Maarten Lankhorst
> > Cc: Kai Vehmanen
> > Cc: Souza, Jose
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1363
> > Suggested-by: Ville Syrjä
> > Signed-off-by: Uma Shankar
> > Signed-off-by: SweeAun Khor
> > Reviewed-by: Maarten Lankhorst
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index fe55c7c713f1..e630429af2c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device
> > *dev,
> > /* Catch I915_MODE_FLAG_INHERITED */
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > - if (new_crtc_state->hw.mode.private_flags !=
> > - old_crtc_state->hw.mode.private_flags)
> > + if (new_crtc_state->uapi.mode.private_flags !=
> > + old_crtc_state->uapi.mode.private_flags)
> > new_crtc_state->uapi.mode_changed = true;
> > }
> >
>
> Still missing the fixes tags!
My Bad, updated.
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[Intel-gfx] [v3] drm/i915/display: Fix mode private_flags comparison at atomic_check
This patch fixes the private_flags of mode to be checked and
compared against uapi.mode and not from hw.mode. This helps
properly trigger modeset at boot if desired by driver.
It helps resolve audio_codec initialization issues if display
is connected at boot. Initial discussion on this issue has happened
on below thread:
https://patchwork.freedesktop.org/series/74828/
v2: No functional change. Fixed the Closes tag and added
Maarten's RB.
v3: Added Fixes tag.
Cc: Ville Syrjä
Cc: Maarten Lankhorst
Cc: Kai Vehmanen
Cc: Souza, Jose
Fixes: 58d124ea2739 ("drm/i915: Complete crtc hw/uapi split, v6.")
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1363
Suggested-by: Ville Syrjä
Signed-off-by: Uma Shankar
Signed-off-by: SweeAun Khor
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fe55c7c713f1..e630429af2c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device *dev,
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (new_crtc_state->hw.mode.private_flags !=
- old_crtc_state->hw.mode.private_flags)
+ if (new_crtc_state->uapi.mode.private_flags !=
+ old_crtc_state->uapi.mode.private_flags)
new_crtc_state->uapi.mode_changed = true;
}
--
2.22.0
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Re: [Intel-gfx] [PATCH] drm/i915/display: Remove useless but deadly local
On Thu, 26 Mar 2020, Chris Wilson wrote: > Beware dereferencing the NULL pointer prior to checking for its > existence. Okay, so the crt code calls ddi functions, and enc_to_dig_port() will return NULL. Backtrace for posterity below, copy-pasted from logs Chris pointed me at. I think alternatively we could just use to_i915(encoder->base.dev) here instead of accessing intel_dig_port, but the patch at hand fixes stuff, Reviewed-by: Jani Nikula Some other observations: As we're moving further and further away from crt, I don't think people expect the intel_ddi_* functions to be called directly from crt code, or any code where the encoder is *not* a digital port. And that brings us to another case where enc_to_dig_port() will return NULL: INTEL_OUTPUT_DP_MST. We rarely check for enc_to_dig_port() being NULL anywhere. There's probably more subtle bugs waiting to happen here and there. BR, Jani. <1>[3.324694] BUG: kernel NULL pointer dereference, address: <1>[3.324696] #PF: supervisor read access in kernel mode <4>[3.324704] hardirqs last enabled at (751): [] d_lookup+0x57/0xa0 <1>[3.324709] #PF: error_code(0x) - not-present page <4>[3.324716] hardirqs last disabled at (752): [] __slab_alloc.isra.89.constprop.94+0x19/0x70 <4>[3.324720] softirqs last enabled at (402): [] __do_softirq+0x385/0x47f <6>[3.324725] PGD 0 P4D 0 <4>[3.324733] softirqs last disabled at (395): [] irq_exit+0xba/0xc0 <4>[3.324762] Oops: [#1] PREEMPT SMP PTI <4>[3.324768] CPU: 0 PID: 380 Comm: systemd-udevd Not tainted 5.6.0-rc7-CI-CI_DRM_8189+ #1 <4>[3.324776] Hardware name: MSI MS-7924/Z97M-G43(MS-7924), BIOS V1.12 02/15/2016 <4>[3.324840] RIP: 0010:intel_read_infoframe+0x3a/0x170 [i915] <4>[3.324848] Code: 65 48 8b 04 25 28 00 00 00 48 89 44 24 20 31 c0 83 f9 0a 77 12 ba 01 00 00 00 48 d3 e2 f7 c2 c0 05 00 00 48 0f 45 c7 83 fb 03 <4c> 8b 20 0f 84 f2 00 00 00 83 fb 0a 0f 84 f3 00 00 00 83 fb 07 0f <4>[3.324865] RSP: 0018:c95438b0 EFLAGS: 00010212 <4>[3.324871] RAX: RBX: 0082 RCX: 0001 <4>[3.324879] RDX: 0002 RSI: 8883f8309000 RDI: 8883f80cbe00 <4>[3.324887] RBP: 8883f8309b34 R08: 000e R09: 0001 <4>[3.324894] R10: R11: R12: 8883f7ac <4>[3.324901] R13: 8883f7ac R14: 8883f7ac0d90 R15: 8883f844d000 <4>[3.324908] FS: 7ffa4a839680() GS:88841000() knlGS: <4>[3.324917] CS: 0010 DS: ES: CR0: 80050033 <4>[3.324923] CR2: CR3: 000401aa4002 CR4: 001606f0 <4>[3.324930] Call Trace: <4>[3.324980] ? gen6_read32+0x272/0x300 [i915] <4>[3.325044] intel_ddi_get_config+0x238/0x610 [i915] <4>[3.325108] hsw_crt_get_config+0x12/0x40 [i915] <4>[3.325173] intel_modeset_setup_hw_state+0x3b3/0x1660 [i915] <4>[3.325182] ? ww_mutex_lock+0x39/0x70 <4>[3.325190] ? drm_modeset_lock+0xad/0x120 <4>[3.325254] intel_modeset_init+0x582/0x1c50 [i915] <4>[3.325263] ? _raw_spin_unlock_irqrestore+0x34/0x60 <4>[3.325314] ? intel_irq_postinstall+0xb3/0x610 [i915] <4>[3.325366] i915_driver_probe+0xa7e/0xed0 [i915] <4>[3.325375] ? __pm_runtime_resume+0x4f/0x80 <4>[3.325426] i915_pci_probe+0x43/0x1b0 [i915] <4>[3.325434] ? _raw_spin_unlock_irqrestore+0x34/0x60 <4>[3.325442] pci_device_probe+0x9e/0x120 <4>[3.325450] really_probe+0xea/0x430 <4>[3.325456] driver_probe_device+0x10b/0x120 <4>[3.325463] device_driver_attach+0x4a/0x50 <4>[3.325469] __driver_attach+0x97/0x130 <4>[3.325476] ? device_driver_attach+0x50/0x50 <4>[3.325482] bus_for_each_dev+0x74/0xc0 <4>[3.325489] bus_add_driver+0x142/0x220 <4>[3.325495] driver_register+0x56/0xf0 <4>[3.325543] i915_init+0x6c/0x7c [i915] <4>[3.325549] ? 0xa087f000 <4>[3.32] do_one_initcall+0x58/0x300 <4>[3.325562] ? rcu_read_lock_sched_held+0x4d/0x80 <4>[3.325570] ? kmem_cache_alloc_trace+0x2a6/0x2d0 <4>[3.325578] do_init_module+0x56/0x1f2 <4>[3.325584] load_module+0x233d/0x2a30 <4>[3.325596] ? __do_sys_finit_module+0xe9/0x110 <4>[3.325602] __do_sys_finit_module+0xe9/0x110 <4>[3.325612] do_syscall_64+0x4f/0x220 <4>[3.325618] entry_SYSCALL_64_after_hwframe+0x49/0xbe <4>[3.325624] RIP: 0033:0x7ffa4a35a839 <4>[3.325630] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48 <4>[3.325647] RSP: 002b:7ffdbdf7b848 EFLAGS: 0246 ORIG_RAX: 0139 <4>[3.325656] RAX: ffda RBX: 55bc2aa95fc0 RCX: 7ffa4a35a839 <4>[3.325663] RDX: RSI: 7ffa4a039145 RDI: 000f <4>[3.325671]
Re: [Intel-gfx] [PATCH] drm/i915/display: Fix mode private_flags comparison at atomic_check
Op 26-03-2020 om 08:49 schreef Uma Shankar:
> This patch fixes the private_flags of mode to be checked and
> compared against uapi.mode and not from hw.mode. This helps
> properly trigger modeset at boot if desired by driver.
>
> It helps resolve audio_codec initialization issues if display
> is connected at boot. Initial discussion on this issue has happened
> on below thread:
> https://patchwork.freedesktop.org/series/74828/
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/issues/1363
Wrong use of fixes. :)
Use dim fixes original-commit-id to reference the commit. And for this use the
Closes: tag.
Other than that looks good. :)
So with headers fixed:
Reviewed-By: Maarten Lankhorst
> Cc: Ville Syrjä
> Cc: Maarten Lankhorst
> Cc: Kai Vehmanen
> Cc: Souza, Jose
> Suggested-by: Ville Syrjä
> Signed-off-by: Uma Shankar
> Signed-off-by: SweeAun Khor
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index fe55c7c713f1..e630429af2c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14747,8 +14747,8 @@ static int intel_atomic_check(struct drm_device *dev,
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - if (new_crtc_state->hw.mode.private_flags !=
> - old_crtc_state->hw.mode.private_flags)
> + if (new_crtc_state->uapi.mode.private_flags !=
> + old_crtc_state->uapi.mode.private_flags)
> new_crtc_state->uapi.mode_changed = true;
> }
>
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[Intel-gfx] [PATCH 15/21] drm/i915: Dirty hack to fix selftests locking inversion
Some i915 selftests still use i915_vma_lock() as inner lock, and intel_context_create_request() intel_timeline->mutex as outer lock. Fortunately for selftests this is not an issue, they should be fixed but we can move ahead and cleanify lockdep now. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_context.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 113d0bda1bcf..5c7acddf9651 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -460,6 +460,18 @@ struct i915_request *intel_context_create_request(struct intel_context *ce) rq = i915_request_create(ce); intel_context_unpin(ce); + if (IS_ERR(rq)) + return rq; + + /* +* timeline->mutex should be the inner lock, but is used as outer lock. +* Hack around this to shut up lockdep in selftests.. +*/ + lockdep_unpin_lock(>timeline->mutex, rq->cookie); + mutex_release(>timeline->mutex.dep_map, _RET_IP_); + mutex_acquire(>timeline->mutex.dep_map, SINGLE_DEPTH_NESTING, 0, _RET_IP_); + rq->cookie = lockdep_pin_lock(>timeline->mutex); + return rq; } -- 2.25.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/21] drm/i915: Remove locking from i915_gem_object_prepare_read/write
Execbuffer submission will perform its own WW locking, and we
cannot rely on the implicit lock there.
This also makes it clear that the GVT code will get a lockdep splat when
multiple batchbuffer shadows need to be performed in the same instance,
fix that up.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 20 ++-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 13 ++--
drivers/gpu/drm/i915/gem/i915_gem_object.h| 1 -
.../gpu/drm/i915/gem/selftests/huge_pages.c | 5 -
.../i915/gem/selftests/i915_gem_coherency.c | 14 +
.../drm/i915/gem/selftests/i915_gem_context.c | 12 ---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 5 -
drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 -
drivers/gpu/drm/i915/i915_gem.c | 20 +--
9 files changed, 70 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index f4602faa8db9..e9d3b587f562 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -581,19 +581,17 @@ int i915_gem_object_prepare_read(struct
drm_i915_gem_object *obj,
if (!i915_gem_object_has_struct_page(obj))
return -ENODEV;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
+ assert_object_held(obj);
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE,
MAX_SCHEDULE_TIMEOUT);
if (ret)
- goto err_unlock;
+ return ret;
ret = i915_gem_object_pin_pages(obj);
if (ret)
- goto err_unlock;
+ return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
!static_cpu_has(X86_FEATURE_CLFLUSH)) {
@@ -621,8 +619,6 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object
*obj,
err_unpin:
i915_gem_object_unpin_pages(obj);
-err_unlock:
- i915_gem_object_unlock(obj);
return ret;
}
@@ -635,20 +631,18 @@ int i915_gem_object_prepare_write(struct
drm_i915_gem_object *obj,
if (!i915_gem_object_has_struct_page(obj))
return -ENODEV;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
+ assert_object_held(obj);
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE |
I915_WAIT_ALL,
MAX_SCHEDULE_TIMEOUT);
if (ret)
- goto err_unlock;
+ return ret;
ret = i915_gem_object_pin_pages(obj);
if (ret)
- goto err_unlock;
+ return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
!static_cpu_has(X86_FEATURE_CLFLUSH)) {
@@ -685,7 +679,5 @@ int i915_gem_object_prepare_write(struct
drm_i915_gem_object *obj,
err_unpin:
i915_gem_object_unpin_pages(obj);
-err_unlock:
- i915_gem_object_unlock(obj);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index b20df39a57ba..00c7c72c4742 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -960,11 +960,14 @@ static void reloc_cache_reset(struct reloc_cache *cache)
vaddr = unmask_page(cache->vaddr);
if (cache->vaddr & KMAP) {
+ struct drm_i915_gem_object *obj =
+ (struct drm_i915_gem_object *)cache->node.mm;
if (cache->vaddr & CLFLUSH_AFTER)
mb();
kunmap_atomic(vaddr);
- i915_gem_object_finish_access((struct drm_i915_gem_object
*)cache->node.mm);
+ i915_gem_object_finish_access(obj);
+ i915_gem_object_unlock(obj);
} else {
struct i915_ggtt *ggtt = cache_to_ggtt(cache);
@@ -999,10 +1002,16 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,
unsigned int flushes;
int err;
- err = i915_gem_object_prepare_write(obj, );
+ err = i915_gem_object_lock_interruptible(obj, NULL);
if (err)
return ERR_PTR(err);
+ err = i915_gem_object_prepare_write(obj, );
+ if (err) {
+ i915_gem_object_unlock(obj);
+ return ERR_PTR(err);
+ }
+
BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 5103067269b0..11b8e2735071 100644
---
[Intel-gfx] [PATCH 12/21] drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2.
This is the last part outside of selftests that still don't use the
correct lock ordering of timeline->mutex vs resv_lock.
With gem fixed, there are a few places that still get locking wrong:
- gvt/scheduler.c
- i915_perf.c
- Most if not all selftests.
Changes since v1:
- Add intel_engine_pm_get/put() calls to fix use-after-free when using
intel_engine_get_pool().
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 80 +++--
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 156 +++---
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 3 +
3 files changed, 165 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 5d94a77f9bdd..10df576e785f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -157,6 +157,7 @@ static void clear_pages_worker(struct work_struct *work)
struct clear_pages_work *w = container_of(work, typeof(*w), work);
struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
struct i915_vma *vma = w->sleeve->vma;
+ struct i915_gem_ww_ctx ww;
struct i915_request *rq;
struct i915_vma *batch;
int err = w->dma.error;
@@ -172,17 +173,20 @@ static void clear_pages_worker(struct work_struct *work)
obj->read_domains = I915_GEM_GPU_DOMAINS;
obj->write_domain = 0;
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
- if (unlikely(err))
+ i915_gem_ww_ctx_init(, false);
+ intel_engine_pm_get(w->ce->engine);
+retry:
+ err = intel_context_pin_ww(w->ce, );
+ if (err)
goto out_signal;
- batch = intel_emit_vma_fill_blt(w->ce, vma, w->value);
+ batch = intel_emit_vma_fill_blt(w->ce, vma, , w->value);
if (IS_ERR(batch)) {
err = PTR_ERR(batch);
- goto out_unpin;
+ goto out_ctx;
}
- rq = intel_context_create_request(w->ce);
+ rq = i915_request_create(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_batch;
@@ -224,9 +228,19 @@ static void clear_pages_worker(struct work_struct *work)
i915_request_add(rq);
out_batch:
intel_emit_vma_release(w->ce, batch);
-out_unpin:
- i915_vma_unpin(vma);
+out_ctx:
+ intel_context_unpin(w->ce);
out_signal:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+
+ i915_vma_unpin(w->sleeve->vma);
+ intel_engine_pm_put(w->ce->engine);
+
if (unlikely(err)) {
dma_fence_set_error(>dma, err);
dma_fence_signal(>dma);
@@ -234,6 +248,45 @@ static void clear_pages_worker(struct work_struct *work)
}
}
+static int pin_wait_clear_pages_work(struct clear_pages_work *w,
+struct intel_context *ce)
+{
+ struct i915_vma *vma = w->sleeve->vma;
+ struct i915_gem_ww_ctx ww;
+ int err;
+
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_gem_object_lock(vma->obj, );
+ if (err)
+ goto out;
+
+ err = i915_vma_pin_ww(vma, , 0, 0, PIN_USER);
+ if (unlikely(err))
+ goto out;
+
+ err = i915_sw_fence_await_reservation(>wait,
+ vma->obj->base.resv, NULL,
+ true, I915_FENCE_TIMEOUT,
+ I915_FENCE_GFP);
+ if (err)
+ goto err_unpin_vma;
+
+ dma_resv_add_excl_fence(vma->obj->base.resv, >dma);
+
+err_unpin_vma:
+ if (err)
+ i915_vma_unpin(vma);
+out:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+ return err;
+}
+
static int __i915_sw_fence_call
clear_pages_work_notify(struct i915_sw_fence *fence,
enum i915_sw_fence_notify state)
@@ -287,18 +340,9 @@ int i915_gem_schedule_fill_pages_blt(struct
drm_i915_gem_object *obj,
dma_fence_init(>dma, _pages_work_ops, _lock, 0, 0);
i915_sw_fence_init(>wait, clear_pages_work_notify);
- i915_gem_object_lock(obj, NULL);
- err = i915_sw_fence_await_reservation(>wait,
- obj->base.resv, NULL,
- true, I915_FENCE_TIMEOUT,
- I915_FENCE_GFP);
- if (err < 0) {
+ err = pin_wait_clear_pages_work(work, ce);
+ if (err < 0)
dma_fence_set_error(>dma, err);
- } else {
- dma_resv_add_excl_fence(obj->base.resv, >dma);
- err = 0;
- }
-
[Intel-gfx] [PATCH 11/21] drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin.
As a preparation step for full object locking and wait/wound handling
during pin and object mapping, ensure that we always pass the ww context
in i915_gem_execbuffer.c to i915_vma_pin, use lockdep to ensure this
happens.
This also requires changing the order of eb_parse slightly, to ensure
we pass ww at a point where we could still handle -EDEADLK safely.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 125 ++
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 4 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 4 +-
drivers/gpu/drm/i915/gt/intel_context.c | 65 +
drivers/gpu/drm/i915/gt/intel_context.h | 13 ++
drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ring.c | 10 +-
drivers/gpu/drm/i915/gt/intel_ring.h | 3 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 15 +--
drivers/gpu/drm/i915/gt/intel_timeline.c | 12 +-
drivers/gpu/drm/i915/gt/intel_timeline.h | 3 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 13 +-
drivers/gpu/drm/i915/i915_gem.c | 11 +-
drivers/gpu/drm/i915/i915_vma.c | 13 +-
drivers/gpu/drm/i915/i915_vma.h | 13 +-
24 files changed, 207 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 80d13a2fa66b..a9911dc9f2a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3441,7 +3441,7 @@ initial_plane_vma(struct drm_i915_private *i915,
if (IS_ERR(vma))
goto err_obj;
- if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
+ if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
goto err_obj;
if (i915_gem_object_is_tiled(obj) &&
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 062848951095..f5b01e70eb61 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1145,7 +1145,7 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
i915_gem_ww_ctx_init(, true);
retry:
- err = intel_context_pin(ce);
+ err = intel_context_pin_ww(ce, );
if (err)
goto err;
@@ -1238,7 +1238,7 @@ static int pin_ppgtt_update(struct intel_context *ce,
struct i915_gem_ww_ctx *ww
if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915))
/* ppGTT is not part of the legacy context image */
- return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm));
+ return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm), ww);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 6b8d5163de5a..ce3b62a7385c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -394,7 +394,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT))
pin_flags |= PIN_GLOBAL;
- if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags)))
+ if (unlikely(i915_vma_pin_ww(vma, >ww, 0, 0, pin_flags)))
return false;
if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
@@ -535,7 +535,7 @@ static inline int use_cpu_reloc(const struct reloc_cache
*cache,
obj->cache_level != I915_CACHE_NONE);
}
-static int eb_reserve_vma(const struct i915_execbuffer *eb,
+static int eb_reserve_vma(struct i915_execbuffer *eb,
struct eb_vma *ev,
u64 pin_flags)
{
@@ -569,7 +569,7 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb,
return err;
}
- err = i915_vma_pin(vma,
+ err = i915_vma_pin_ww(vma, >ww,
entry->pad_to_size, entry->alignment,
pin_flags);
if (err)
@@ -1062,9 +1062,10 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,
}
static void *reloc_iomap(struct drm_i915_gem_object *obj,
-struct reloc_cache *cache,
+struct i915_execbuffer *eb,
unsigned long page)
{
+ struct reloc_cache *cache = >reloc_cache;
[Intel-gfx] [PATCH 18/21] drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2.
Make sure vma_lock is not used as inner lock when kernel context is used,
and add ww handling where appropriate.
Signed-off-by: Maarten Lankhorst
---
.../i915/gem/selftests/i915_gem_coherency.c | 26 ++--
.../drm/i915/gem/selftests/i915_gem_mman.c| 41 ++-
drivers/gpu/drm/i915/selftests/i915_request.c | 18 +---
3 files changed, 57 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 99f8466a108a..d93b7d9ad174 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -199,25 +199,25 @@ static int gpu_set(struct context *ctx, unsigned long
offset, u32 v)
i915_gem_object_lock(ctx->obj, NULL);
err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);
- i915_gem_object_unlock(ctx->obj);
if (err)
- return err;
+ goto out_unlock;
vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0);
- if (IS_ERR(vma))
- return PTR_ERR(vma);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_unlock;
+ }
rq = intel_engine_create_kernel_request(ctx->engine);
if (IS_ERR(rq)) {
- i915_vma_unpin(vma);
- return PTR_ERR(rq);
+ err = PTR_ERR(rq);
+ goto out_unpin;
}
cs = intel_ring_begin(rq, 4);
if (IS_ERR(cs)) {
- i915_request_add(rq);
- i915_vma_unpin(vma);
- return PTR_ERR(cs);
+ err = PTR_ERR(cs);
+ goto out_rq;
}
if (INTEL_GEN(ctx->engine->i915) >= 8) {
@@ -238,14 +238,16 @@ static int gpu_set(struct context *ctx, unsigned long
offset, u32 v)
}
intel_ring_advance(rq, cs);
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, true);
if (err == 0)
err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
- i915_vma_unpin(vma);
+out_rq:
i915_request_add(rq);
+out_unpin:
+ i915_vma_unpin(vma);
+out_unlock:
+ i915_gem_object_unlock(ctx->obj);
return err;
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index a67d9e59fe12..d4aaf603a78f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -528,31 +528,42 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
for_each_uabi_engine(engine, i915) {
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
int err;
vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
if (IS_ERR(vma))
return PTR_ERR(vma);
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_gem_object_lock(obj, );
+ if (!err)
+ err = i915_vma_pin_ww(vma, , 0, 0, PIN_USER);
if (err)
- return err;
+ goto err;
rq = intel_engine_create_kernel_request(engine);
if (IS_ERR(rq)) {
- i915_vma_unpin(vma);
- return PTR_ERR(rq);
+ err = PTR_ERR(rq);
+ goto err_unpin;
}
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, true);
if (err == 0)
err = i915_vma_move_to_active(vma, rq,
EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
i915_request_add(rq);
+err_unpin:
i915_vma_unpin(vma);
+err:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
if (err)
return err;
}
@@ -1000,6 +1011,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
for_each_uabi_engine(engine, i915) {
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
vma = i915_vma_instance(obj, engine->kernel_context->vm, NULL);
if (IS_ERR(vma)) {
@@ -1007,9 +1019,13 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
goto out_unmap;
}
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ i915_gem_ww_ctx_init(, false);
[Intel-gfx] [PATCH 19/21] drm/i915: Add ww locking to vm_fault_gtt
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 51 +++-
1 file changed, 33 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index b39c24dae64e..e35e8d0b6938 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -283,37 +283,46 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
struct intel_runtime_pm *rpm = >runtime_pm;
struct i915_ggtt *ggtt = >ggtt;
bool write = area->vm_flags & VM_WRITE;
+ struct i915_gem_ww_ctx ww;
intel_wakeref_t wakeref;
struct i915_vma *vma;
pgoff_t page_offset;
int srcu;
int ret;
- /* Sanity check that we allow writing into this object */
- if (i915_gem_object_is_readonly(obj) && write)
- return VM_FAULT_SIGBUS;
-
/* We don't use vmf->pgoff since that has the fake offset */
page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
trace_i915_gem_object_fault(obj, page_offset, true, write);
- ret = i915_gem_object_pin_pages(obj);
+ wakeref = intel_runtime_pm_get(rpm);
+
+ i915_gem_ww_ctx_init(, true);
+retry:
+ ret = i915_gem_object_lock(obj, );
if (ret)
- goto err;
+ goto err_rpm;
- wakeref = intel_runtime_pm_get(rpm);
+ /* Sanity check that we allow writing into this object */
+ if (i915_gem_object_is_readonly(obj) && write) {
+ ret = -EFAULT;
+ goto err_rpm;
+ }
- ret = intel_gt_reset_trylock(ggtt->vm.gt, );
+ ret = i915_gem_object_pin_pages(obj);
if (ret)
goto err_rpm;
+ ret = intel_gt_reset_trylock(ggtt->vm.gt, );
+ if (ret)
+ goto err_pages;
+
/* Now pin it into the GTT as needed */
- vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
- PIN_MAPPABLE |
- PIN_NONBLOCK /* NOWARN */ |
- PIN_NOEVICT);
- if (IS_ERR(vma)) {
+ vma = i915_gem_object_ggtt_pin_ww(obj, , NULL, 0, 0,
+ PIN_MAPPABLE |
+ PIN_NONBLOCK /* NOWARN */ |
+ PIN_NOEVICT);
+ if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) {
/* Use a partial view if it is bigger than available space */
struct i915_ggtt_view view =
compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
@@ -328,11 +337,11 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
* all hope that the hardware is able to track future writes.
*/
- vma = i915_gem_object_ggtt_pin(obj, , 0, 0, flags);
- if (IS_ERR(vma)) {
+ vma = i915_gem_object_ggtt_pin_ww(obj, , , 0, 0, flags);
+ if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) {
flags = PIN_MAPPABLE;
view.type = I915_GGTT_VIEW_PARTIAL;
- vma = i915_gem_object_ggtt_pin(obj, , 0, 0, flags);
+ vma = i915_gem_object_ggtt_pin_ww(obj, , , 0,
0, flags);
}
/* The entire mappable GGTT is pinned? Unexpected! */
@@ -389,10 +398,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
__i915_vma_unpin(vma);
err_reset:
intel_gt_reset_unlock(ggtt->vm.gt, srcu);
+err_pages:
+ i915_gem_object_unpin_pages(obj);
err_rpm:
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff();
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
intel_runtime_pm_put(rpm, wakeref);
- i915_gem_object_unpin_pages(obj);
-err:
return i915_error_to_vmf_fault(ret);
}
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/21] drm/i915: Use ww pinning for intel_context_create_request()
We want to get rid of intel_context_pin(), convert
intel_context_create_request() first. :)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_context.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 5c7acddf9651..f70135685552 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -450,15 +450,25 @@ int intel_context_prepare_remote_request(struct
intel_context *ce,
struct i915_request *intel_context_create_request(struct intel_context *ce)
{
+ struct i915_gem_ww_ctx ww;
struct i915_request *rq;
int err;
- err = intel_context_pin(ce);
- if (unlikely(err))
- return ERR_PTR(err);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = intel_context_pin_ww(ce, );
+ if (!err) {
+ rq = i915_request_create(ce);
+ intel_context_unpin(ce);
+ } else if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ } else {
+ rq = ERR_PTR(err);
+ }
- rq = i915_request_create(ce);
- intel_context_unpin(ce);
+ i915_gem_ww_ctx_fini();
if (IS_ERR(rq))
return rq;
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/21] drm/i915: Nuke arguments to eb_pin_engine
Those arguments are already set as eb.file and eb.args, so kill off
the extra arguments. This will allow us to move eb_pin_engine() to
after we reserved all BO's.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 08face3dfca9..775acc07e946 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2414,11 +2414,10 @@ static void eb_unpin_engine(struct i915_execbuffer *eb)
}
static unsigned int
-eb_select_legacy_ring(struct i915_execbuffer *eb,
- struct drm_file *file,
- struct drm_i915_gem_execbuffer2 *args)
+eb_select_legacy_ring(struct i915_execbuffer *eb)
{
struct drm_i915_private *i915 = eb->i915;
+ struct drm_i915_gem_execbuffer2 *args = eb->args;
unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
if (user_ring_id != I915_EXEC_BSD &&
@@ -2433,7 +2432,7 @@ eb_select_legacy_ring(struct i915_execbuffer *eb,
unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
- bsd_idx = gen8_dispatch_bsd_engine(i915, file);
+ bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file);
} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
bsd_idx <= I915_EXEC_BSD_RING2) {
bsd_idx >>= I915_EXEC_BSD_SHIFT;
@@ -2458,18 +2457,16 @@ eb_select_legacy_ring(struct i915_execbuffer *eb,
}
static int
-eb_pin_engine(struct i915_execbuffer *eb,
- struct drm_file *file,
- struct drm_i915_gem_execbuffer2 *args)
+eb_pin_engine(struct i915_execbuffer *eb)
{
struct intel_context *ce;
unsigned int idx;
int err;
if (i915_gem_context_user_engines(eb->gem_context))
- idx = args->flags & I915_EXEC_RING_MASK;
+ idx = eb->args->flags & I915_EXEC_RING_MASK;
else
- idx = eb_select_legacy_ring(eb, file, args);
+ idx = eb_select_legacy_ring(eb);
ce = i915_gem_context_get_engine(eb->gem_context, idx);
if (IS_ERR(ce))
@@ -2767,7 +2764,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_destroy;
- err = eb_pin_engine(, file, args);
+ err = eb_pin_engine();
if (unlikely(err))
goto err_context;
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/21] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2.
i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory
eviction. We don't use it yet, but lets start adding the definition
first.
To use it, we have to pass a non-NULL ww to gem_object_lock, and don't
unlock directly. It is done in i915_gem_ww_ctx_fini.
Changes since v1:
- Change ww_ctx and obj order in locking functions (Jonas Lahtinen)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 10 ++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 38 +++---
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../i915/gem/selftests/i915_gem_coherency.c | 10 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 4 +-
.../drm/i915/gem/selftests/i915_gem_phys.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 52 +--
drivers/gpu/drm/i915/i915_gem.h | 11
drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++
drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +-
.../drm/i915/selftests/intel_memory_region.c | 2 +-
26 files changed, 175 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fe55c7c713f1..80d13a2fa66b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2303,7 +2303,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
{
- i915_gem_object_lock(vma->obj);
+ i915_gem_object_lock(vma->obj, NULL);
if (flags & PLANE_HAS_FENCE)
i915_vma_unpin_fence(vma);
i915_gem_object_unpin_from_display_plane(vma);
@@ -17137,7 +17137,7 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
if (!intel_fb->frontbuffer)
return -ENOMEM;
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
tiling = i915_gem_object_get_tiling(obj);
stride = i915_gem_object_get_stride(obj);
i915_gem_object_unlock(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 0598e5382a1d..5d94a77f9bdd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -287,7 +287,7 @@ int i915_gem_schedule_fill_pages_blt(struct
drm_i915_gem_object *obj,
dma_fence_init(>dma, _pages_work_ops, _lock, 0, 0);
i915_sw_fence_init(>wait, clear_pages_work_notify);
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
err = i915_sw_fence_await_reservation(>wait,
obj->base.resv, NULL,
true, I915_FENCE_TIMEOUT,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 50e7580f9337..ac2b88ca00ce 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx)
continue;
rcu_read_unlock();
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
list_for_each_entry(lut, >lut_list, obj_link) {
if (lut->ctx != ctx)
continue;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 7db5a793739d..cfadccfc2990 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf
*dma_buf, enum dma_data_dire
if (err)
return err;
- err = i915_gem_object_lock_interruptible(obj);
+ err = i915_gem_object_lock_interruptible(obj, NULL);
if (err)
goto out;
@@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf,
enum dma_data_direct
if (err)
return err;
-
[Intel-gfx] [PATCH 05/21] drm/i915: Use per object locking in execbuf, v6.
Now that we changed execbuf submission slightly to allow us to do all
pinning in one place, we can now simply add ww versions on top of
struct_mutex. All we have to do is a separate path for -EDEADLK
handling, which needs to unpin all gem bo's before dropping the lock,
then starting over.
This finally allows us to do parallel submission, but because not
all of the pinning code uses the ww ctx yet, we cannot completely
drop struct_mutex yet.
Changes since v1:
- Keep struct_mutex for now. :(
Changes since v2:
- Make sure we always lock the ww context in slowpath.
Changes since v3:
- Don't call __eb_unreserve_vma in eb_move_to_gpu now; this can be
done on normal unlock path.
- Unconditionally release vmas and context.
Changes since v4:
- Rebased on top of struct_mutex reduction.
Changes since v5:
- Remove training wheels.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 271 ++
1 file changed, 148 insertions(+), 123 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 4a41ff4d2e62..08face3dfca9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -249,6 +249,8 @@ struct i915_execbuffer {
/** list of vma that have execobj.relocation_count */
struct list_head relocs;
+ struct i915_gem_ww_ctx ww;
+
/**
* Track the most recently used object for relocations, as we
* frequently have to perform multiple relocations within the same
@@ -404,24 +406,18 @@ eb_pin_vma(struct i915_execbuffer *eb,
return !eb_vma_misplaced(entry, vma, ev->flags);
}
-static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
-{
- GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
-
- if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
- __i915_vma_unpin_fence(vma);
-
- __i915_vma_unpin(vma);
-}
-
static inline void
eb_unreserve_vma(struct eb_vma *ev)
{
if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
return;
- __eb_unreserve_vma(ev->vma, ev->flags);
ev->flags &= ~__EXEC_OBJECT_RESERVED;
+
+ if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
+ __i915_vma_unpin_fence(ev->vma);
+
+ __i915_vma_unpin(ev->vma);
}
static int
@@ -515,16 +511,6 @@ eb_add_vma(struct i915_execbuffer *eb,
eb->batch = ev;
}
-
- if (eb_pin_vma(eb, entry, ev)) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
- eb->args->flags |= __EXEC_HAS_RELOC;
- }
- } else {
- eb_unreserve_vma(ev);
- list_add_tail(>bind_link, >unbound);
- }
}
static inline int use_cpu_reloc(const struct reloc_cache *cache,
@@ -628,18 +614,14 @@ static int eb_reserve(struct i915_execbuffer *eb)
* This avoid unnecessary unbinding of later objects in order to make
* room for the earlier objects *unless* we need to defragment.
*/
-
- if (mutex_lock_interruptible(>i915->drm.struct_mutex))
- return -EINTR;
-
pass = 0;
do {
list_for_each_entry(ev, >unbound, bind_link) {
err = eb_reserve_vma(eb, ev, pin_flags);
if (err)
- break;
+ return err;
}
- if (!(err == -ENOSPC || err == -EAGAIN))
+ if (err != -ENOSPC)
break;
/* Resort *all* the objects into priority order */
@@ -670,13 +652,6 @@ static int eb_reserve(struct i915_execbuffer *eb)
}
list_splice_tail(, >unbound);
- if (err == -EAGAIN) {
- mutex_unlock(>i915->drm.struct_mutex);
- flush_workqueue(eb->i915->mm.userptr_wq);
- mutex_lock(>i915->drm.struct_mutex);
- continue;
- }
-
switch (pass++) {
case 0:
break;
@@ -687,19 +662,16 @@ static int eb_reserve(struct i915_execbuffer *eb)
err = i915_gem_evict_vm(eb->context->vm);
mutex_unlock(>context->vm->mutex);
if (err)
- goto unlock;
+ return err;
break;
default:
- err = -ENOSPC;
- goto unlock;
+ return -ENOSPC;
}
pin_flags = PIN_USER;
} while (1);
-unlock:
- mutex_unlock(>i915->drm.struct_mutex);
return err;
}
@@ -822,7 +794,6 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
int err =
[Intel-gfx] [PATCH 04/21] drm/i915: Parse command buffer earlier in eb_relocate(slow)
We want to introduce backoff logic, but we need to lock the
pool object as well for command parsing. Because of this, we
will need backoff logic for the engine pool obj, move the batch
validation up slightly to eb_lookup_vmas, and the actual command
parsing in a separate function which can get called from execbuf
relocation fast and slowpath.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 68 ++-
1 file changed, 37 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 00c7c72c4742..4a41ff4d2e62 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -285,6 +285,8 @@ struct i915_execbuffer {
struct hlist_head *buckets; /** ht for relocation handles */
};
+static int eb_parse(struct i915_execbuffer *eb);
+
static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
{
return intel_engine_requires_cmd_parser(eb->engine) ||
@@ -814,6 +816,7 @@ static struct i915_vma *eb_lookup_vma(struct
i915_execbuffer *eb, u32 handle)
static int eb_lookup_vmas(struct i915_execbuffer *eb)
{
+ struct drm_i915_private *i915 = eb->i915;
unsigned int batch = eb_batch_index(eb);
unsigned int i;
int err = 0;
@@ -827,18 +830,37 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
vma = eb_lookup_vma(eb, eb->exec[i].handle);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
- break;
+ goto err;
}
err = eb_validate_vma(eb, >exec[i], vma);
if (unlikely(err)) {
i915_vma_put(vma);
- break;
+ goto err;
}
eb_add_vma(eb, i, batch, vma);
}
+ if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) {
+ drm_dbg(>drm,
+ "Attempting to use self-modifying batch buffer\n");
+ return -EINVAL;
+ }
+
+ if (range_overflows_t(u64,
+ eb->batch_start_offset, eb->batch_len,
+ eb->batch->vma->size)) {
+ drm_dbg(>drm, "Attempting to use out-of-bounds batch\n");
+ return -EINVAL;
+ }
+
+ if (eb->batch_len == 0)
+ eb->batch_len = eb->batch->vma->size - eb->batch_start_offset;
+
+ return 0;
+
+err:
eb->vma[i].vma = NULL;
return err;
}
@@ -1688,7 +1710,7 @@ static int eb_prefault_relocations(const struct
i915_execbuffer *eb)
return 0;
}
-static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
+static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb)
{
bool have_copy = false;
struct eb_vma *ev;
@@ -1739,6 +1761,11 @@ static noinline int eb_relocate_slow(struct
i915_execbuffer *eb)
}
}
+ /* as last step, parse the command buffer */
+ err = eb_parse(eb);
+ if (err)
+ goto err;
+
/*
* Leave the user relocations as are, this is the painfully slow path,
* and we want to avoid the complication of dropping the lock whilst
@@ -1771,7 +1798,7 @@ static noinline int eb_relocate_slow(struct
i915_execbuffer *eb)
return err;
}
-static int eb_relocate(struct i915_execbuffer *eb)
+static int eb_relocate_parse(struct i915_execbuffer *eb)
{
int err;
@@ -1791,11 +1818,11 @@ static int eb_relocate(struct i915_execbuffer *eb)
list_for_each_entry(ev, >relocs, reloc_link) {
if (eb_relocate_vma(eb, ev))
- return eb_relocate_slow(eb);
+ return eb_relocate_parse_slow(eb);
}
}
- return 0;
+ return eb_parse(eb);
}
static int eb_move_to_gpu(struct i915_execbuffer *eb)
@@ -2731,7 +2758,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_context;
- err = eb_relocate();
+ err = eb_relocate_parse();
if (err) {
/*
* If the user expects the execobject.offset and
@@ -2744,33 +2771,10 @@ i915_gem_do_execbuffer(struct drm_device *dev,
goto err_vma;
}
- if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) {
- drm_dbg(>drm,
- "Attempting to use self-modifying batch buffer\n");
- err = -EINVAL;
- goto err_vma;
- }
-
- if (range_overflows_t(u64,
- eb.batch_start_offset, eb.batch_len,
- eb.batch->vma->size)) {
- drm_dbg(>drm, "Attempting to use out-of-bounds batch\n");
- err = -EINVAL;
-
