Re: [PATCH] drm/msm: Fix link error with !MSM_IOMMU
On Wed, Jan 08, 2014 at 08:23:49AM -0500, Rob Clark wrote: On Tue, Jan 7, 2014 at 5:53 PM, Joerg Roedel j...@8bytes.org wrote: On Tue, Jan 07, 2014 at 11:47:26PM +0100, Joerg Roedel wrote: The DRM driver for MSM depends on symbols from the MSM IOMMU driver. Add this dependency to the Kconfig file. Fixes this comile error: Kernel: arch/arm/boot/zImage is ready ERROR: msm_iommu_get_ctx [drivers/gpu/drm/msm/msm.ko] undefined! make[2]: *** [__modpost] Error 1 Thanks, I'll pull this into my pull req for 3.14 drm-next.. although, after chatting with Stephen Boyd, I think we should eventually be able to get rid of this (seems msm_iommu_get_ctx() was mainly for dealing with secure playback (?)) It is already in my next-branch. So if you are ok with the approach for now there is no need for action. If you want it to go through your tree anyway please let me know and I will drop it from mine. Joerg ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH] drm/msm: Fix link error with !MSM_IOMMU
On Wed, Jan 8, 2014 at 8:35 AM, Joerg Roedel j...@8bytes.org wrote: On Wed, Jan 08, 2014 at 08:23:49AM -0500, Rob Clark wrote: On Tue, Jan 7, 2014 at 5:53 PM, Joerg Roedel j...@8bytes.org wrote: On Tue, Jan 07, 2014 at 11:47:26PM +0100, Joerg Roedel wrote: The DRM driver for MSM depends on symbols from the MSM IOMMU driver. Add this dependency to the Kconfig file. Fixes this comile error: Kernel: arch/arm/boot/zImage is ready ERROR: msm_iommu_get_ctx [drivers/gpu/drm/msm/msm.ko] undefined! make[2]: *** [__modpost] Error 1 Thanks, I'll pull this into my pull req for 3.14 drm-next.. although, after chatting with Stephen Boyd, I think we should eventually be able to get rid of this (seems msm_iommu_get_ctx() was mainly for dealing with secure playback (?)) It is already in my next-branch. So if you are ok with the approach for now there is no need for action. If you want it to go through your tree anyway please let me know and I will drop it from mine. probably will be a slight merge conflict if it goes through your branch.. although should be easy enough to resolve, basically the result should look something like: depends on (ARCH_MSM ARCH_MSM8960 MSM_IOMMU) || (ARM COMPILE_TEST) BR, -R Joerg ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [Patch Part2 V1 00/14] Enhance DMAR drivers to handle PCI/memory hotplug events
On Tue, Jan 7, 2014 at 1:00 AM, Jiang Liu jiang@linux.intel.com wrote: Intel DMA/interrupt remapping drivers scan available PCI/memory devices at startup and cache discovered hardware topologies. They don't update cached information if PCI/memory hotplug event happens at runtime, then the stale information may break DMA/interrupt remapping logic. This patchset first (Patch 1-8) tries to introduces some helper functions and fixes several bugs, then (Patch 9,10) uses a global rwsem and RCU to protect global DMA/interrupt remapping data structures, and finally (Patch 11-14) hook PCI/memory hotplug events to update cached information. It's also a preparation for supporting of DMA/interrupt remapping hotplug. Jiang Liu (14): iommu/vt-d: factor out dmar_alloc_dev_scope() for later reuse iommu/vt-d: move private structures and variables into intel-iommu.c iommu/vt-d: simplify function get_domain_for_dev() iommu/vt-d: free resources if failed to create domain for PCIe endpoint iommu/vt-d: create device_domain_info structure for intermediate P2P bridges iommu/vt-d: fix incorrect iommu_count for si_domain iommu/vt-d: fix error in detect ATS capability iommu/vt-d: introduce macro for_each_dev_scope() to walk device scope entries iommu/vt-d: introduce a rwsem to protect global data structures iommu/vt-d: use RCU to protect global resources in interrupt context iommu/vt-d, PCI: update DRHD/RMRR/ATSR device scope caches when PCI hotplug happens iommu/vt-d, PCI: unify the way to process DMAR device scope array iommu/vt-d: update device to static identity domain mapping for PCI hotplug iommu/vt-d: update IOMMU state when memory hotplug happens drivers/iommu/dmar.c| 412 + drivers/iommu/intel-iommu.c | 583 +-- drivers/iommu/intel_irq_remapping.c | 108 --- include/linux/dmar.h| 75 +++-- 4 files changed, 753 insertions(+), 425 deletions(-) Hi, Jiang, What is relationship between your two patchset with my iommu hotplug patchset? https://lkml.org/lkml/2014/1/2/527 or yours will just replace mine? Thanks Yinghai ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [Patch Part2 V1 00/14] Enhance DMAR drivers to handle PCI/memory hotplug events
On 2014/1/9 4:43, Yinghai Lu wrote: On Tue, Jan 7, 2014 at 1:00 AM, Jiang Liu jiang@linux.intel.com wrote: Intel DMA/interrupt remapping drivers scan available PCI/memory devices at startup and cache discovered hardware topologies. They don't update cached information if PCI/memory hotplug event happens at runtime, then the stale information may break DMA/interrupt remapping logic. This patchset first (Patch 1-8) tries to introduces some helper functions and fixes several bugs, then (Patch 9,10) uses a global rwsem and RCU to protect global DMA/interrupt remapping data structures, and finally (Patch 11-14) hook PCI/memory hotplug events to update cached information. It's also a preparation for supporting of DMA/interrupt remapping hotplug. Jiang Liu (14): iommu/vt-d: factor out dmar_alloc_dev_scope() for later reuse iommu/vt-d: move private structures and variables into intel-iommu.c iommu/vt-d: simplify function get_domain_for_dev() iommu/vt-d: free resources if failed to create domain for PCIe endpoint iommu/vt-d: create device_domain_info structure for intermediate P2P bridges iommu/vt-d: fix incorrect iommu_count for si_domain iommu/vt-d: fix error in detect ATS capability iommu/vt-d: introduce macro for_each_dev_scope() to walk device scope entries iommu/vt-d: introduce a rwsem to protect global data structures iommu/vt-d: use RCU to protect global resources in interrupt context iommu/vt-d, PCI: update DRHD/RMRR/ATSR device scope caches when PCI hotplug happens iommu/vt-d, PCI: unify the way to process DMAR device scope array iommu/vt-d: update device to static identity domain mapping for PCI hotplug iommu/vt-d: update IOMMU state when memory hotplug happens drivers/iommu/dmar.c| 412 + drivers/iommu/intel-iommu.c | 583 +-- drivers/iommu/intel_irq_remapping.c | 108 --- include/linux/dmar.h| 75 +++-- 4 files changed, 753 insertions(+), 425 deletions(-) Hi, Jiang, What is relationship between your two patchset with my iommu hotplug patchset? https://lkml.org/lkml/2014/1/2/527 or yours will just replace mine? Hi Yinghai, I have reviewed your v2 patch set, I think we are doing the same task. If you agree, I will try to combine our two versions. Thanks! Gerry Thanks Yinghai ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 4/6] iommu/tegra124: smmu: support more than 32 bit pa
On 01/08/2014 09:45 PM, Thierry Reding wrote:
On Tue, Jan 07, 2014 at 01:25:37PM +0800, Mark Zhang wrote:
On 12/05/2013 08:25 PM, Hiroshi Doyu wrote:
[...]
@@ -526,6 +530,21 @@ static int smmu_setup_regs(struct smmu_device *smmu)
return 0;
}
+static void flush_ptc_by_addr(struct smmu_device *smmu, unsigned long *pte,
+ struct page *page)
+{
+ u32 val;
+
+ val = VA_PAGE_TO_PA_HI(pte, page);
+ if (val)
+ smmu_write(smmu, val, SMMU_PTC_FLUSH_1);
+
This is not correct, according to my tests. We should write
SMMU_PTC_FLUSH_1 even when the val is zero.
So I just copied Pavan's original work here, after applied this, the
SMMU works correctly:
- val = VA_PAGE_TO_PA_HI(pte, page);
- if (val)
+ if (!pte) {
+ smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
+ return;
+ }
+
+ if (of_machine_is_compatible(nvidia,tegra124)) {
This check should be replaced by some flag so we don't have to compare
strings every time the PTC is flushed.
Yes, I believe Hiroshi will consider this in his v8 series.
Mark
Thierry
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Re: [Patch Part2 V1 07/14] iommu/vt-d: fix error in detect ATS capability
This is a issue, our BIOS also supports several ATSR which have the same segment. Good fix :) On 2014/1/7 17:00, Jiang Liu wrote: Current Intel IOMMU driver only matches a PCIe root port with the first DRHD unit with the samge segment number. It will report false result if there are multiple DRHD units with the same segment number, thus fail to detect ATS capability for some PCIe devices. This patch refines function dmar_find_matched_atsr_unit() to search all DRHD units with the same segment number. An example DMAR table entries as below: [1D0h 0464 2]Subtable Type : 0002 Root Port ATS Capability [1D2h 0466 2] Length : 0028 [1D4h 0468 1]Flags : 00 [1D5h 0469 1] Reserved : 00 [1D6h 0470 2] PCI Segment Number : [1D8h 0472 1] Device Scope Entry Type : 02 [1D9h 0473 1] Entry Length : 08 [1DAh 0474 2] Reserved : [1DCh 0476 1] Enumeration ID : 00 [1DDh 0477 1] PCI Bus Number : 00 [1DEh 0478 2] PCI Path : [02, 00] [1E0h 0480 1] Device Scope Entry Type : 02 [1E1h 0481 1] Entry Length : 08 [1E2h 0482 2] Reserved : [1E4h 0484 1] Enumeration ID : 00 [1E5h 0485 1] PCI Bus Number : 00 [1E6h 0486 2] PCI Path : [03, 00] [1E8h 0488 1] Device Scope Entry Type : 02 [1E9h 0489 1] Entry Length : 08 [1EAh 0490 2] Reserved : [1ECh 0492 1] Enumeration ID : 00 [1EDh 0493 1] PCI Bus Number : 00 [1EEh 0494 2] PCI Path : [03, 02] [1F0h 0496 1] Device Scope Entry Type : 02 [1F1h 0497 1] Entry Length : 08 [1F2h 0498 2] Reserved : [1F4h 0500 1] Enumeration ID : 00 [1F5h 0501 1] PCI Bus Number : 00 [1F6h 0502 2] PCI Path : [03, 03] [1F8h 0504 2]Subtable Type : 0002 Root Port ATS Capability [1FAh 0506 2] Length : 0020 [1FCh 0508 1]Flags : 00 [1FDh 0509 1] Reserved : 00 [1FEh 0510 2] PCI Segment Number : [200h 0512 1] Device Scope Entry Type : 02 [201h 0513 1] Entry Length : 08 [202h 0514 2] Reserved : [204h 0516 1] Enumeration ID : 00 [205h 0517 1] PCI Bus Number : 40 [206h 0518 2] PCI Path : [02, 00] [208h 0520 1] Device Scope Entry Type : 02 [209h 0521 1] Entry Length : 08 [20Ah 0522 2] Reserved : [20Ch 0524 1] Enumeration ID : 00 [20Dh 0525 1] PCI Bus Number : 40 [20Eh 0526 2] PCI Path : [02, 02] [210h 0528 1] Device Scope Entry Type : 02 [211h 0529 1] Entry Length : 08 [212h 0530 2] Reserved : [214h 0532 1] Enumeration ID : 00 [215h 0533 1] PCI Bus Number : 40 [216h 0534 2] PCI Path : [03, 00] [218h 0536 2]Subtable Type : 0002 Root Port ATS Capability [21Ah 0538 2] Length : 0020 [21Ch 0540 1]Flags : 00 [21Dh 0541 1] Reserved : 00 [21Eh 0542 2] PCI Segment Number : [220h 0544 1] Device Scope Entry Type : 02 [221h 0545 1] Entry Length : 08 [222h 0546 2] Reserved : [224h 0548 1] Enumeration ID : 00 [225h 0549 1] PCI Bus Number : 80 [226h 0550 2] PCI Path : [02, 00] [228h 0552 1] Device Scope Entry Type : 02 [229h 0553 1] Entry Length : 08 [22Ah 0554 2] Reserved : [22Ch 0556 1] Enumeration ID : 00 [22Dh 0557 1] PCI Bus Number : 80 [22Eh 0558 2] PCI Path : [02, 02] [230h 0560 1] Device Scope Entry Type : 02 [231h 0561 1] Entry Length : 08 [232h 0562 2] Reserved : [234h 0564 1] Enumeration ID : 00 [235h 0565 1] PCI Bus Number : 80 [236h 0566 2] PCI Path : [03, 00] [238h 0568 2]Subtable Type : 0002 Root Port ATS Capability [23Ah 0570 2] Length : 0020 [23Ch 0572 1]Flags : 00 [23Dh 0573 1] Reserved : 00 [23Eh 0574 2] PCI Segment Number : [240h 0576 1] Device Scope Entry Type : 02 [241h 0577 1] Entry Length : 08 [242h 0578 2] Reserved : [244h 0580 1] Enumeration ID : 00 [245h
[patch] iommu/vt-d: signedness bug in alloc_irte()
index needs to be signed for the error handling to work. I deleted a
little bit of obsolete cruft related to index and start_index as
well.
Fixes: 360eb3c5687e ('iommu/vt-d: use dedicated bitmap to track remapping entry
allocation status')
Signed-off-by: Dan Carpenter dan.carpen...@oracle.com
diff --git a/drivers/iommu/intel_irq_remapping.c
b/drivers/iommu/intel_irq_remapping.c
index 78fba6212ed2..ef5f65dbafe9 100644
--- a/drivers/iommu/intel_irq_remapping.c
+++ b/drivers/iommu/intel_irq_remapping.c
@@ -71,18 +71,13 @@ static int alloc_irte(struct intel_iommu *iommu, int irq,
u16 count)
struct ir_table *table = iommu-ir_table;
struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
struct irq_cfg *cfg = irq_get_chip_data(irq);
- u16 index, start_index;
unsigned int mask = 0;
unsigned long flags;
+ int index;
if (!count || !irq_iommu)
return -1;
- /*
-* start the IRTE search from index 0.
-*/
- index = start_index = 0;
-
if (count 1) {
count = __roundup_pow_of_two(count);
mask = ilog2(count);
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